1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_plane_helper.h> 39 #include <drm/drm_edid.h> 40 41 #include <nvif/class.h> 42 #include <nvif/cl0002.h> 43 #include <nvif/cl5070.h> 44 #include <nvif/cl507d.h> 45 #include <nvif/event.h> 46 47 #include "nouveau_drv.h" 48 #include "nouveau_dma.h" 49 #include "nouveau_gem.h" 50 #include "nouveau_connector.h" 51 #include "nouveau_encoder.h" 52 #include "nouveau_fence.h" 53 #include "nouveau_fbcon.h" 54 55 #include <subdev/bios/dp.h> 56 57 /****************************************************************************** 58 * Atomic state 59 *****************************************************************************/ 60 61 struct nv50_outp_atom { 62 struct list_head head; 63 64 struct drm_encoder *encoder; 65 bool flush_disable; 66 67 union nv50_outp_atom_mask { 68 struct { 69 bool ctrl:1; 70 }; 71 u8 mask; 72 } set, clr; 73 }; 74 75 /****************************************************************************** 76 * EVO channel 77 *****************************************************************************/ 78 79 static int 80 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 81 const s32 *oclass, u8 head, void *data, u32 size, 82 struct nv50_chan *chan) 83 { 84 struct nvif_sclass *sclass; 85 int ret, i, n; 86 87 chan->device = device; 88 89 ret = n = nvif_object_sclass_get(disp, &sclass); 90 if (ret < 0) 91 return ret; 92 93 while (oclass[0]) { 94 for (i = 0; i < n; i++) { 95 if (sclass[i].oclass == oclass[0]) { 96 ret = nvif_object_init(disp, 0, oclass[0], 97 data, size, &chan->user); 98 if (ret == 0) 99 nvif_object_map(&chan->user, NULL, 0); 100 nvif_object_sclass_put(&sclass); 101 return ret; 102 } 103 } 104 oclass++; 105 } 106 107 nvif_object_sclass_put(&sclass); 108 return -ENOSYS; 109 } 110 111 static void 112 nv50_chan_destroy(struct nv50_chan *chan) 113 { 114 nvif_object_fini(&chan->user); 115 } 116 117 /****************************************************************************** 118 * DMA EVO channel 119 *****************************************************************************/ 120 121 void 122 nv50_dmac_destroy(struct nv50_dmac *dmac) 123 { 124 nvif_object_fini(&dmac->vram); 125 nvif_object_fini(&dmac->sync); 126 127 nv50_chan_destroy(&dmac->base); 128 129 nvif_mem_fini(&dmac->push); 130 } 131 132 int 133 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 134 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 135 struct nv50_dmac *dmac) 136 { 137 struct nouveau_cli *cli = (void *)device->object.client; 138 struct nv50_disp_core_channel_dma_v0 *args = data; 139 u8 type = NVIF_MEM_COHERENT; 140 int ret; 141 142 mutex_init(&dmac->lock); 143 144 /* Pascal added support for 47-bit physical addresses, but some 145 * parts of EVO still only accept 40-bit PAs. 146 * 147 * To avoid issues on systems with large amounts of RAM, and on 148 * systems where an IOMMU maps pages at a high address, we need 149 * to allocate push buffers in VRAM instead. 150 * 151 * This appears to match NVIDIA's behaviour on Pascal. 152 */ 153 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 154 type |= NVIF_MEM_VRAM; 155 156 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 157 if (ret) 158 return ret; 159 160 dmac->ptr = dmac->push.object.map.ptr; 161 162 args->pushbuf = nvif_handle(&dmac->push.object); 163 164 ret = nv50_chan_create(device, disp, oclass, head, data, size, 165 &dmac->base); 166 if (ret) 167 return ret; 168 169 if (!syncbuf) 170 return 0; 171 172 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 173 &(struct nv_dma_v0) { 174 .target = NV_DMA_V0_TARGET_VRAM, 175 .access = NV_DMA_V0_ACCESS_RDWR, 176 .start = syncbuf + 0x0000, 177 .limit = syncbuf + 0x0fff, 178 }, sizeof(struct nv_dma_v0), 179 &dmac->sync); 180 if (ret) 181 return ret; 182 183 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 184 &(struct nv_dma_v0) { 185 .target = NV_DMA_V0_TARGET_VRAM, 186 .access = NV_DMA_V0_ACCESS_RDWR, 187 .start = 0, 188 .limit = device->info.ram_user - 1, 189 }, sizeof(struct nv_dma_v0), 190 &dmac->vram); 191 if (ret) 192 return ret; 193 194 return ret; 195 } 196 197 /****************************************************************************** 198 * EVO channel helpers 199 *****************************************************************************/ 200 u32 * 201 evo_wait(struct nv50_dmac *evoc, int nr) 202 { 203 struct nv50_dmac *dmac = evoc; 204 struct nvif_device *device = dmac->base.device; 205 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 206 207 mutex_lock(&dmac->lock); 208 if (put + nr >= (PAGE_SIZE / 4) - 8) { 209 dmac->ptr[put] = 0x20000000; 210 211 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 212 if (nvif_msec(device, 2000, 213 if (!nvif_rd32(&dmac->base.user, 0x0004)) 214 break; 215 ) < 0) { 216 mutex_unlock(&dmac->lock); 217 pr_err("nouveau: evo channel stalled\n"); 218 return NULL; 219 } 220 221 put = 0; 222 } 223 224 return dmac->ptr + put; 225 } 226 227 void 228 evo_kick(u32 *push, struct nv50_dmac *evoc) 229 { 230 struct nv50_dmac *dmac = evoc; 231 232 /* Push buffer fetches are not coherent with BAR1, we need to ensure 233 * writes have been flushed right through to VRAM before writing PUT. 234 */ 235 if (dmac->push.type & NVIF_MEM_VRAM) { 236 struct nvif_device *device = dmac->base.device; 237 nvif_wr32(&device->object, 0x070000, 0x00000001); 238 nvif_msec(device, 2000, 239 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 240 break; 241 ); 242 } 243 244 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 245 mutex_unlock(&dmac->lock); 246 } 247 248 /****************************************************************************** 249 * Output path helpers 250 *****************************************************************************/ 251 static void 252 nv50_outp_release(struct nouveau_encoder *nv_encoder) 253 { 254 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 255 struct { 256 struct nv50_disp_mthd_v1 base; 257 } args = { 258 .base.version = 1, 259 .base.method = NV50_DISP_MTHD_V1_RELEASE, 260 .base.hasht = nv_encoder->dcb->hasht, 261 .base.hashm = nv_encoder->dcb->hashm, 262 }; 263 264 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 265 nv_encoder->or = -1; 266 nv_encoder->link = 0; 267 } 268 269 static int 270 nv50_outp_acquire(struct nouveau_encoder *nv_encoder) 271 { 272 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 273 struct nv50_disp *disp = nv50_disp(drm->dev); 274 struct { 275 struct nv50_disp_mthd_v1 base; 276 struct nv50_disp_acquire_v0 info; 277 } args = { 278 .base.version = 1, 279 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 280 .base.hasht = nv_encoder->dcb->hasht, 281 .base.hashm = nv_encoder->dcb->hashm, 282 }; 283 int ret; 284 285 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 286 if (ret) { 287 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 288 return ret; 289 } 290 291 nv_encoder->or = args.info.or; 292 nv_encoder->link = args.info.link; 293 return 0; 294 } 295 296 static int 297 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 298 struct drm_crtc_state *crtc_state, 299 struct drm_connector_state *conn_state, 300 struct drm_display_mode *native_mode) 301 { 302 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 303 struct drm_display_mode *mode = &crtc_state->mode; 304 struct drm_connector *connector = conn_state->connector; 305 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 306 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 307 308 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 309 asyc->scaler.full = false; 310 if (!native_mode) 311 return 0; 312 313 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 314 switch (connector->connector_type) { 315 case DRM_MODE_CONNECTOR_LVDS: 316 case DRM_MODE_CONNECTOR_eDP: 317 /* Force use of scaler for non-EDID modes. */ 318 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) 319 break; 320 mode = native_mode; 321 asyc->scaler.full = true; 322 break; 323 default: 324 break; 325 } 326 } else { 327 mode = native_mode; 328 } 329 330 if (!drm_mode_equal(adjusted_mode, mode)) { 331 drm_mode_copy(adjusted_mode, mode); 332 crtc_state->mode_changed = true; 333 } 334 335 return 0; 336 } 337 338 static int 339 nv50_outp_atomic_check(struct drm_encoder *encoder, 340 struct drm_crtc_state *crtc_state, 341 struct drm_connector_state *conn_state) 342 { 343 struct nouveau_connector *nv_connector = 344 nouveau_connector(conn_state->connector); 345 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 346 nv_connector->native_mode); 347 } 348 349 /****************************************************************************** 350 * DAC 351 *****************************************************************************/ 352 static void 353 nv50_dac_disable(struct drm_encoder *encoder) 354 { 355 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 356 struct nv50_core *core = nv50_disp(encoder->dev)->core; 357 if (nv_encoder->crtc) 358 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 359 nv_encoder->crtc = NULL; 360 nv50_outp_release(nv_encoder); 361 } 362 363 static void 364 nv50_dac_enable(struct drm_encoder *encoder) 365 { 366 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 367 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 368 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 369 struct nv50_core *core = nv50_disp(encoder->dev)->core; 370 371 nv50_outp_acquire(nv_encoder); 372 373 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 374 asyh->or.depth = 0; 375 376 nv_encoder->crtc = encoder->crtc; 377 } 378 379 static enum drm_connector_status 380 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 381 { 382 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 383 struct nv50_disp *disp = nv50_disp(encoder->dev); 384 struct { 385 struct nv50_disp_mthd_v1 base; 386 struct nv50_disp_dac_load_v0 load; 387 } args = { 388 .base.version = 1, 389 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 390 .base.hasht = nv_encoder->dcb->hasht, 391 .base.hashm = nv_encoder->dcb->hashm, 392 }; 393 int ret; 394 395 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 396 if (args.load.data == 0) 397 args.load.data = 340; 398 399 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 400 if (ret || !args.load.load) 401 return connector_status_disconnected; 402 403 return connector_status_connected; 404 } 405 406 static const struct drm_encoder_helper_funcs 407 nv50_dac_help = { 408 .atomic_check = nv50_outp_atomic_check, 409 .enable = nv50_dac_enable, 410 .disable = nv50_dac_disable, 411 .detect = nv50_dac_detect 412 }; 413 414 static void 415 nv50_dac_destroy(struct drm_encoder *encoder) 416 { 417 drm_encoder_cleanup(encoder); 418 kfree(encoder); 419 } 420 421 static const struct drm_encoder_funcs 422 nv50_dac_func = { 423 .destroy = nv50_dac_destroy, 424 }; 425 426 static int 427 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 428 { 429 struct nouveau_drm *drm = nouveau_drm(connector->dev); 430 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 431 struct nvkm_i2c_bus *bus; 432 struct nouveau_encoder *nv_encoder; 433 struct drm_encoder *encoder; 434 int type = DRM_MODE_ENCODER_DAC; 435 436 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 437 if (!nv_encoder) 438 return -ENOMEM; 439 nv_encoder->dcb = dcbe; 440 441 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 442 if (bus) 443 nv_encoder->i2c = &bus->i2c; 444 445 encoder = to_drm_encoder(nv_encoder); 446 encoder->possible_crtcs = dcbe->heads; 447 encoder->possible_clones = 0; 448 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 449 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 450 drm_encoder_helper_add(encoder, &nv50_dac_help); 451 452 drm_connector_attach_encoder(connector, encoder); 453 return 0; 454 } 455 456 /****************************************************************************** 457 * Audio 458 *****************************************************************************/ 459 static void 460 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 461 { 462 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 463 struct nv50_disp *disp = nv50_disp(encoder->dev); 464 struct { 465 struct nv50_disp_mthd_v1 base; 466 struct nv50_disp_sor_hda_eld_v0 eld; 467 } args = { 468 .base.version = 1, 469 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 470 .base.hasht = nv_encoder->dcb->hasht, 471 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 472 (0x0100 << nv_crtc->index), 473 }; 474 475 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 476 } 477 478 static void 479 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 480 { 481 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 482 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 483 struct nouveau_connector *nv_connector; 484 struct nv50_disp *disp = nv50_disp(encoder->dev); 485 struct __packed { 486 struct { 487 struct nv50_disp_mthd_v1 mthd; 488 struct nv50_disp_sor_hda_eld_v0 eld; 489 } base; 490 u8 data[sizeof(nv_connector->base.eld)]; 491 } args = { 492 .base.mthd.version = 1, 493 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 494 .base.mthd.hasht = nv_encoder->dcb->hasht, 495 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 496 (0x0100 << nv_crtc->index), 497 }; 498 499 nv_connector = nouveau_encoder_connector_get(nv_encoder); 500 if (!drm_detect_monitor_audio(nv_connector->edid)) 501 return; 502 503 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 504 505 nvif_mthd(&disp->disp->object, 0, &args, 506 sizeof(args.base) + drm_eld_size(args.data)); 507 } 508 509 /****************************************************************************** 510 * HDMI 511 *****************************************************************************/ 512 static void 513 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 514 { 515 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 516 struct nv50_disp *disp = nv50_disp(encoder->dev); 517 struct { 518 struct nv50_disp_mthd_v1 base; 519 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 520 } args = { 521 .base.version = 1, 522 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 523 .base.hasht = nv_encoder->dcb->hasht, 524 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 525 (0x0100 << nv_crtc->index), 526 }; 527 528 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 529 } 530 531 static void 532 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 533 { 534 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 535 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 536 struct nv50_disp *disp = nv50_disp(encoder->dev); 537 struct { 538 struct nv50_disp_mthd_v1 base; 539 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 540 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 541 } args = { 542 .base.version = 1, 543 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 544 .base.hasht = nv_encoder->dcb->hasht, 545 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 546 (0x0100 << nv_crtc->index), 547 .pwr.state = 1, 548 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 549 }; 550 struct nouveau_connector *nv_connector; 551 u32 max_ac_packet; 552 union hdmi_infoframe avi_frame; 553 union hdmi_infoframe vendor_frame; 554 int ret; 555 int size; 556 557 nv_connector = nouveau_encoder_connector_get(nv_encoder); 558 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 559 return; 560 561 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode, 562 false); 563 if (!ret) { 564 /* We have an AVI InfoFrame, populate it to the display */ 565 args.pwr.avi_infoframe_length 566 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 567 } 568 569 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 570 &nv_connector->base, mode); 571 if (!ret) { 572 /* We have a Vendor InfoFrame, populate it to the display */ 573 args.pwr.vendor_infoframe_length 574 = hdmi_infoframe_pack(&vendor_frame, 575 args.infoframes 576 + args.pwr.avi_infoframe_length, 577 17); 578 } 579 580 max_ac_packet = mode->htotal - mode->hdisplay; 581 max_ac_packet -= args.pwr.rekey; 582 max_ac_packet -= 18; /* constant from tegra */ 583 args.pwr.max_ac_packet = max_ac_packet / 32; 584 585 size = sizeof(args.base) 586 + sizeof(args.pwr) 587 + args.pwr.avi_infoframe_length 588 + args.pwr.vendor_infoframe_length; 589 nvif_mthd(&disp->disp->object, 0, &args, size); 590 nv50_audio_enable(encoder, mode); 591 } 592 593 /****************************************************************************** 594 * MST 595 *****************************************************************************/ 596 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 597 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 598 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 599 600 struct nv50_mstm { 601 struct nouveau_encoder *outp; 602 603 struct drm_dp_mst_topology_mgr mgr; 604 struct nv50_msto *msto[4]; 605 606 bool modified; 607 bool disabled; 608 int links; 609 }; 610 611 struct nv50_mstc { 612 struct nv50_mstm *mstm; 613 struct drm_dp_mst_port *port; 614 struct drm_connector connector; 615 616 struct drm_display_mode *native; 617 struct edid *edid; 618 619 int pbn; 620 }; 621 622 struct nv50_msto { 623 struct drm_encoder encoder; 624 625 struct nv50_head *head; 626 struct nv50_mstc *mstc; 627 bool disabled; 628 }; 629 630 static struct drm_dp_payload * 631 nv50_msto_payload(struct nv50_msto *msto) 632 { 633 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 634 struct nv50_mstc *mstc = msto->mstc; 635 struct nv50_mstm *mstm = mstc->mstm; 636 int vcpi = mstc->port->vcpi.vcpi, i; 637 638 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 639 for (i = 0; i < mstm->mgr.max_payloads; i++) { 640 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 641 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 642 mstm->outp->base.base.name, i, payload->vcpi, 643 payload->start_slot, payload->num_slots); 644 } 645 646 for (i = 0; i < mstm->mgr.max_payloads; i++) { 647 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 648 if (payload->vcpi == vcpi) 649 return payload; 650 } 651 652 return NULL; 653 } 654 655 static void 656 nv50_msto_cleanup(struct nv50_msto *msto) 657 { 658 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 659 struct nv50_mstc *mstc = msto->mstc; 660 struct nv50_mstm *mstm = mstc->mstm; 661 662 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 663 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto)) 664 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 665 if (msto->disabled) { 666 msto->mstc = NULL; 667 msto->head = NULL; 668 msto->disabled = false; 669 } 670 } 671 672 static void 673 nv50_msto_prepare(struct nv50_msto *msto) 674 { 675 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 676 struct nv50_mstc *mstc = msto->mstc; 677 struct nv50_mstm *mstm = mstc->mstm; 678 struct { 679 struct nv50_disp_mthd_v1 base; 680 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 681 } args = { 682 .base.version = 1, 683 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 684 .base.hasht = mstm->outp->dcb->hasht, 685 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 686 (0x0100 << msto->head->base.index), 687 }; 688 689 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 690 if (mstc->port && mstc->port->vcpi.vcpi > 0) { 691 struct drm_dp_payload *payload = nv50_msto_payload(msto); 692 if (payload) { 693 args.vcpi.start_slot = payload->start_slot; 694 args.vcpi.num_slots = payload->num_slots; 695 args.vcpi.pbn = mstc->port->vcpi.pbn; 696 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 697 } 698 } 699 700 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 701 msto->encoder.name, msto->head->base.base.name, 702 args.vcpi.start_slot, args.vcpi.num_slots, 703 args.vcpi.pbn, args.vcpi.aligned_pbn); 704 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 705 } 706 707 static int 708 nv50_msto_atomic_check(struct drm_encoder *encoder, 709 struct drm_crtc_state *crtc_state, 710 struct drm_connector_state *conn_state) 711 { 712 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector); 713 struct nv50_mstm *mstm = mstc->mstm; 714 int bpp = conn_state->connector->display_info.bpc * 3; 715 int slots; 716 717 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp); 718 719 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 720 if (slots < 0) 721 return slots; 722 723 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 724 mstc->native); 725 } 726 727 static void 728 nv50_msto_enable(struct drm_encoder *encoder) 729 { 730 struct nv50_head *head = nv50_head(encoder->crtc); 731 struct nv50_msto *msto = nv50_msto(encoder); 732 struct nv50_mstc *mstc = NULL; 733 struct nv50_mstm *mstm = NULL; 734 struct drm_connector *connector; 735 struct drm_connector_list_iter conn_iter; 736 u8 proto, depth; 737 int slots; 738 bool r; 739 740 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 741 drm_for_each_connector_iter(connector, &conn_iter) { 742 if (connector->state->best_encoder == &msto->encoder) { 743 mstc = nv50_mstc(connector); 744 mstm = mstc->mstm; 745 break; 746 } 747 } 748 drm_connector_list_iter_end(&conn_iter); 749 750 if (WARN_ON(!mstc)) 751 return; 752 753 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 754 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots); 755 WARN_ON(!r); 756 757 if (!mstm->links++) 758 nv50_outp_acquire(mstm->outp); 759 760 if (mstm->outp->link & 1) 761 proto = 0x8; 762 else 763 proto = 0x9; 764 765 switch (mstc->connector.display_info.bpc) { 766 case 6: depth = 0x2; break; 767 case 8: depth = 0x5; break; 768 case 10: 769 default: depth = 0x6; break; 770 } 771 772 mstm->outp->update(mstm->outp, head->base.index, 773 nv50_head_atom(head->base.base.state), proto, depth); 774 775 msto->head = head; 776 msto->mstc = mstc; 777 mstm->modified = true; 778 } 779 780 static void 781 nv50_msto_disable(struct drm_encoder *encoder) 782 { 783 struct nv50_msto *msto = nv50_msto(encoder); 784 struct nv50_mstc *mstc = msto->mstc; 785 struct nv50_mstm *mstm = mstc->mstm; 786 787 if (mstc->port) 788 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 789 790 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 791 mstm->modified = true; 792 if (!--mstm->links) 793 mstm->disabled = true; 794 msto->disabled = true; 795 } 796 797 static const struct drm_encoder_helper_funcs 798 nv50_msto_help = { 799 .disable = nv50_msto_disable, 800 .enable = nv50_msto_enable, 801 .atomic_check = nv50_msto_atomic_check, 802 }; 803 804 static void 805 nv50_msto_destroy(struct drm_encoder *encoder) 806 { 807 struct nv50_msto *msto = nv50_msto(encoder); 808 drm_encoder_cleanup(&msto->encoder); 809 kfree(msto); 810 } 811 812 static const struct drm_encoder_funcs 813 nv50_msto = { 814 .destroy = nv50_msto_destroy, 815 }; 816 817 static int 818 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, 819 struct nv50_msto **pmsto) 820 { 821 struct nv50_msto *msto; 822 int ret; 823 824 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) 825 return -ENOMEM; 826 827 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 828 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); 829 if (ret) { 830 kfree(*pmsto); 831 *pmsto = NULL; 832 return ret; 833 } 834 835 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 836 msto->encoder.possible_crtcs = heads; 837 return 0; 838 } 839 840 static struct drm_encoder * 841 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 842 struct drm_connector_state *connector_state) 843 { 844 struct nv50_head *head = nv50_head(connector_state->crtc); 845 struct nv50_mstc *mstc = nv50_mstc(connector); 846 if (mstc->port) { 847 struct nv50_mstm *mstm = mstc->mstm; 848 return &mstm->msto[head->base.index]->encoder; 849 } 850 return NULL; 851 } 852 853 static struct drm_encoder * 854 nv50_mstc_best_encoder(struct drm_connector *connector) 855 { 856 struct nv50_mstc *mstc = nv50_mstc(connector); 857 if (mstc->port) { 858 struct nv50_mstm *mstm = mstc->mstm; 859 return &mstm->msto[0]->encoder; 860 } 861 return NULL; 862 } 863 864 static enum drm_mode_status 865 nv50_mstc_mode_valid(struct drm_connector *connector, 866 struct drm_display_mode *mode) 867 { 868 return MODE_OK; 869 } 870 871 static int 872 nv50_mstc_get_modes(struct drm_connector *connector) 873 { 874 struct nv50_mstc *mstc = nv50_mstc(connector); 875 int ret = 0; 876 877 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 878 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 879 if (mstc->edid) 880 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 881 882 if (!mstc->connector.display_info.bpc) 883 mstc->connector.display_info.bpc = 8; 884 885 if (mstc->native) 886 drm_mode_destroy(mstc->connector.dev, mstc->native); 887 mstc->native = nouveau_conn_native_mode(&mstc->connector); 888 return ret; 889 } 890 891 static const struct drm_connector_helper_funcs 892 nv50_mstc_help = { 893 .get_modes = nv50_mstc_get_modes, 894 .mode_valid = nv50_mstc_mode_valid, 895 .best_encoder = nv50_mstc_best_encoder, 896 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 897 }; 898 899 static enum drm_connector_status 900 nv50_mstc_detect(struct drm_connector *connector, bool force) 901 { 902 struct nv50_mstc *mstc = nv50_mstc(connector); 903 if (!mstc->port) 904 return connector_status_disconnected; 905 return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port); 906 } 907 908 static void 909 nv50_mstc_destroy(struct drm_connector *connector) 910 { 911 struct nv50_mstc *mstc = nv50_mstc(connector); 912 drm_connector_cleanup(&mstc->connector); 913 kfree(mstc); 914 } 915 916 static const struct drm_connector_funcs 917 nv50_mstc = { 918 .reset = nouveau_conn_reset, 919 .detect = nv50_mstc_detect, 920 .fill_modes = drm_helper_probe_single_connector_modes, 921 .destroy = nv50_mstc_destroy, 922 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 923 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 924 .atomic_set_property = nouveau_conn_atomic_set_property, 925 .atomic_get_property = nouveau_conn_atomic_get_property, 926 }; 927 928 static int 929 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 930 const char *path, struct nv50_mstc **pmstc) 931 { 932 struct drm_device *dev = mstm->outp->base.base.dev; 933 struct nv50_mstc *mstc; 934 int ret, i; 935 936 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 937 return -ENOMEM; 938 mstc->mstm = mstm; 939 mstc->port = port; 940 941 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 942 DRM_MODE_CONNECTOR_DisplayPort); 943 if (ret) { 944 kfree(*pmstc); 945 *pmstc = NULL; 946 return ret; 947 } 948 949 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 950 951 mstc->connector.funcs->reset(&mstc->connector); 952 nouveau_conn_attach_properties(&mstc->connector); 953 954 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) 955 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); 956 957 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 958 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 959 drm_connector_set_path_property(&mstc->connector, path); 960 return 0; 961 } 962 963 static void 964 nv50_mstm_cleanup(struct nv50_mstm *mstm) 965 { 966 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 967 struct drm_encoder *encoder; 968 int ret; 969 970 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 971 ret = drm_dp_check_act_status(&mstm->mgr); 972 973 ret = drm_dp_update_payload_part2(&mstm->mgr); 974 975 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 976 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 977 struct nv50_msto *msto = nv50_msto(encoder); 978 struct nv50_mstc *mstc = msto->mstc; 979 if (mstc && mstc->mstm == mstm) 980 nv50_msto_cleanup(msto); 981 } 982 } 983 984 mstm->modified = false; 985 } 986 987 static void 988 nv50_mstm_prepare(struct nv50_mstm *mstm) 989 { 990 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 991 struct drm_encoder *encoder; 992 int ret; 993 994 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 995 ret = drm_dp_update_payload_part1(&mstm->mgr); 996 997 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 998 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 999 struct nv50_msto *msto = nv50_msto(encoder); 1000 struct nv50_mstc *mstc = msto->mstc; 1001 if (mstc && mstc->mstm == mstm) 1002 nv50_msto_prepare(msto); 1003 } 1004 } 1005 1006 if (mstm->disabled) { 1007 if (!mstm->links) 1008 nv50_outp_release(mstm->outp); 1009 mstm->disabled = false; 1010 } 1011 } 1012 1013 static void 1014 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr) 1015 { 1016 struct nv50_mstm *mstm = nv50_mstm(mgr); 1017 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev); 1018 } 1019 1020 static void 1021 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 1022 struct drm_connector *connector) 1023 { 1024 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1025 struct nv50_mstc *mstc = nv50_mstc(connector); 1026 1027 drm_connector_unregister(&mstc->connector); 1028 1029 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 1030 1031 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL); 1032 mstc->port = NULL; 1033 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex); 1034 1035 drm_connector_put(&mstc->connector); 1036 } 1037 1038 static void 1039 nv50_mstm_register_connector(struct drm_connector *connector) 1040 { 1041 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1042 1043 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 1044 1045 drm_connector_register(connector); 1046 } 1047 1048 static struct drm_connector * 1049 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1050 struct drm_dp_mst_port *port, const char *path) 1051 { 1052 struct nv50_mstm *mstm = nv50_mstm(mgr); 1053 struct nv50_mstc *mstc; 1054 int ret; 1055 1056 ret = nv50_mstc_new(mstm, port, path, &mstc); 1057 if (ret) { 1058 if (mstc) 1059 mstc->connector.funcs->destroy(&mstc->connector); 1060 return NULL; 1061 } 1062 1063 return &mstc->connector; 1064 } 1065 1066 static const struct drm_dp_mst_topology_cbs 1067 nv50_mstm = { 1068 .add_connector = nv50_mstm_add_connector, 1069 .register_connector = nv50_mstm_register_connector, 1070 .destroy_connector = nv50_mstm_destroy_connector, 1071 .hotplug = nv50_mstm_hotplug, 1072 }; 1073 1074 void 1075 nv50_mstm_service(struct nv50_mstm *mstm) 1076 { 1077 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1078 bool handled = true; 1079 int ret; 1080 u8 esi[8] = {}; 1081 1082 if (!aux) 1083 return; 1084 1085 while (handled) { 1086 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1087 if (ret != 8) { 1088 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1089 return; 1090 } 1091 1092 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1093 if (!handled) 1094 break; 1095 1096 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1097 } 1098 } 1099 1100 void 1101 nv50_mstm_remove(struct nv50_mstm *mstm) 1102 { 1103 if (mstm) 1104 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1105 } 1106 1107 static int 1108 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1109 { 1110 struct nouveau_encoder *outp = mstm->outp; 1111 struct { 1112 struct nv50_disp_mthd_v1 base; 1113 struct nv50_disp_sor_dp_mst_link_v0 mst; 1114 } args = { 1115 .base.version = 1, 1116 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1117 .base.hasht = outp->dcb->hasht, 1118 .base.hashm = outp->dcb->hashm, 1119 .mst.state = state, 1120 }; 1121 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1122 struct nvif_object *disp = &drm->display->disp.object; 1123 int ret; 1124 1125 if (dpcd >= 0x12) { 1126 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd); 1127 if (ret < 0) 1128 return ret; 1129 1130 dpcd &= ~DP_MST_EN; 1131 if (state) 1132 dpcd |= DP_MST_EN; 1133 1134 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd); 1135 if (ret < 0) 1136 return ret; 1137 } 1138 1139 return nvif_mthd(disp, 0, &args, sizeof(args)); 1140 } 1141 1142 int 1143 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1144 { 1145 int ret, state = 0; 1146 1147 if (!mstm) 1148 return 0; 1149 1150 if (dpcd[0] >= 0x12) { 1151 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]); 1152 if (ret < 0) 1153 return ret; 1154 1155 if (!(dpcd[1] & DP_MST_CAP)) 1156 dpcd[0] = 0x11; 1157 else 1158 state = allow; 1159 } 1160 1161 ret = nv50_mstm_enable(mstm, dpcd[0], state); 1162 if (ret) 1163 return ret; 1164 1165 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state); 1166 if (ret) 1167 return nv50_mstm_enable(mstm, dpcd[0], 0); 1168 1169 return mstm->mgr.mst_state; 1170 } 1171 1172 static void 1173 nv50_mstm_fini(struct nv50_mstm *mstm) 1174 { 1175 if (mstm && mstm->mgr.mst_state) 1176 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1177 } 1178 1179 static void 1180 nv50_mstm_init(struct nv50_mstm *mstm) 1181 { 1182 if (mstm && mstm->mgr.mst_state) 1183 drm_dp_mst_topology_mgr_resume(&mstm->mgr); 1184 } 1185 1186 static void 1187 nv50_mstm_del(struct nv50_mstm **pmstm) 1188 { 1189 struct nv50_mstm *mstm = *pmstm; 1190 if (mstm) { 1191 kfree(*pmstm); 1192 *pmstm = NULL; 1193 } 1194 } 1195 1196 static int 1197 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1198 int conn_base_id, struct nv50_mstm **pmstm) 1199 { 1200 const int max_payloads = hweight8(outp->dcb->heads); 1201 struct drm_device *dev = outp->base.base.dev; 1202 struct nv50_mstm *mstm; 1203 int ret, i; 1204 u8 dpcd; 1205 1206 /* This is a workaround for some monitors not functioning 1207 * correctly in MST mode on initial module load. I think 1208 * some bad interaction with the VBIOS may be responsible. 1209 * 1210 * A good ol' off and on again seems to work here ;) 1211 */ 1212 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1213 if (ret >= 0 && dpcd >= 0x12) 1214 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1215 1216 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1217 return -ENOMEM; 1218 mstm->outp = outp; 1219 mstm->mgr.cbs = &nv50_mstm; 1220 1221 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1222 max_payloads, conn_base_id); 1223 if (ret) 1224 return ret; 1225 1226 for (i = 0; i < max_payloads; i++) { 1227 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, 1228 i, &mstm->msto[i]); 1229 if (ret) 1230 return ret; 1231 } 1232 1233 return 0; 1234 } 1235 1236 /****************************************************************************** 1237 * SOR 1238 *****************************************************************************/ 1239 static void 1240 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1241 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1242 { 1243 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1244 struct nv50_core *core = disp->core; 1245 1246 if (!asyh) { 1247 nv_encoder->ctrl &= ~BIT(head); 1248 if (!(nv_encoder->ctrl & 0x0000000f)) 1249 nv_encoder->ctrl = 0; 1250 } else { 1251 nv_encoder->ctrl |= proto << 8; 1252 nv_encoder->ctrl |= BIT(head); 1253 asyh->or.depth = depth; 1254 } 1255 1256 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1257 } 1258 1259 static void 1260 nv50_sor_disable(struct drm_encoder *encoder) 1261 { 1262 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1263 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1264 1265 nv_encoder->crtc = NULL; 1266 1267 if (nv_crtc) { 1268 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1269 u8 pwr; 1270 1271 if (aux) { 1272 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1273 if (ret == 0) { 1274 pwr &= ~DP_SET_POWER_MASK; 1275 pwr |= DP_SET_POWER_D3; 1276 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1277 } 1278 } 1279 1280 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1281 nv50_audio_disable(encoder, nv_crtc); 1282 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1283 nv50_outp_release(nv_encoder); 1284 } 1285 } 1286 1287 static void 1288 nv50_sor_enable(struct drm_encoder *encoder) 1289 { 1290 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1291 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1292 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1293 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1294 struct { 1295 struct nv50_disp_mthd_v1 base; 1296 struct nv50_disp_sor_lvds_script_v0 lvds; 1297 } lvds = { 1298 .base.version = 1, 1299 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1300 .base.hasht = nv_encoder->dcb->hasht, 1301 .base.hashm = nv_encoder->dcb->hashm, 1302 }; 1303 struct nv50_disp *disp = nv50_disp(encoder->dev); 1304 struct drm_device *dev = encoder->dev; 1305 struct nouveau_drm *drm = nouveau_drm(dev); 1306 struct nouveau_connector *nv_connector; 1307 struct nvbios *bios = &drm->vbios; 1308 u8 proto = 0xf; 1309 u8 depth = 0x0; 1310 1311 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1312 nv_encoder->crtc = encoder->crtc; 1313 nv50_outp_acquire(nv_encoder); 1314 1315 switch (nv_encoder->dcb->type) { 1316 case DCB_OUTPUT_TMDS: 1317 if (nv_encoder->link & 1) { 1318 proto = 0x1; 1319 /* Only enable dual-link if: 1320 * - Need to (i.e. rate > 165MHz) 1321 * - DCB says we can 1322 * - Not an HDMI monitor, since there's no dual-link 1323 * on HDMI. 1324 */ 1325 if (mode->clock >= 165000 && 1326 nv_encoder->dcb->duallink_possible && 1327 !drm_detect_hdmi_monitor(nv_connector->edid)) 1328 proto |= 0x4; 1329 } else { 1330 proto = 0x2; 1331 } 1332 1333 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1334 break; 1335 case DCB_OUTPUT_LVDS: 1336 proto = 0x0; 1337 1338 if (bios->fp_no_ddc) { 1339 if (bios->fp.dual_link) 1340 lvds.lvds.script |= 0x0100; 1341 if (bios->fp.if_is_24bit) 1342 lvds.lvds.script |= 0x0200; 1343 } else { 1344 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1345 if (((u8 *)nv_connector->edid)[121] == 2) 1346 lvds.lvds.script |= 0x0100; 1347 } else 1348 if (mode->clock >= bios->fp.duallink_transition_clk) { 1349 lvds.lvds.script |= 0x0100; 1350 } 1351 1352 if (lvds.lvds.script & 0x0100) { 1353 if (bios->fp.strapless_is_24bit & 2) 1354 lvds.lvds.script |= 0x0200; 1355 } else { 1356 if (bios->fp.strapless_is_24bit & 1) 1357 lvds.lvds.script |= 0x0200; 1358 } 1359 1360 if (nv_connector->base.display_info.bpc == 8) 1361 lvds.lvds.script |= 0x0200; 1362 } 1363 1364 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1365 break; 1366 case DCB_OUTPUT_DP: 1367 if (nv_connector->base.display_info.bpc == 6) 1368 depth = 0x2; 1369 else 1370 if (nv_connector->base.display_info.bpc == 8) 1371 depth = 0x5; 1372 else 1373 depth = 0x6; 1374 1375 if (nv_encoder->link & 1) 1376 proto = 0x8; 1377 else 1378 proto = 0x9; 1379 1380 nv50_audio_enable(encoder, mode); 1381 break; 1382 default: 1383 BUG(); 1384 break; 1385 } 1386 1387 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1388 } 1389 1390 static const struct drm_encoder_helper_funcs 1391 nv50_sor_help = { 1392 .atomic_check = nv50_outp_atomic_check, 1393 .enable = nv50_sor_enable, 1394 .disable = nv50_sor_disable, 1395 }; 1396 1397 static void 1398 nv50_sor_destroy(struct drm_encoder *encoder) 1399 { 1400 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1401 nv50_mstm_del(&nv_encoder->dp.mstm); 1402 drm_encoder_cleanup(encoder); 1403 kfree(encoder); 1404 } 1405 1406 static const struct drm_encoder_funcs 1407 nv50_sor_func = { 1408 .destroy = nv50_sor_destroy, 1409 }; 1410 1411 static int 1412 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1413 { 1414 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1415 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1416 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1417 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1418 struct nouveau_encoder *nv_encoder; 1419 struct drm_encoder *encoder; 1420 u8 ver, hdr, cnt, len; 1421 u32 data; 1422 int type, ret; 1423 1424 switch (dcbe->type) { 1425 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1426 case DCB_OUTPUT_TMDS: 1427 case DCB_OUTPUT_DP: 1428 default: 1429 type = DRM_MODE_ENCODER_TMDS; 1430 break; 1431 } 1432 1433 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1434 if (!nv_encoder) 1435 return -ENOMEM; 1436 nv_encoder->dcb = dcbe; 1437 nv_encoder->update = nv50_sor_update; 1438 1439 encoder = to_drm_encoder(nv_encoder); 1440 encoder->possible_crtcs = dcbe->heads; 1441 encoder->possible_clones = 0; 1442 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1443 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1444 drm_encoder_helper_add(encoder, &nv50_sor_help); 1445 1446 drm_connector_attach_encoder(connector, encoder); 1447 1448 if (dcbe->type == DCB_OUTPUT_DP) { 1449 struct nv50_disp *disp = nv50_disp(encoder->dev); 1450 struct nvkm_i2c_aux *aux = 1451 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1452 if (aux) { 1453 if (disp->disp->object.oclass < GF110_DISP) { 1454 /* HW has no support for address-only 1455 * transactions, so we're required to 1456 * use custom I2C-over-AUX code. 1457 */ 1458 nv_encoder->i2c = &aux->i2c; 1459 } else { 1460 nv_encoder->i2c = &nv_connector->aux.ddc; 1461 } 1462 nv_encoder->aux = aux; 1463 } 1464 1465 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && 1466 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) { 1467 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, 1468 nv_connector->base.base.id, 1469 &nv_encoder->dp.mstm); 1470 if (ret) 1471 return ret; 1472 } 1473 } else { 1474 struct nvkm_i2c_bus *bus = 1475 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1476 if (bus) 1477 nv_encoder->i2c = &bus->i2c; 1478 } 1479 1480 return 0; 1481 } 1482 1483 /****************************************************************************** 1484 * PIOR 1485 *****************************************************************************/ 1486 static int 1487 nv50_pior_atomic_check(struct drm_encoder *encoder, 1488 struct drm_crtc_state *crtc_state, 1489 struct drm_connector_state *conn_state) 1490 { 1491 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1492 if (ret) 1493 return ret; 1494 crtc_state->adjusted_mode.clock *= 2; 1495 return 0; 1496 } 1497 1498 static void 1499 nv50_pior_disable(struct drm_encoder *encoder) 1500 { 1501 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1502 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1503 if (nv_encoder->crtc) 1504 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1505 nv_encoder->crtc = NULL; 1506 nv50_outp_release(nv_encoder); 1507 } 1508 1509 static void 1510 nv50_pior_enable(struct drm_encoder *encoder) 1511 { 1512 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1513 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1514 struct nouveau_connector *nv_connector; 1515 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1516 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1517 u8 owner = 1 << nv_crtc->index; 1518 u8 proto; 1519 1520 nv50_outp_acquire(nv_encoder); 1521 1522 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1523 switch (nv_connector->base.display_info.bpc) { 1524 case 10: asyh->or.depth = 0x6; break; 1525 case 8: asyh->or.depth = 0x5; break; 1526 case 6: asyh->or.depth = 0x2; break; 1527 default: asyh->or.depth = 0x0; break; 1528 } 1529 1530 switch (nv_encoder->dcb->type) { 1531 case DCB_OUTPUT_TMDS: 1532 case DCB_OUTPUT_DP: 1533 proto = 0x0; 1534 break; 1535 default: 1536 BUG(); 1537 break; 1538 } 1539 1540 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1541 nv_encoder->crtc = encoder->crtc; 1542 } 1543 1544 static const struct drm_encoder_helper_funcs 1545 nv50_pior_help = { 1546 .atomic_check = nv50_pior_atomic_check, 1547 .enable = nv50_pior_enable, 1548 .disable = nv50_pior_disable, 1549 }; 1550 1551 static void 1552 nv50_pior_destroy(struct drm_encoder *encoder) 1553 { 1554 drm_encoder_cleanup(encoder); 1555 kfree(encoder); 1556 } 1557 1558 static const struct drm_encoder_funcs 1559 nv50_pior_func = { 1560 .destroy = nv50_pior_destroy, 1561 }; 1562 1563 static int 1564 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1565 { 1566 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1567 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1568 struct nvkm_i2c_bus *bus = NULL; 1569 struct nvkm_i2c_aux *aux = NULL; 1570 struct i2c_adapter *ddc; 1571 struct nouveau_encoder *nv_encoder; 1572 struct drm_encoder *encoder; 1573 int type; 1574 1575 switch (dcbe->type) { 1576 case DCB_OUTPUT_TMDS: 1577 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1578 ddc = bus ? &bus->i2c : NULL; 1579 type = DRM_MODE_ENCODER_TMDS; 1580 break; 1581 case DCB_OUTPUT_DP: 1582 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1583 ddc = aux ? &aux->i2c : NULL; 1584 type = DRM_MODE_ENCODER_TMDS; 1585 break; 1586 default: 1587 return -ENODEV; 1588 } 1589 1590 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1591 if (!nv_encoder) 1592 return -ENOMEM; 1593 nv_encoder->dcb = dcbe; 1594 nv_encoder->i2c = ddc; 1595 nv_encoder->aux = aux; 1596 1597 encoder = to_drm_encoder(nv_encoder); 1598 encoder->possible_crtcs = dcbe->heads; 1599 encoder->possible_clones = 0; 1600 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1601 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1602 drm_encoder_helper_add(encoder, &nv50_pior_help); 1603 1604 drm_connector_attach_encoder(connector, encoder); 1605 return 0; 1606 } 1607 1608 /****************************************************************************** 1609 * Atomic 1610 *****************************************************************************/ 1611 1612 static void 1613 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1614 { 1615 struct nouveau_drm *drm = nouveau_drm(state->dev); 1616 struct nv50_disp *disp = nv50_disp(drm->dev); 1617 struct nv50_core *core = disp->core; 1618 struct nv50_mstm *mstm; 1619 struct drm_encoder *encoder; 1620 1621 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1622 1623 drm_for_each_encoder(encoder, drm->dev) { 1624 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1625 mstm = nouveau_encoder(encoder)->dp.mstm; 1626 if (mstm && mstm->modified) 1627 nv50_mstm_prepare(mstm); 1628 } 1629 } 1630 1631 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1632 core->func->update(core, interlock, true); 1633 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1634 disp->core->chan.base.device)) 1635 NV_ERROR(drm, "core notifier timeout\n"); 1636 1637 drm_for_each_encoder(encoder, drm->dev) { 1638 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1639 mstm = nouveau_encoder(encoder)->dp.mstm; 1640 if (mstm && mstm->modified) 1641 nv50_mstm_cleanup(mstm); 1642 } 1643 } 1644 } 1645 1646 static void 1647 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1648 { 1649 struct drm_plane_state *new_plane_state; 1650 struct drm_plane *plane; 1651 int i; 1652 1653 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1654 struct nv50_wndw *wndw = nv50_wndw(plane); 1655 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1656 if (wndw->func->update) 1657 wndw->func->update(wndw, interlock); 1658 } 1659 } 1660 } 1661 1662 static void 1663 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1664 { 1665 struct drm_device *dev = state->dev; 1666 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1667 struct drm_crtc *crtc; 1668 struct drm_plane_state *new_plane_state; 1669 struct drm_plane *plane; 1670 struct nouveau_drm *drm = nouveau_drm(dev); 1671 struct nv50_disp *disp = nv50_disp(dev); 1672 struct nv50_atom *atom = nv50_atom(state); 1673 struct nv50_outp_atom *outp, *outt; 1674 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1675 int i; 1676 1677 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1678 drm_atomic_helper_wait_for_fences(dev, state, false); 1679 drm_atomic_helper_wait_for_dependencies(state); 1680 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1681 1682 if (atom->lock_core) 1683 mutex_lock(&disp->mutex); 1684 1685 /* Disable head(s). */ 1686 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1687 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1688 struct nv50_head *head = nv50_head(crtc); 1689 1690 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1691 asyh->clr.mask, asyh->set.mask); 1692 if (old_crtc_state->active && !new_crtc_state->active) 1693 drm_crtc_vblank_off(crtc); 1694 1695 if (asyh->clr.mask) { 1696 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1697 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1698 } 1699 } 1700 1701 /* Disable plane(s). */ 1702 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1703 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1704 struct nv50_wndw *wndw = nv50_wndw(plane); 1705 1706 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1707 asyw->clr.mask, asyw->set.mask); 1708 if (!asyw->clr.mask) 1709 continue; 1710 1711 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1712 } 1713 1714 /* Disable output path(s). */ 1715 list_for_each_entry(outp, &atom->outp, head) { 1716 const struct drm_encoder_helper_funcs *help; 1717 struct drm_encoder *encoder; 1718 1719 encoder = outp->encoder; 1720 help = encoder->helper_private; 1721 1722 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1723 outp->clr.mask, outp->set.mask); 1724 1725 if (outp->clr.mask) { 1726 help->disable(encoder); 1727 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1728 if (outp->flush_disable) { 1729 nv50_disp_atomic_commit_wndw(state, interlock); 1730 nv50_disp_atomic_commit_core(state, interlock); 1731 memset(interlock, 0x00, sizeof(interlock)); 1732 } 1733 } 1734 } 1735 1736 /* Flush disable. */ 1737 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1738 if (atom->flush_disable) { 1739 nv50_disp_atomic_commit_wndw(state, interlock); 1740 nv50_disp_atomic_commit_core(state, interlock); 1741 memset(interlock, 0x00, sizeof(interlock)); 1742 } 1743 } 1744 1745 /* Update output path(s). */ 1746 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1747 const struct drm_encoder_helper_funcs *help; 1748 struct drm_encoder *encoder; 1749 1750 encoder = outp->encoder; 1751 help = encoder->helper_private; 1752 1753 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 1754 outp->set.mask, outp->clr.mask); 1755 1756 if (outp->set.mask) { 1757 help->enable(encoder); 1758 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1759 } 1760 1761 list_del(&outp->head); 1762 kfree(outp); 1763 } 1764 1765 /* Update head(s). */ 1766 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1767 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1768 struct nv50_head *head = nv50_head(crtc); 1769 1770 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 1771 asyh->set.mask, asyh->clr.mask); 1772 1773 if (asyh->set.mask) { 1774 nv50_head_flush_set(head, asyh); 1775 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1776 } 1777 1778 if (new_crtc_state->active) { 1779 if (!old_crtc_state->active) 1780 drm_crtc_vblank_on(crtc); 1781 if (new_crtc_state->event) 1782 drm_crtc_vblank_get(crtc); 1783 } 1784 } 1785 1786 /* Update plane(s). */ 1787 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1788 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1789 struct nv50_wndw *wndw = nv50_wndw(plane); 1790 1791 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 1792 asyw->set.mask, asyw->clr.mask); 1793 if ( !asyw->set.mask && 1794 (!asyw->clr.mask || atom->flush_disable)) 1795 continue; 1796 1797 nv50_wndw_flush_set(wndw, interlock, asyw); 1798 } 1799 1800 /* Flush update. */ 1801 nv50_disp_atomic_commit_wndw(state, interlock); 1802 1803 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1804 if (interlock[NV50_DISP_INTERLOCK_BASE] || 1805 interlock[NV50_DISP_INTERLOCK_OVLY] || 1806 interlock[NV50_DISP_INTERLOCK_WNDW] || 1807 !atom->state.legacy_cursor_update) 1808 nv50_disp_atomic_commit_core(state, interlock); 1809 else 1810 disp->core->func->update(disp->core, interlock, false); 1811 } 1812 1813 if (atom->lock_core) 1814 mutex_unlock(&disp->mutex); 1815 1816 /* Wait for HW to signal completion. */ 1817 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1818 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1819 struct nv50_wndw *wndw = nv50_wndw(plane); 1820 int ret = nv50_wndw_wait_armed(wndw, asyw); 1821 if (ret) 1822 NV_ERROR(drm, "%s: timeout\n", plane->name); 1823 } 1824 1825 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 1826 if (new_crtc_state->event) { 1827 unsigned long flags; 1828 /* Get correct count/ts if racing with vblank irq */ 1829 if (new_crtc_state->active) 1830 drm_crtc_accurate_vblank_count(crtc); 1831 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1832 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 1833 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1834 1835 new_crtc_state->event = NULL; 1836 if (new_crtc_state->active) 1837 drm_crtc_vblank_put(crtc); 1838 } 1839 } 1840 1841 drm_atomic_helper_commit_hw_done(state); 1842 drm_atomic_helper_cleanup_planes(dev, state); 1843 drm_atomic_helper_commit_cleanup_done(state); 1844 drm_atomic_state_put(state); 1845 } 1846 1847 static void 1848 nv50_disp_atomic_commit_work(struct work_struct *work) 1849 { 1850 struct drm_atomic_state *state = 1851 container_of(work, typeof(*state), commit_work); 1852 nv50_disp_atomic_commit_tail(state); 1853 } 1854 1855 static int 1856 nv50_disp_atomic_commit(struct drm_device *dev, 1857 struct drm_atomic_state *state, bool nonblock) 1858 { 1859 struct nouveau_drm *drm = nouveau_drm(dev); 1860 struct drm_plane_state *new_plane_state; 1861 struct drm_plane *plane; 1862 struct drm_crtc *crtc; 1863 bool active = false; 1864 int ret, i; 1865 1866 ret = pm_runtime_get_sync(dev->dev); 1867 if (ret < 0 && ret != -EACCES) 1868 return ret; 1869 1870 ret = drm_atomic_helper_setup_commit(state, nonblock); 1871 if (ret) 1872 goto done; 1873 1874 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 1875 1876 ret = drm_atomic_helper_prepare_planes(dev, state); 1877 if (ret) 1878 goto done; 1879 1880 if (!nonblock) { 1881 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 1882 if (ret) 1883 goto err_cleanup; 1884 } 1885 1886 ret = drm_atomic_helper_swap_state(state, true); 1887 if (ret) 1888 goto err_cleanup; 1889 1890 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1891 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1892 struct nv50_wndw *wndw = nv50_wndw(plane); 1893 1894 if (asyw->set.image) 1895 nv50_wndw_ntfy_enable(wndw, asyw); 1896 } 1897 1898 drm_atomic_state_get(state); 1899 1900 if (nonblock) 1901 queue_work(system_unbound_wq, &state->commit_work); 1902 else 1903 nv50_disp_atomic_commit_tail(state); 1904 1905 drm_for_each_crtc(crtc, dev) { 1906 if (crtc->state->active) { 1907 if (!drm->have_disp_power_ref) { 1908 drm->have_disp_power_ref = true; 1909 return 0; 1910 } 1911 active = true; 1912 break; 1913 } 1914 } 1915 1916 if (!active && drm->have_disp_power_ref) { 1917 pm_runtime_put_autosuspend(dev->dev); 1918 drm->have_disp_power_ref = false; 1919 } 1920 1921 err_cleanup: 1922 if (ret) 1923 drm_atomic_helper_cleanup_planes(dev, state); 1924 done: 1925 pm_runtime_put_autosuspend(dev->dev); 1926 return ret; 1927 } 1928 1929 static struct nv50_outp_atom * 1930 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 1931 { 1932 struct nv50_outp_atom *outp; 1933 1934 list_for_each_entry(outp, &atom->outp, head) { 1935 if (outp->encoder == encoder) 1936 return outp; 1937 } 1938 1939 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 1940 if (!outp) 1941 return ERR_PTR(-ENOMEM); 1942 1943 list_add(&outp->head, &atom->outp); 1944 outp->encoder = encoder; 1945 return outp; 1946 } 1947 1948 static int 1949 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 1950 struct drm_connector_state *old_connector_state) 1951 { 1952 struct drm_encoder *encoder = old_connector_state->best_encoder; 1953 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1954 struct drm_crtc *crtc; 1955 struct nv50_outp_atom *outp; 1956 1957 if (!(crtc = old_connector_state->crtc)) 1958 return 0; 1959 1960 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 1961 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 1962 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 1963 outp = nv50_disp_outp_atomic_add(atom, encoder); 1964 if (IS_ERR(outp)) 1965 return PTR_ERR(outp); 1966 1967 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1968 outp->flush_disable = true; 1969 atom->flush_disable = true; 1970 } 1971 outp->clr.ctrl = true; 1972 atom->lock_core = true; 1973 } 1974 1975 return 0; 1976 } 1977 1978 static int 1979 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 1980 struct drm_connector_state *connector_state) 1981 { 1982 struct drm_encoder *encoder = connector_state->best_encoder; 1983 struct drm_crtc_state *new_crtc_state; 1984 struct drm_crtc *crtc; 1985 struct nv50_outp_atom *outp; 1986 1987 if (!(crtc = connector_state->crtc)) 1988 return 0; 1989 1990 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 1991 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 1992 outp = nv50_disp_outp_atomic_add(atom, encoder); 1993 if (IS_ERR(outp)) 1994 return PTR_ERR(outp); 1995 1996 outp->set.ctrl = true; 1997 atom->lock_core = true; 1998 } 1999 2000 return 0; 2001 } 2002 2003 static int 2004 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2005 { 2006 struct nv50_atom *atom = nv50_atom(state); 2007 struct drm_connector_state *old_connector_state, *new_connector_state; 2008 struct drm_connector *connector; 2009 struct drm_crtc_state *new_crtc_state; 2010 struct drm_crtc *crtc; 2011 int ret, i; 2012 2013 /* We need to handle colour management on a per-plane basis. */ 2014 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2015 if (new_crtc_state->color_mgmt_changed) { 2016 ret = drm_atomic_add_affected_planes(state, crtc); 2017 if (ret) 2018 return ret; 2019 } 2020 } 2021 2022 ret = drm_atomic_helper_check(dev, state); 2023 if (ret) 2024 return ret; 2025 2026 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2027 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2028 if (ret) 2029 return ret; 2030 2031 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2032 if (ret) 2033 return ret; 2034 } 2035 2036 return 0; 2037 } 2038 2039 static void 2040 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2041 { 2042 struct nv50_atom *atom = nv50_atom(state); 2043 struct nv50_outp_atom *outp, *outt; 2044 2045 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2046 list_del(&outp->head); 2047 kfree(outp); 2048 } 2049 2050 drm_atomic_state_default_clear(state); 2051 } 2052 2053 static void 2054 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2055 { 2056 struct nv50_atom *atom = nv50_atom(state); 2057 drm_atomic_state_default_release(&atom->state); 2058 kfree(atom); 2059 } 2060 2061 static struct drm_atomic_state * 2062 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2063 { 2064 struct nv50_atom *atom; 2065 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2066 drm_atomic_state_init(dev, &atom->state) < 0) { 2067 kfree(atom); 2068 return NULL; 2069 } 2070 INIT_LIST_HEAD(&atom->outp); 2071 return &atom->state; 2072 } 2073 2074 static const struct drm_mode_config_funcs 2075 nv50_disp_func = { 2076 .fb_create = nouveau_user_framebuffer_create, 2077 .output_poll_changed = drm_fb_helper_output_poll_changed, 2078 .atomic_check = nv50_disp_atomic_check, 2079 .atomic_commit = nv50_disp_atomic_commit, 2080 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2081 .atomic_state_clear = nv50_disp_atomic_state_clear, 2082 .atomic_state_free = nv50_disp_atomic_state_free, 2083 }; 2084 2085 /****************************************************************************** 2086 * Init 2087 *****************************************************************************/ 2088 2089 void 2090 nv50_display_fini(struct drm_device *dev) 2091 { 2092 struct nouveau_encoder *nv_encoder; 2093 struct drm_encoder *encoder; 2094 struct drm_plane *plane; 2095 2096 drm_for_each_plane(plane, dev) { 2097 struct nv50_wndw *wndw = nv50_wndw(plane); 2098 if (plane->funcs != &nv50_wndw) 2099 continue; 2100 nv50_wndw_fini(wndw); 2101 } 2102 2103 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2104 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2105 nv_encoder = nouveau_encoder(encoder); 2106 nv50_mstm_fini(nv_encoder->dp.mstm); 2107 } 2108 } 2109 } 2110 2111 int 2112 nv50_display_init(struct drm_device *dev) 2113 { 2114 struct nv50_core *core = nv50_disp(dev)->core; 2115 struct drm_encoder *encoder; 2116 struct drm_plane *plane; 2117 2118 core->func->init(core); 2119 2120 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2121 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2122 struct nouveau_encoder *nv_encoder = 2123 nouveau_encoder(encoder); 2124 nv50_mstm_init(nv_encoder->dp.mstm); 2125 } 2126 } 2127 2128 drm_for_each_plane(plane, dev) { 2129 struct nv50_wndw *wndw = nv50_wndw(plane); 2130 if (plane->funcs != &nv50_wndw) 2131 continue; 2132 nv50_wndw_init(wndw); 2133 } 2134 2135 return 0; 2136 } 2137 2138 void 2139 nv50_display_destroy(struct drm_device *dev) 2140 { 2141 struct nv50_disp *disp = nv50_disp(dev); 2142 2143 nv50_core_del(&disp->core); 2144 2145 nouveau_bo_unmap(disp->sync); 2146 if (disp->sync) 2147 nouveau_bo_unpin(disp->sync); 2148 nouveau_bo_ref(NULL, &disp->sync); 2149 2150 nouveau_display(dev)->priv = NULL; 2151 kfree(disp); 2152 } 2153 2154 int 2155 nv50_display_create(struct drm_device *dev) 2156 { 2157 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2158 struct nouveau_drm *drm = nouveau_drm(dev); 2159 struct dcb_table *dcb = &drm->vbios.dcb; 2160 struct drm_connector *connector, *tmp; 2161 struct nv50_disp *disp; 2162 struct dcb_output *dcbe; 2163 int crtcs, ret, i; 2164 2165 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2166 if (!disp) 2167 return -ENOMEM; 2168 2169 mutex_init(&disp->mutex); 2170 2171 nouveau_display(dev)->priv = disp; 2172 nouveau_display(dev)->dtor = nv50_display_destroy; 2173 nouveau_display(dev)->init = nv50_display_init; 2174 nouveau_display(dev)->fini = nv50_display_fini; 2175 disp->disp = &nouveau_display(dev)->disp; 2176 dev->mode_config.funcs = &nv50_disp_func; 2177 dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP; 2178 2179 /* small shared memory area we use for notifiers and semaphores */ 2180 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2181 0, 0x0000, NULL, NULL, &disp->sync); 2182 if (!ret) { 2183 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2184 if (!ret) { 2185 ret = nouveau_bo_map(disp->sync); 2186 if (ret) 2187 nouveau_bo_unpin(disp->sync); 2188 } 2189 if (ret) 2190 nouveau_bo_ref(NULL, &disp->sync); 2191 } 2192 2193 if (ret) 2194 goto out; 2195 2196 /* allocate master evo channel */ 2197 ret = nv50_core_new(drm, &disp->core); 2198 if (ret) 2199 goto out; 2200 2201 /* create crtc objects to represent the hw heads */ 2202 if (disp->disp->object.oclass >= GV100_DISP) 2203 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2204 else 2205 if (disp->disp->object.oclass >= GF110_DISP) 2206 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2207 else 2208 crtcs = 0x3; 2209 2210 for (i = 0; i < fls(crtcs); i++) { 2211 if (!(crtcs & (1 << i))) 2212 continue; 2213 ret = nv50_head_create(dev, i); 2214 if (ret) 2215 goto out; 2216 } 2217 2218 /* create encoder/connector objects based on VBIOS DCB table */ 2219 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2220 connector = nouveau_connector_create(dev, dcbe->connector); 2221 if (IS_ERR(connector)) 2222 continue; 2223 2224 if (dcbe->location == DCB_LOC_ON_CHIP) { 2225 switch (dcbe->type) { 2226 case DCB_OUTPUT_TMDS: 2227 case DCB_OUTPUT_LVDS: 2228 case DCB_OUTPUT_DP: 2229 ret = nv50_sor_create(connector, dcbe); 2230 break; 2231 case DCB_OUTPUT_ANALOG: 2232 ret = nv50_dac_create(connector, dcbe); 2233 break; 2234 default: 2235 ret = -ENODEV; 2236 break; 2237 } 2238 } else { 2239 ret = nv50_pior_create(connector, dcbe); 2240 } 2241 2242 if (ret) { 2243 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2244 dcbe->location, dcbe->type, 2245 ffs(dcbe->or) - 1, ret); 2246 ret = 0; 2247 } 2248 } 2249 2250 /* cull any connectors we created that don't have an encoder */ 2251 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2252 if (connector->encoder_ids[0]) 2253 continue; 2254 2255 NV_WARN(drm, "%s has no encoders, removing\n", 2256 connector->name); 2257 connector->funcs->destroy(connector); 2258 } 2259 2260 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2261 dev->vblank_disable_immediate = true; 2262 2263 out: 2264 if (ret) 2265 nv50_display_destroy(dev); 2266 return ret; 2267 } 2268