1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 #include <linux/iopoll.h> 35 36 #include <drm/display/drm_dp_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fb_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #include <nvif/push507c.h> 46 47 #include <nvif/class.h> 48 #include <nvif/cl0002.h> 49 #include <nvif/cl5070.h> 50 #include <nvif/event.h> 51 #include <nvif/if0014.h> 52 #include <nvif/timer.h> 53 54 #include <nvhw/class/cl507c.h> 55 #include <nvhw/class/cl507d.h> 56 #include <nvhw/class/cl837d.h> 57 #include <nvhw/class/cl887d.h> 58 #include <nvhw/class/cl907d.h> 59 #include <nvhw/class/cl917d.h> 60 61 #include "nouveau_drv.h" 62 #include "nouveau_dma.h" 63 #include "nouveau_gem.h" 64 #include "nouveau_connector.h" 65 #include "nouveau_encoder.h" 66 #include "nouveau_fence.h" 67 #include "nouveau_fbcon.h" 68 69 #include <subdev/bios/dp.h> 70 71 /****************************************************************************** 72 * EVO channel 73 *****************************************************************************/ 74 75 static int 76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 77 const s32 *oclass, u8 head, void *data, u32 size, 78 struct nv50_chan *chan) 79 { 80 struct nvif_sclass *sclass; 81 int ret, i, n; 82 83 chan->device = device; 84 85 ret = n = nvif_object_sclass_get(disp, &sclass); 86 if (ret < 0) 87 return ret; 88 89 while (oclass[0]) { 90 for (i = 0; i < n; i++) { 91 if (sclass[i].oclass == oclass[0]) { 92 ret = nvif_object_ctor(disp, "kmsChan", 0, 93 oclass[0], data, size, 94 &chan->user); 95 if (ret == 0) 96 nvif_object_map(&chan->user, NULL, 0); 97 nvif_object_sclass_put(&sclass); 98 return ret; 99 } 100 } 101 oclass++; 102 } 103 104 nvif_object_sclass_put(&sclass); 105 return -ENOSYS; 106 } 107 108 static void 109 nv50_chan_destroy(struct nv50_chan *chan) 110 { 111 nvif_object_dtor(&chan->user); 112 } 113 114 /****************************************************************************** 115 * DMA EVO channel 116 *****************************************************************************/ 117 118 void 119 nv50_dmac_destroy(struct nv50_dmac *dmac) 120 { 121 nvif_object_dtor(&dmac->vram); 122 nvif_object_dtor(&dmac->sync); 123 124 nv50_chan_destroy(&dmac->base); 125 126 nvif_mem_dtor(&dmac->_push.mem); 127 } 128 129 static void 130 nv50_dmac_kick(struct nvif_push *push) 131 { 132 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 133 134 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 135 if (dmac->put != dmac->cur) { 136 /* Push buffer fetches are not coherent with BAR1, we need to ensure 137 * writes have been flushed right through to VRAM before writing PUT. 138 */ 139 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 140 struct nvif_device *device = dmac->base.device; 141 nvif_wr32(&device->object, 0x070000, 0x00000001); 142 nvif_msec(device, 2000, 143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 144 break; 145 ); 146 } 147 148 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 149 dmac->put = dmac->cur; 150 } 151 152 push->bgn = push->cur; 153 } 154 155 static int 156 nv50_dmac_free(struct nv50_dmac *dmac) 157 { 158 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 159 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 160 return get - dmac->cur - 5; 161 return dmac->max - dmac->cur; 162 } 163 164 static int 165 nv50_dmac_wind(struct nv50_dmac *dmac) 166 { 167 /* Wait for GET to depart from the beginning of the push buffer to 168 * prevent writing PUT == GET, which would be ignored by HW. 169 */ 170 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 171 if (get == 0) { 172 /* Corner-case, HW idle, but non-committed work pending. */ 173 if (dmac->put == 0) 174 nv50_dmac_kick(dmac->push); 175 176 if (nvif_msec(dmac->base.device, 2000, 177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 178 break; 179 ) < 0) 180 return -ETIMEDOUT; 181 } 182 183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 184 dmac->cur = 0; 185 return 0; 186 } 187 188 static int 189 nv50_dmac_wait(struct nvif_push *push, u32 size) 190 { 191 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 192 int free; 193 194 if (WARN_ON(size > dmac->max)) 195 return -EINVAL; 196 197 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 198 if (dmac->cur + size >= dmac->max) { 199 int ret = nv50_dmac_wind(dmac); 200 if (ret) 201 return ret; 202 203 push->cur = dmac->_push.mem.object.map.ptr; 204 push->cur = push->cur + dmac->cur; 205 nv50_dmac_kick(push); 206 } 207 208 if (nvif_msec(dmac->base.device, 2000, 209 if ((free = nv50_dmac_free(dmac)) >= size) 210 break; 211 ) < 0) { 212 WARN_ON(1); 213 return -ETIMEDOUT; 214 } 215 216 push->bgn = dmac->_push.mem.object.map.ptr; 217 push->bgn = push->bgn + dmac->cur; 218 push->cur = push->bgn; 219 push->end = push->cur + free; 220 return 0; 221 } 222 223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)"); 224 static int nv50_dmac_vram_pushbuf = -1; 225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400); 226 227 int 228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 229 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf, 230 struct nv50_dmac *dmac) 231 { 232 struct nouveau_cli *cli = (void *)device->object.client; 233 struct nvif_disp_chan_v0 *args = data; 234 u8 type = NVIF_MEM_COHERENT; 235 int ret; 236 237 mutex_init(&dmac->lock); 238 239 /* Pascal added support for 47-bit physical addresses, but some 240 * parts of EVO still only accept 40-bit PAs. 241 * 242 * To avoid issues on systems with large amounts of RAM, and on 243 * systems where an IOMMU maps pages at a high address, we need 244 * to allocate push buffers in VRAM instead. 245 * 246 * This appears to match NVIDIA's behaviour on Pascal. 247 */ 248 if ((nv50_dmac_vram_pushbuf > 0) || 249 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) 250 type |= NVIF_MEM_VRAM; 251 252 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 253 &dmac->_push.mem); 254 if (ret) 255 return ret; 256 257 dmac->ptr = dmac->_push.mem.object.map.ptr; 258 dmac->_push.wait = nv50_dmac_wait; 259 dmac->_push.kick = nv50_dmac_kick; 260 dmac->push = &dmac->_push; 261 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 262 dmac->push->cur = dmac->push->bgn; 263 dmac->push->end = dmac->push->bgn; 264 dmac->max = 0x1000/4 - 1; 265 266 /* EVO channels are affected by a HW bug where the last 12 DWORDs 267 * of the push buffer aren't able to be used safely. 268 */ 269 if (disp->oclass < GV100_DISP) 270 dmac->max -= 12; 271 272 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 273 274 ret = nv50_chan_create(device, disp, oclass, head, data, size, 275 &dmac->base); 276 if (ret) 277 return ret; 278 279 if (syncbuf < 0) 280 return 0; 281 282 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 283 NV_DMA_IN_MEMORY, 284 &(struct nv_dma_v0) { 285 .target = NV_DMA_V0_TARGET_VRAM, 286 .access = NV_DMA_V0_ACCESS_RDWR, 287 .start = syncbuf + 0x0000, 288 .limit = syncbuf + 0x0fff, 289 }, sizeof(struct nv_dma_v0), 290 &dmac->sync); 291 if (ret) 292 return ret; 293 294 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 295 NV_DMA_IN_MEMORY, 296 &(struct nv_dma_v0) { 297 .target = NV_DMA_V0_TARGET_VRAM, 298 .access = NV_DMA_V0_ACCESS_RDWR, 299 .start = 0, 300 .limit = device->info.ram_user - 1, 301 }, sizeof(struct nv_dma_v0), 302 &dmac->vram); 303 if (ret) 304 return ret; 305 306 return ret; 307 } 308 309 /****************************************************************************** 310 * Output path helpers 311 *****************************************************************************/ 312 static void 313 nv50_outp_dump_caps(struct nouveau_drm *drm, 314 struct nouveau_encoder *outp) 315 { 316 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n", 317 outp->base.base.name, outp->caps.dp_interlace); 318 } 319 320 static void 321 nv50_outp_release(struct nouveau_encoder *nv_encoder) 322 { 323 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 324 struct { 325 struct nv50_disp_mthd_v1 base; 326 } args = { 327 .base.version = 1, 328 .base.method = NV50_DISP_MTHD_V1_RELEASE, 329 .base.hasht = nv_encoder->dcb->hasht, 330 .base.hashm = nv_encoder->dcb->hashm, 331 }; 332 333 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 334 nv_encoder->or = -1; 335 nv_encoder->link = 0; 336 } 337 338 static int 339 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 340 { 341 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 342 struct nv50_disp *disp = nv50_disp(drm->dev); 343 struct { 344 struct nv50_disp_mthd_v1 base; 345 struct nv50_disp_acquire_v0 info; 346 } args = { 347 .base.version = 1, 348 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 349 .base.hasht = nv_encoder->dcb->hasht, 350 .base.hashm = nv_encoder->dcb->hashm, 351 .info.hda = hda, 352 }; 353 int ret; 354 355 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 356 if (ret) { 357 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 358 return ret; 359 } 360 361 nv_encoder->or = args.info.or; 362 nv_encoder->link = args.info.link; 363 return 0; 364 } 365 366 static int 367 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 368 struct drm_crtc_state *crtc_state, 369 struct drm_connector_state *conn_state, 370 struct drm_display_mode *native_mode) 371 { 372 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 373 struct drm_display_mode *mode = &crtc_state->mode; 374 struct drm_connector *connector = conn_state->connector; 375 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 376 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 377 378 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 379 asyc->scaler.full = false; 380 if (!native_mode) 381 return 0; 382 383 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 384 switch (connector->connector_type) { 385 case DRM_MODE_CONNECTOR_LVDS: 386 case DRM_MODE_CONNECTOR_eDP: 387 /* Don't force scaler for EDID modes with 388 * same size as the native one (e.g. different 389 * refresh rate) 390 */ 391 if (mode->hdisplay == native_mode->hdisplay && 392 mode->vdisplay == native_mode->vdisplay && 393 mode->type & DRM_MODE_TYPE_DRIVER) 394 break; 395 mode = native_mode; 396 asyc->scaler.full = true; 397 break; 398 default: 399 break; 400 } 401 } else { 402 mode = native_mode; 403 } 404 405 if (!drm_mode_equal(adjusted_mode, mode)) { 406 drm_mode_copy(adjusted_mode, mode); 407 crtc_state->mode_changed = true; 408 } 409 410 return 0; 411 } 412 413 static int 414 nv50_outp_atomic_check(struct drm_encoder *encoder, 415 struct drm_crtc_state *crtc_state, 416 struct drm_connector_state *conn_state) 417 { 418 struct drm_connector *connector = conn_state->connector; 419 struct nouveau_connector *nv_connector = nouveau_connector(connector); 420 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 421 int ret; 422 423 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 424 nv_connector->native_mode); 425 if (ret) 426 return ret; 427 428 if (crtc_state->mode_changed || crtc_state->connectors_changed) 429 asyh->or.bpc = connector->display_info.bpc; 430 431 return 0; 432 } 433 434 struct nouveau_connector * 435 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 436 { 437 struct drm_connector *connector; 438 struct drm_connector_state *connector_state; 439 struct drm_encoder *encoder = to_drm_encoder(outp); 440 int i; 441 442 for_each_new_connector_in_state(state, connector, connector_state, i) { 443 if (connector_state->best_encoder == encoder) 444 return nouveau_connector(connector); 445 } 446 447 return NULL; 448 } 449 450 struct nouveau_connector * 451 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 452 { 453 struct drm_connector *connector; 454 struct drm_connector_state *connector_state; 455 struct drm_encoder *encoder = to_drm_encoder(outp); 456 int i; 457 458 for_each_old_connector_in_state(state, connector, connector_state, i) { 459 if (connector_state->best_encoder == encoder) 460 return nouveau_connector(connector); 461 } 462 463 return NULL; 464 } 465 466 static struct nouveau_crtc * 467 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp) 468 { 469 struct drm_crtc *crtc; 470 struct drm_crtc_state *crtc_state; 471 const u32 mask = drm_encoder_mask(&outp->base.base); 472 int i; 473 474 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 475 if (crtc_state->encoder_mask & mask) 476 return nouveau_crtc(crtc); 477 } 478 479 return NULL; 480 } 481 482 /****************************************************************************** 483 * DAC 484 *****************************************************************************/ 485 static void 486 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 487 { 488 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 489 struct nv50_core *core = nv50_disp(encoder->dev)->core; 490 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 491 492 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); 493 nv_encoder->crtc = NULL; 494 nv50_outp_release(nv_encoder); 495 } 496 497 static void 498 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 499 { 500 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 501 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 502 struct nv50_head_atom *asyh = 503 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 504 struct nv50_core *core = nv50_disp(encoder->dev)->core; 505 u32 ctrl = 0; 506 507 switch (nv_crtc->index) { 508 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 509 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 510 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 511 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 512 default: 513 WARN_ON(1); 514 break; 515 } 516 517 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 518 519 nv50_outp_acquire(nv_encoder, false); 520 521 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); 522 asyh->or.depth = 0; 523 524 nv_encoder->crtc = &nv_crtc->base; 525 } 526 527 static enum drm_connector_status 528 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 529 { 530 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 531 u32 loadval; 532 int ret; 533 534 loadval = nouveau_drm(encoder->dev)->vbios.dactestval; 535 if (loadval == 0) 536 loadval = 340; 537 538 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval); 539 if (ret <= 0) 540 return connector_status_disconnected; 541 542 return connector_status_connected; 543 } 544 545 static const struct drm_encoder_helper_funcs 546 nv50_dac_help = { 547 .atomic_check = nv50_outp_atomic_check, 548 .atomic_enable = nv50_dac_atomic_enable, 549 .atomic_disable = nv50_dac_atomic_disable, 550 .detect = nv50_dac_detect 551 }; 552 553 static void 554 nv50_dac_destroy(struct drm_encoder *encoder) 555 { 556 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 557 558 nvif_outp_dtor(&nv_encoder->outp); 559 560 drm_encoder_cleanup(encoder); 561 kfree(encoder); 562 } 563 564 static const struct drm_encoder_funcs 565 nv50_dac_func = { 566 .destroy = nv50_dac_destroy, 567 }; 568 569 static int 570 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 571 { 572 struct nouveau_drm *drm = nouveau_drm(connector->dev); 573 struct nv50_disp *disp = nv50_disp(connector->dev); 574 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 575 struct nvkm_i2c_bus *bus; 576 struct nouveau_encoder *nv_encoder; 577 struct drm_encoder *encoder; 578 int type = DRM_MODE_ENCODER_DAC; 579 580 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 581 if (!nv_encoder) 582 return -ENOMEM; 583 nv_encoder->dcb = dcbe; 584 585 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 586 if (bus) 587 nv_encoder->i2c = &bus->i2c; 588 589 encoder = to_drm_encoder(nv_encoder); 590 encoder->possible_crtcs = dcbe->heads; 591 encoder->possible_clones = 0; 592 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 593 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 594 drm_encoder_helper_add(encoder, &nv50_dac_help); 595 596 drm_connector_attach_encoder(connector, encoder); 597 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 598 } 599 600 /* 601 * audio component binding for ELD notification 602 */ 603 static void 604 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 605 int dev_id) 606 { 607 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 608 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 609 port, dev_id); 610 } 611 612 static int 613 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 614 bool *enabled, unsigned char *buf, int max_bytes) 615 { 616 struct drm_device *drm_dev = dev_get_drvdata(kdev); 617 struct nouveau_drm *drm = nouveau_drm(drm_dev); 618 struct drm_encoder *encoder; 619 struct nouveau_encoder *nv_encoder; 620 struct nouveau_crtc *nv_crtc; 621 int ret = 0; 622 623 *enabled = false; 624 625 mutex_lock(&drm->audio.lock); 626 627 drm_for_each_encoder(encoder, drm->dev) { 628 struct nouveau_connector *nv_connector = NULL; 629 630 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) 631 continue; /* TODO */ 632 633 nv_encoder = nouveau_encoder(encoder); 634 nv_connector = nouveau_connector(nv_encoder->audio.connector); 635 nv_crtc = nouveau_crtc(nv_encoder->crtc); 636 637 if (!nv_crtc || nv_encoder->or != port || nv_crtc->index != dev_id) 638 continue; 639 640 *enabled = nv_encoder->audio.enabled; 641 if (*enabled) { 642 ret = drm_eld_size(nv_connector->base.eld); 643 memcpy(buf, nv_connector->base.eld, 644 min(max_bytes, ret)); 645 } 646 break; 647 } 648 649 mutex_unlock(&drm->audio.lock); 650 651 return ret; 652 } 653 654 static const struct drm_audio_component_ops nv50_audio_component_ops = { 655 .get_eld = nv50_audio_component_get_eld, 656 }; 657 658 static int 659 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 660 void *data) 661 { 662 struct drm_device *drm_dev = dev_get_drvdata(kdev); 663 struct nouveau_drm *drm = nouveau_drm(drm_dev); 664 struct drm_audio_component *acomp = data; 665 666 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 667 return -ENOMEM; 668 669 drm_modeset_lock_all(drm_dev); 670 acomp->ops = &nv50_audio_component_ops; 671 acomp->dev = kdev; 672 drm->audio.component = acomp; 673 drm_modeset_unlock_all(drm_dev); 674 return 0; 675 } 676 677 static void 678 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 679 void *data) 680 { 681 struct drm_device *drm_dev = dev_get_drvdata(kdev); 682 struct nouveau_drm *drm = nouveau_drm(drm_dev); 683 struct drm_audio_component *acomp = data; 684 685 drm_modeset_lock_all(drm_dev); 686 drm->audio.component = NULL; 687 acomp->ops = NULL; 688 acomp->dev = NULL; 689 drm_modeset_unlock_all(drm_dev); 690 } 691 692 static const struct component_ops nv50_audio_component_bind_ops = { 693 .bind = nv50_audio_component_bind, 694 .unbind = nv50_audio_component_unbind, 695 }; 696 697 static void 698 nv50_audio_component_init(struct nouveau_drm *drm) 699 { 700 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 701 return; 702 703 drm->audio.component_registered = true; 704 mutex_init(&drm->audio.lock); 705 } 706 707 static void 708 nv50_audio_component_fini(struct nouveau_drm *drm) 709 { 710 if (!drm->audio.component_registered) 711 return; 712 713 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 714 drm->audio.component_registered = false; 715 mutex_destroy(&drm->audio.lock); 716 } 717 718 /****************************************************************************** 719 * Audio 720 *****************************************************************************/ 721 static void 722 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 723 { 724 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 725 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 726 struct nv50_disp *disp = nv50_disp(encoder->dev); 727 struct { 728 struct nv50_disp_mthd_v1 base; 729 struct nv50_disp_sor_hda_eld_v0 eld; 730 } args = { 731 .base.version = 1, 732 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 733 .base.hasht = nv_encoder->dcb->hasht, 734 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 735 (0x0100 << nv_crtc->index), 736 }; 737 738 mutex_lock(&drm->audio.lock); 739 if (nv_encoder->audio.enabled) { 740 nv_encoder->audio.enabled = false; 741 nv_encoder->audio.connector = NULL; 742 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 743 } 744 mutex_unlock(&drm->audio.lock); 745 746 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 747 nv_crtc->index); 748 } 749 750 static void 751 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 752 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 753 struct drm_display_mode *mode) 754 { 755 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 756 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 757 struct nv50_disp *disp = nv50_disp(encoder->dev); 758 struct __packed { 759 struct { 760 struct nv50_disp_mthd_v1 mthd; 761 struct nv50_disp_sor_hda_eld_v0 eld; 762 } base; 763 u8 data[sizeof(nv_connector->base.eld)]; 764 } args = { 765 .base.mthd.version = 1, 766 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 767 .base.mthd.hasht = nv_encoder->dcb->hasht, 768 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 769 (0x0100 << nv_crtc->index), 770 }; 771 772 if (!drm_detect_monitor_audio(nv_connector->edid)) 773 return; 774 775 mutex_lock(&drm->audio.lock); 776 777 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 778 779 nvif_mthd(&disp->disp->object, 0, &args, 780 sizeof(args.base) + drm_eld_size(args.data)); 781 nv_encoder->audio.enabled = true; 782 nv_encoder->audio.connector = &nv_connector->base; 783 784 mutex_unlock(&drm->audio.lock); 785 786 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 787 nv_crtc->index); 788 } 789 790 /****************************************************************************** 791 * HDMI 792 *****************************************************************************/ 793 static void 794 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 795 { 796 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 797 struct nv50_disp *disp = nv50_disp(encoder->dev); 798 struct { 799 struct nv50_disp_mthd_v1 base; 800 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 801 } args = { 802 .base.version = 1, 803 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 804 .base.hasht = nv_encoder->dcb->hasht, 805 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 806 (0x0100 << nv_crtc->index), 807 }; 808 809 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 810 } 811 812 static void 813 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 814 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 815 struct drm_display_mode *mode) 816 { 817 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 818 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 819 struct nv50_disp *disp = nv50_disp(encoder->dev); 820 struct { 821 struct nv50_disp_mthd_v1 base; 822 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 823 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 824 } args = { 825 .base.version = 1, 826 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 827 .base.hasht = nv_encoder->dcb->hasht, 828 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 829 (0x0100 << nv_crtc->index), 830 .pwr.state = 1, 831 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 832 }; 833 struct drm_hdmi_info *hdmi; 834 u32 max_ac_packet; 835 union hdmi_infoframe avi_frame; 836 union hdmi_infoframe vendor_frame; 837 bool high_tmds_clock_ratio = false, scrambling = false; 838 u8 config; 839 int ret; 840 int size; 841 842 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 843 return; 844 845 hdmi = &nv_connector->base.display_info.hdmi; 846 847 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 848 &nv_connector->base, mode); 849 if (!ret) { 850 drm_hdmi_avi_infoframe_quant_range(&avi_frame.avi, 851 &nv_connector->base, mode, 852 HDMI_QUANTIZATION_RANGE_FULL); 853 /* We have an AVI InfoFrame, populate it to the display */ 854 args.pwr.avi_infoframe_length 855 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 856 } 857 858 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 859 &nv_connector->base, mode); 860 if (!ret) { 861 /* We have a Vendor InfoFrame, populate it to the display */ 862 args.pwr.vendor_infoframe_length 863 = hdmi_infoframe_pack(&vendor_frame, 864 args.infoframes 865 + args.pwr.avi_infoframe_length, 866 17); 867 } 868 869 max_ac_packet = mode->htotal - mode->hdisplay; 870 max_ac_packet -= args.pwr.rekey; 871 max_ac_packet -= 18; /* constant from tegra */ 872 args.pwr.max_ac_packet = max_ac_packet / 32; 873 874 if (hdmi->scdc.scrambling.supported) { 875 high_tmds_clock_ratio = mode->clock > 340000; 876 scrambling = high_tmds_clock_ratio || 877 hdmi->scdc.scrambling.low_rates; 878 } 879 880 args.pwr.scdc = 881 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 882 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 883 884 size = sizeof(args.base) 885 + sizeof(args.pwr) 886 + args.pwr.avi_infoframe_length 887 + args.pwr.vendor_infoframe_length; 888 nvif_mthd(&disp->disp->object, 0, &args, size); 889 890 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 891 892 /* If SCDC is supported by the downstream monitor, update 893 * divider / scrambling settings to what we programmed above. 894 */ 895 if (!hdmi->scdc.scrambling.supported) 896 return; 897 898 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 899 if (ret < 0) { 900 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 901 return; 902 } 903 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 904 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 905 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 906 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 907 if (ret < 0) 908 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 909 config, ret); 910 } 911 912 /****************************************************************************** 913 * MST 914 *****************************************************************************/ 915 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 916 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 917 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 918 919 struct nv50_mstc { 920 struct nv50_mstm *mstm; 921 struct drm_dp_mst_port *port; 922 struct drm_connector connector; 923 924 struct drm_display_mode *native; 925 struct edid *edid; 926 }; 927 928 struct nv50_msto { 929 struct drm_encoder encoder; 930 931 /* head is statically assigned on msto creation */ 932 struct nv50_head *head; 933 struct nv50_mstc *mstc; 934 bool disabled; 935 bool enabled; 936 }; 937 938 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 939 { 940 struct nv50_msto *msto; 941 942 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 943 return nouveau_encoder(encoder); 944 945 msto = nv50_msto(encoder); 946 if (!msto->mstc) 947 return NULL; 948 return msto->mstc->mstm->outp; 949 } 950 951 static void 952 nv50_msto_cleanup(struct drm_atomic_state *state, 953 struct drm_dp_mst_topology_state *mst_state, 954 struct drm_dp_mst_topology_mgr *mgr, 955 struct nv50_msto *msto) 956 { 957 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 958 struct drm_dp_mst_atomic_payload *payload = 959 drm_atomic_get_mst_payload_state(mst_state, msto->mstc->port); 960 961 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 962 963 if (msto->disabled) { 964 msto->mstc = NULL; 965 msto->disabled = false; 966 } else if (msto->enabled) { 967 drm_dp_add_payload_part2(mgr, state, payload); 968 msto->enabled = false; 969 } 970 } 971 972 static void 973 nv50_msto_prepare(struct drm_atomic_state *state, 974 struct drm_dp_mst_topology_state *mst_state, 975 struct drm_dp_mst_topology_mgr *mgr, 976 struct nv50_msto *msto) 977 { 978 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 979 struct nv50_mstc *mstc = msto->mstc; 980 struct nv50_mstm *mstm = mstc->mstm; 981 struct drm_dp_mst_atomic_payload *payload; 982 struct { 983 struct nv50_disp_mthd_v1 base; 984 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 985 } args = { 986 .base.version = 1, 987 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 988 .base.hasht = mstm->outp->dcb->hasht, 989 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 990 (0x0100 << msto->head->base.index), 991 }; 992 993 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 994 995 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port); 996 997 // TODO: Figure out if we want to do a better job of handling VCPI allocation failures here? 998 if (msto->disabled) { 999 drm_dp_remove_payload(mgr, mst_state, payload); 1000 } else { 1001 if (msto->enabled) 1002 drm_dp_add_payload_part1(mgr, mst_state, payload); 1003 1004 args.vcpi.start_slot = payload->vc_start_slot; 1005 args.vcpi.num_slots = payload->time_slots; 1006 args.vcpi.pbn = payload->pbn; 1007 args.vcpi.aligned_pbn = payload->time_slots * mst_state->pbn_div; 1008 } 1009 1010 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 1011 msto->encoder.name, msto->head->base.base.name, 1012 args.vcpi.start_slot, args.vcpi.num_slots, 1013 args.vcpi.pbn, args.vcpi.aligned_pbn); 1014 1015 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 1016 } 1017 1018 static int 1019 nv50_msto_atomic_check(struct drm_encoder *encoder, 1020 struct drm_crtc_state *crtc_state, 1021 struct drm_connector_state *conn_state) 1022 { 1023 struct drm_atomic_state *state = crtc_state->state; 1024 struct drm_connector *connector = conn_state->connector; 1025 struct drm_dp_mst_topology_state *mst_state; 1026 struct nv50_mstc *mstc = nv50_mstc(connector); 1027 struct nv50_mstm *mstm = mstc->mstm; 1028 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 1029 int slots; 1030 int ret; 1031 1032 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 1033 mstc->native); 1034 if (ret) 1035 return ret; 1036 1037 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 1038 return 0; 1039 1040 /* 1041 * When restoring duplicated states, we need to make sure that the bw 1042 * remains the same and avoid recalculating it, as the connector's bpc 1043 * may have changed after the state was duplicated 1044 */ 1045 if (!state->duplicated) { 1046 const int clock = crtc_state->adjusted_mode.clock; 1047 1048 asyh->or.bpc = connector->display_info.bpc; 1049 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 1050 false); 1051 } 1052 1053 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr); 1054 if (IS_ERR(mst_state)) 1055 return PTR_ERR(mst_state); 1056 1057 if (!mst_state->pbn_div) { 1058 struct nouveau_encoder *outp = mstc->mstm->outp; 1059 1060 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr, 1061 outp->dp.link_bw, outp->dp.link_nr); 1062 } 1063 1064 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); 1065 if (slots < 0) 1066 return slots; 1067 1068 asyh->dp.tu = slots; 1069 1070 return 0; 1071 } 1072 1073 static u8 1074 nv50_dp_bpc_to_depth(unsigned int bpc) 1075 { 1076 switch (bpc) { 1077 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1078 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1079 case 10: 1080 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1081 } 1082 } 1083 1084 static void 1085 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1086 { 1087 struct nv50_msto *msto = nv50_msto(encoder); 1088 struct nv50_head *head = msto->head; 1089 struct nv50_head_atom *asyh = 1090 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base)); 1091 struct nv50_mstc *mstc = NULL; 1092 struct nv50_mstm *mstm = NULL; 1093 struct drm_connector *connector; 1094 struct drm_connector_list_iter conn_iter; 1095 u8 proto; 1096 1097 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1098 drm_for_each_connector_iter(connector, &conn_iter) { 1099 if (connector->state->best_encoder == &msto->encoder) { 1100 mstc = nv50_mstc(connector); 1101 mstm = mstc->mstm; 1102 break; 1103 } 1104 } 1105 drm_connector_list_iter_end(&conn_iter); 1106 1107 if (WARN_ON(!mstc)) 1108 return; 1109 1110 if (!mstm->links++) 1111 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 1112 1113 if (mstm->outp->link & 1) 1114 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1115 else 1116 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1117 1118 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, 1119 nv50_dp_bpc_to_depth(asyh->or.bpc)); 1120 1121 msto->mstc = mstc; 1122 msto->enabled = true; 1123 mstm->modified = true; 1124 } 1125 1126 static void 1127 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1128 { 1129 struct nv50_msto *msto = nv50_msto(encoder); 1130 struct nv50_mstc *mstc = msto->mstc; 1131 struct nv50_mstm *mstm = mstc->mstm; 1132 1133 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1134 mstm->modified = true; 1135 if (!--mstm->links) 1136 mstm->disabled = true; 1137 msto->disabled = true; 1138 } 1139 1140 static const struct drm_encoder_helper_funcs 1141 nv50_msto_help = { 1142 .atomic_disable = nv50_msto_atomic_disable, 1143 .atomic_enable = nv50_msto_atomic_enable, 1144 .atomic_check = nv50_msto_atomic_check, 1145 }; 1146 1147 static void 1148 nv50_msto_destroy(struct drm_encoder *encoder) 1149 { 1150 struct nv50_msto *msto = nv50_msto(encoder); 1151 drm_encoder_cleanup(&msto->encoder); 1152 kfree(msto); 1153 } 1154 1155 static const struct drm_encoder_funcs 1156 nv50_msto = { 1157 .destroy = nv50_msto_destroy, 1158 }; 1159 1160 static struct nv50_msto * 1161 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1162 { 1163 struct nv50_msto *msto; 1164 int ret; 1165 1166 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1167 if (!msto) 1168 return ERR_PTR(-ENOMEM); 1169 1170 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1171 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1172 if (ret) { 1173 kfree(msto); 1174 return ERR_PTR(ret); 1175 } 1176 1177 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1178 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1179 msto->head = head; 1180 return msto; 1181 } 1182 1183 static struct drm_encoder * 1184 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1185 struct drm_atomic_state *state) 1186 { 1187 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1188 connector); 1189 struct nv50_mstc *mstc = nv50_mstc(connector); 1190 struct drm_crtc *crtc = connector_state->crtc; 1191 1192 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1193 return NULL; 1194 1195 return &nv50_head(crtc)->msto->encoder; 1196 } 1197 1198 static enum drm_mode_status 1199 nv50_mstc_mode_valid(struct drm_connector *connector, 1200 struct drm_display_mode *mode) 1201 { 1202 struct nv50_mstc *mstc = nv50_mstc(connector); 1203 struct nouveau_encoder *outp = mstc->mstm->outp; 1204 1205 /* TODO: calculate the PBN from the dotclock and validate against the 1206 * MSTB's max possible PBN 1207 */ 1208 1209 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1210 } 1211 1212 static int 1213 nv50_mstc_get_modes(struct drm_connector *connector) 1214 { 1215 struct nv50_mstc *mstc = nv50_mstc(connector); 1216 int ret = 0; 1217 1218 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1219 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1220 if (mstc->edid) 1221 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1222 1223 /* 1224 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1225 * to 8 to save bandwidth on the topology. In the future, we'll want 1226 * to properly fix this by dynamically selecting the highest possible 1227 * bpc that would fit in the topology 1228 */ 1229 if (connector->display_info.bpc) 1230 connector->display_info.bpc = 1231 clamp(connector->display_info.bpc, 6U, 8U); 1232 else 1233 connector->display_info.bpc = 8; 1234 1235 if (mstc->native) 1236 drm_mode_destroy(mstc->connector.dev, mstc->native); 1237 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1238 return ret; 1239 } 1240 1241 static int 1242 nv50_mstc_atomic_check(struct drm_connector *connector, 1243 struct drm_atomic_state *state) 1244 { 1245 struct nv50_mstc *mstc = nv50_mstc(connector); 1246 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1247 1248 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port); 1249 } 1250 1251 static int 1252 nv50_mstc_detect(struct drm_connector *connector, 1253 struct drm_modeset_acquire_ctx *ctx, bool force) 1254 { 1255 struct nv50_mstc *mstc = nv50_mstc(connector); 1256 int ret; 1257 1258 if (drm_connector_is_unregistered(connector)) 1259 return connector_status_disconnected; 1260 1261 ret = pm_runtime_get_sync(connector->dev->dev); 1262 if (ret < 0 && ret != -EACCES) { 1263 pm_runtime_put_autosuspend(connector->dev->dev); 1264 return connector_status_disconnected; 1265 } 1266 1267 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1268 mstc->port); 1269 if (ret != connector_status_connected) 1270 goto out; 1271 1272 out: 1273 pm_runtime_mark_last_busy(connector->dev->dev); 1274 pm_runtime_put_autosuspend(connector->dev->dev); 1275 return ret; 1276 } 1277 1278 static const struct drm_connector_helper_funcs 1279 nv50_mstc_help = { 1280 .get_modes = nv50_mstc_get_modes, 1281 .mode_valid = nv50_mstc_mode_valid, 1282 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1283 .atomic_check = nv50_mstc_atomic_check, 1284 .detect_ctx = nv50_mstc_detect, 1285 }; 1286 1287 static void 1288 nv50_mstc_destroy(struct drm_connector *connector) 1289 { 1290 struct nv50_mstc *mstc = nv50_mstc(connector); 1291 1292 drm_connector_cleanup(&mstc->connector); 1293 drm_dp_mst_put_port_malloc(mstc->port); 1294 1295 kfree(mstc); 1296 } 1297 1298 static const struct drm_connector_funcs 1299 nv50_mstc = { 1300 .reset = nouveau_conn_reset, 1301 .fill_modes = drm_helper_probe_single_connector_modes, 1302 .destroy = nv50_mstc_destroy, 1303 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1304 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1305 .atomic_set_property = nouveau_conn_atomic_set_property, 1306 .atomic_get_property = nouveau_conn_atomic_get_property, 1307 }; 1308 1309 static int 1310 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1311 const char *path, struct nv50_mstc **pmstc) 1312 { 1313 struct drm_device *dev = mstm->outp->base.base.dev; 1314 struct drm_crtc *crtc; 1315 struct nv50_mstc *mstc; 1316 int ret; 1317 1318 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1319 return -ENOMEM; 1320 mstc->mstm = mstm; 1321 mstc->port = port; 1322 1323 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1324 DRM_MODE_CONNECTOR_DisplayPort); 1325 if (ret) { 1326 kfree(*pmstc); 1327 *pmstc = NULL; 1328 return ret; 1329 } 1330 1331 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1332 1333 mstc->connector.funcs->reset(&mstc->connector); 1334 nouveau_conn_attach_properties(&mstc->connector); 1335 1336 drm_for_each_crtc(crtc, dev) { 1337 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1338 continue; 1339 1340 drm_connector_attach_encoder(&mstc->connector, 1341 &nv50_head(crtc)->msto->encoder); 1342 } 1343 1344 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1345 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1346 drm_connector_set_path_property(&mstc->connector, path); 1347 drm_dp_mst_get_port_malloc(port); 1348 return 0; 1349 } 1350 1351 static void 1352 nv50_mstm_cleanup(struct drm_atomic_state *state, 1353 struct drm_dp_mst_topology_state *mst_state, 1354 struct nv50_mstm *mstm) 1355 { 1356 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1357 struct drm_encoder *encoder; 1358 1359 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1360 drm_dp_check_act_status(&mstm->mgr); 1361 1362 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1363 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1364 struct nv50_msto *msto = nv50_msto(encoder); 1365 struct nv50_mstc *mstc = msto->mstc; 1366 if (mstc && mstc->mstm == mstm) 1367 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto); 1368 } 1369 } 1370 1371 mstm->modified = false; 1372 } 1373 1374 static void 1375 nv50_mstm_prepare(struct drm_atomic_state *state, 1376 struct drm_dp_mst_topology_state *mst_state, 1377 struct nv50_mstm *mstm) 1378 { 1379 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1380 struct drm_encoder *encoder; 1381 1382 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1383 1384 /* Disable payloads first */ 1385 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1386 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1387 struct nv50_msto *msto = nv50_msto(encoder); 1388 struct nv50_mstc *mstc = msto->mstc; 1389 if (mstc && mstc->mstm == mstm && msto->disabled) 1390 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); 1391 } 1392 } 1393 1394 /* Add payloads for new heads, while also updating the start slots of any unmodified (but 1395 * active) heads that may have had their VC slots shifted left after the previous step 1396 */ 1397 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1398 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1399 struct nv50_msto *msto = nv50_msto(encoder); 1400 struct nv50_mstc *mstc = msto->mstc; 1401 if (mstc && mstc->mstm == mstm && !msto->disabled) 1402 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); 1403 } 1404 } 1405 1406 if (mstm->disabled) { 1407 if (!mstm->links) 1408 nv50_outp_release(mstm->outp); 1409 mstm->disabled = false; 1410 } 1411 } 1412 1413 static struct drm_connector * 1414 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1415 struct drm_dp_mst_port *port, const char *path) 1416 { 1417 struct nv50_mstm *mstm = nv50_mstm(mgr); 1418 struct nv50_mstc *mstc; 1419 int ret; 1420 1421 ret = nv50_mstc_new(mstm, port, path, &mstc); 1422 if (ret) 1423 return NULL; 1424 1425 return &mstc->connector; 1426 } 1427 1428 static const struct drm_dp_mst_topology_cbs 1429 nv50_mstm = { 1430 .add_connector = nv50_mstm_add_connector, 1431 }; 1432 1433 bool 1434 nv50_mstm_service(struct nouveau_drm *drm, 1435 struct nouveau_connector *nv_connector, 1436 struct nv50_mstm *mstm) 1437 { 1438 struct drm_dp_aux *aux = &nv_connector->aux; 1439 bool handled = true, ret = true; 1440 int rc; 1441 u8 esi[8] = {}; 1442 1443 while (handled) { 1444 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1445 if (rc != 8) { 1446 ret = false; 1447 break; 1448 } 1449 1450 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1451 if (!handled) 1452 break; 1453 1454 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 1455 3); 1456 if (rc != 3) { 1457 ret = false; 1458 break; 1459 } 1460 } 1461 1462 if (!ret) 1463 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1464 nv_connector->base.name, rc); 1465 1466 return ret; 1467 } 1468 1469 void 1470 nv50_mstm_remove(struct nv50_mstm *mstm) 1471 { 1472 mstm->is_mst = false; 1473 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1474 } 1475 1476 static int 1477 nv50_mstm_enable(struct nv50_mstm *mstm, int state) 1478 { 1479 struct nouveau_encoder *outp = mstm->outp; 1480 struct { 1481 struct nv50_disp_mthd_v1 base; 1482 struct nv50_disp_sor_dp_mst_link_v0 mst; 1483 } args = { 1484 .base.version = 1, 1485 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1486 .base.hasht = outp->dcb->hasht, 1487 .base.hashm = outp->dcb->hashm, 1488 .mst.state = state, 1489 }; 1490 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1491 struct nvif_object *disp = &drm->display->disp.object; 1492 1493 return nvif_mthd(disp, 0, &args, sizeof(args)); 1494 } 1495 1496 int 1497 nv50_mstm_detect(struct nouveau_encoder *outp) 1498 { 1499 struct nv50_mstm *mstm = outp->dp.mstm; 1500 struct drm_dp_aux *aux; 1501 int ret; 1502 1503 if (!mstm || !mstm->can_mst) 1504 return 0; 1505 1506 aux = mstm->mgr.aux; 1507 1508 /* Clear any leftover MST state we didn't set ourselves by first 1509 * disabling MST if it was already enabled 1510 */ 1511 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1512 if (ret < 0) 1513 return ret; 1514 1515 /* And start enabling */ 1516 ret = nv50_mstm_enable(mstm, true); 1517 if (ret) 1518 return ret; 1519 1520 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1521 if (ret) { 1522 nv50_mstm_enable(mstm, false); 1523 return ret; 1524 } 1525 1526 mstm->is_mst = true; 1527 return 1; 1528 } 1529 1530 static void 1531 nv50_mstm_fini(struct nouveau_encoder *outp) 1532 { 1533 struct nv50_mstm *mstm = outp->dp.mstm; 1534 1535 if (!mstm) 1536 return; 1537 1538 /* Don't change the MST state of this connector until we've finished 1539 * resuming, since we can't safely grab hpd_irq_lock in our resume 1540 * path to protect mstm->is_mst without potentially deadlocking 1541 */ 1542 mutex_lock(&outp->dp.hpd_irq_lock); 1543 mstm->suspended = true; 1544 mutex_unlock(&outp->dp.hpd_irq_lock); 1545 1546 if (mstm->is_mst) 1547 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1548 } 1549 1550 static void 1551 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1552 { 1553 struct nv50_mstm *mstm = outp->dp.mstm; 1554 int ret = 0; 1555 1556 if (!mstm) 1557 return; 1558 1559 if (mstm->is_mst) { 1560 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1561 if (ret == -1) 1562 nv50_mstm_remove(mstm); 1563 } 1564 1565 mutex_lock(&outp->dp.hpd_irq_lock); 1566 mstm->suspended = false; 1567 mutex_unlock(&outp->dp.hpd_irq_lock); 1568 1569 if (ret == -1) 1570 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1571 } 1572 1573 static void 1574 nv50_mstm_del(struct nv50_mstm **pmstm) 1575 { 1576 struct nv50_mstm *mstm = *pmstm; 1577 if (mstm) { 1578 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1579 kfree(*pmstm); 1580 *pmstm = NULL; 1581 } 1582 } 1583 1584 static int 1585 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1586 int conn_base_id, struct nv50_mstm **pmstm) 1587 { 1588 const int max_payloads = hweight8(outp->dcb->heads); 1589 struct drm_device *dev = outp->base.base.dev; 1590 struct nv50_mstm *mstm; 1591 int ret; 1592 1593 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1594 return -ENOMEM; 1595 mstm->outp = outp; 1596 mstm->mgr.cbs = &nv50_mstm; 1597 1598 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1599 max_payloads, conn_base_id); 1600 if (ret) 1601 return ret; 1602 1603 return 0; 1604 } 1605 1606 /****************************************************************************** 1607 * SOR 1608 *****************************************************************************/ 1609 static void 1610 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1611 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1612 { 1613 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1614 struct nv50_core *core = disp->core; 1615 1616 if (!asyh) { 1617 nv_encoder->ctrl &= ~BIT(head); 1618 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1619 nv_encoder->ctrl = 0; 1620 } else { 1621 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1622 nv_encoder->ctrl |= BIT(head); 1623 asyh->or.depth = depth; 1624 } 1625 1626 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1627 } 1628 1629 /* TODO: Should we extend this to PWM-only backlights? 1630 * As well, should we add a DRM helper for waiting for the backlight to acknowledge 1631 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a 1632 * fixed time delay from the vbios… 1633 */ 1634 static void 1635 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1636 { 1637 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1638 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1639 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder); 1640 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1641 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 1642 struct nouveau_backlight *backlight = nv_connector->backlight; 1643 #endif 1644 struct drm_dp_aux *aux = &nv_connector->aux; 1645 int ret; 1646 u8 pwr; 1647 1648 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1649 if (backlight && backlight->uses_dpcd) { 1650 ret = drm_edp_backlight_disable(aux, &backlight->edp_info); 1651 if (ret < 0) 1652 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n", 1653 nv_connector->base.base.id, nv_connector->base.name, ret); 1654 } 1655 #endif 1656 1657 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1658 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1659 1660 if (ret == 0) { 1661 pwr &= ~DP_SET_POWER_MASK; 1662 pwr |= DP_SET_POWER_D3; 1663 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1664 } 1665 } 1666 1667 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1668 nv50_audio_disable(encoder, nv_crtc); 1669 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1670 nv50_outp_release(nv_encoder); 1671 nv_encoder->crtc = NULL; 1672 } 1673 1674 static void 1675 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1676 { 1677 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1678 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1679 struct nv50_head_atom *asyh = 1680 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1681 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1682 struct { 1683 struct nv50_disp_mthd_v1 base; 1684 struct nv50_disp_sor_lvds_script_v0 lvds; 1685 } lvds = { 1686 .base.version = 1, 1687 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1688 .base.hasht = nv_encoder->dcb->hasht, 1689 .base.hashm = nv_encoder->dcb->hashm, 1690 }; 1691 struct nv50_disp *disp = nv50_disp(encoder->dev); 1692 struct drm_device *dev = encoder->dev; 1693 struct nouveau_drm *drm = nouveau_drm(dev); 1694 struct nouveau_connector *nv_connector; 1695 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1696 struct nouveau_backlight *backlight; 1697 #endif 1698 struct nvbios *bios = &drm->vbios; 1699 bool hda = false; 1700 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1701 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1702 1703 nv_connector = nv50_outp_get_new_connector(state, nv_encoder); 1704 nv_encoder->crtc = &nv_crtc->base; 1705 1706 if ((disp->disp->object.oclass == GT214_DISP || 1707 disp->disp->object.oclass >= GF110_DISP) && 1708 drm_detect_monitor_audio(nv_connector->edid)) 1709 hda = true; 1710 nv50_outp_acquire(nv_encoder, hda); 1711 1712 switch (nv_encoder->dcb->type) { 1713 case DCB_OUTPUT_TMDS: 1714 if (nv_encoder->link & 1) { 1715 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1716 /* Only enable dual-link if: 1717 * - Need to (i.e. rate > 165MHz) 1718 * - DCB says we can 1719 * - Not an HDMI monitor, since there's no dual-link 1720 * on HDMI. 1721 */ 1722 if (mode->clock >= 165000 && 1723 nv_encoder->dcb->duallink_possible && 1724 !drm_detect_hdmi_monitor(nv_connector->edid)) 1725 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1726 } else { 1727 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1728 } 1729 1730 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode); 1731 break; 1732 case DCB_OUTPUT_LVDS: 1733 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1734 1735 if (bios->fp_no_ddc) { 1736 if (bios->fp.dual_link) 1737 lvds.lvds.script |= 0x0100; 1738 if (bios->fp.if_is_24bit) 1739 lvds.lvds.script |= 0x0200; 1740 } else { 1741 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1742 if (((u8 *)nv_connector->edid)[121] == 2) 1743 lvds.lvds.script |= 0x0100; 1744 } else 1745 if (mode->clock >= bios->fp.duallink_transition_clk) { 1746 lvds.lvds.script |= 0x0100; 1747 } 1748 1749 if (lvds.lvds.script & 0x0100) { 1750 if (bios->fp.strapless_is_24bit & 2) 1751 lvds.lvds.script |= 0x0200; 1752 } else { 1753 if (bios->fp.strapless_is_24bit & 1) 1754 lvds.lvds.script |= 0x0200; 1755 } 1756 1757 if (asyh->or.bpc == 8) 1758 lvds.lvds.script |= 0x0200; 1759 } 1760 1761 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1762 break; 1763 case DCB_OUTPUT_DP: 1764 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1765 1766 if (nv_encoder->link & 1) 1767 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1768 else 1769 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1770 1771 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 1772 1773 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1774 backlight = nv_connector->backlight; 1775 if (backlight && backlight->uses_dpcd) 1776 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info, 1777 (u16)backlight->dev->props.brightness); 1778 #endif 1779 1780 break; 1781 default: 1782 BUG(); 1783 break; 1784 } 1785 1786 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1787 } 1788 1789 static const struct drm_encoder_helper_funcs 1790 nv50_sor_help = { 1791 .atomic_check = nv50_outp_atomic_check, 1792 .atomic_enable = nv50_sor_atomic_enable, 1793 .atomic_disable = nv50_sor_atomic_disable, 1794 }; 1795 1796 static void 1797 nv50_sor_destroy(struct drm_encoder *encoder) 1798 { 1799 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1800 1801 nvif_outp_dtor(&nv_encoder->outp); 1802 1803 nv50_mstm_del(&nv_encoder->dp.mstm); 1804 drm_encoder_cleanup(encoder); 1805 1806 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1807 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1808 1809 kfree(encoder); 1810 } 1811 1812 static const struct drm_encoder_funcs 1813 nv50_sor_func = { 1814 .destroy = nv50_sor_destroy, 1815 }; 1816 1817 bool nv50_has_mst(struct nouveau_drm *drm) 1818 { 1819 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1820 u32 data; 1821 u8 ver, hdr, cnt, len; 1822 1823 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1824 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1825 } 1826 1827 static int 1828 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1829 { 1830 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1831 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1832 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1833 struct nouveau_encoder *nv_encoder; 1834 struct drm_encoder *encoder; 1835 struct nv50_disp *disp = nv50_disp(connector->dev); 1836 int type, ret; 1837 1838 switch (dcbe->type) { 1839 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1840 case DCB_OUTPUT_TMDS: 1841 case DCB_OUTPUT_DP: 1842 default: 1843 type = DRM_MODE_ENCODER_TMDS; 1844 break; 1845 } 1846 1847 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1848 if (!nv_encoder) 1849 return -ENOMEM; 1850 nv_encoder->dcb = dcbe; 1851 nv_encoder->update = nv50_sor_update; 1852 1853 encoder = to_drm_encoder(nv_encoder); 1854 encoder->possible_crtcs = dcbe->heads; 1855 encoder->possible_clones = 0; 1856 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1857 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1858 drm_encoder_helper_add(encoder, &nv50_sor_help); 1859 1860 drm_connector_attach_encoder(connector, encoder); 1861 1862 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1863 nv50_outp_dump_caps(drm, nv_encoder); 1864 1865 if (dcbe->type == DCB_OUTPUT_DP) { 1866 struct nvkm_i2c_aux *aux = 1867 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1868 1869 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1870 1871 if (aux) { 1872 if (disp->disp->object.oclass < GF110_DISP) { 1873 /* HW has no support for address-only 1874 * transactions, so we're required to 1875 * use custom I2C-over-AUX code. 1876 */ 1877 nv_encoder->i2c = &aux->i2c; 1878 } else { 1879 nv_encoder->i2c = &nv_connector->aux.ddc; 1880 } 1881 nv_encoder->aux = aux; 1882 } 1883 1884 if (nv_connector->type != DCB_CONNECTOR_eDP && 1885 nv50_has_mst(drm)) { 1886 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1887 16, nv_connector->base.base.id, 1888 &nv_encoder->dp.mstm); 1889 if (ret) 1890 return ret; 1891 } 1892 } else { 1893 struct nvkm_i2c_bus *bus = 1894 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1895 if (bus) 1896 nv_encoder->i2c = &bus->i2c; 1897 } 1898 1899 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 1900 } 1901 1902 /****************************************************************************** 1903 * PIOR 1904 *****************************************************************************/ 1905 static int 1906 nv50_pior_atomic_check(struct drm_encoder *encoder, 1907 struct drm_crtc_state *crtc_state, 1908 struct drm_connector_state *conn_state) 1909 { 1910 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1911 if (ret) 1912 return ret; 1913 crtc_state->adjusted_mode.clock *= 2; 1914 return 0; 1915 } 1916 1917 static void 1918 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1919 { 1920 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1921 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1922 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1923 1924 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); 1925 nv_encoder->crtc = NULL; 1926 nv50_outp_release(nv_encoder); 1927 } 1928 1929 static void 1930 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1931 { 1932 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1933 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1934 struct nv50_head_atom *asyh = 1935 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1936 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1937 u32 ctrl = 0; 1938 1939 switch (nv_crtc->index) { 1940 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1941 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1942 default: 1943 WARN_ON(1); 1944 break; 1945 } 1946 1947 nv50_outp_acquire(nv_encoder, false); 1948 1949 switch (asyh->or.bpc) { 1950 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1951 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1952 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1953 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1954 } 1955 1956 switch (nv_encoder->dcb->type) { 1957 case DCB_OUTPUT_TMDS: 1958 case DCB_OUTPUT_DP: 1959 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1960 break; 1961 default: 1962 BUG(); 1963 break; 1964 } 1965 1966 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); 1967 nv_encoder->crtc = &nv_crtc->base; 1968 } 1969 1970 static const struct drm_encoder_helper_funcs 1971 nv50_pior_help = { 1972 .atomic_check = nv50_pior_atomic_check, 1973 .atomic_enable = nv50_pior_atomic_enable, 1974 .atomic_disable = nv50_pior_atomic_disable, 1975 }; 1976 1977 static void 1978 nv50_pior_destroy(struct drm_encoder *encoder) 1979 { 1980 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1981 1982 nvif_outp_dtor(&nv_encoder->outp); 1983 1984 drm_encoder_cleanup(encoder); 1985 kfree(encoder); 1986 } 1987 1988 static const struct drm_encoder_funcs 1989 nv50_pior_func = { 1990 .destroy = nv50_pior_destroy, 1991 }; 1992 1993 static int 1994 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1995 { 1996 struct drm_device *dev = connector->dev; 1997 struct nouveau_drm *drm = nouveau_drm(dev); 1998 struct nv50_disp *disp = nv50_disp(dev); 1999 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 2000 struct nvkm_i2c_bus *bus = NULL; 2001 struct nvkm_i2c_aux *aux = NULL; 2002 struct i2c_adapter *ddc; 2003 struct nouveau_encoder *nv_encoder; 2004 struct drm_encoder *encoder; 2005 int type; 2006 2007 switch (dcbe->type) { 2008 case DCB_OUTPUT_TMDS: 2009 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 2010 ddc = bus ? &bus->i2c : NULL; 2011 type = DRM_MODE_ENCODER_TMDS; 2012 break; 2013 case DCB_OUTPUT_DP: 2014 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 2015 ddc = aux ? &aux->i2c : NULL; 2016 type = DRM_MODE_ENCODER_TMDS; 2017 break; 2018 default: 2019 return -ENODEV; 2020 } 2021 2022 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 2023 if (!nv_encoder) 2024 return -ENOMEM; 2025 nv_encoder->dcb = dcbe; 2026 nv_encoder->i2c = ddc; 2027 nv_encoder->aux = aux; 2028 2029 encoder = to_drm_encoder(nv_encoder); 2030 encoder->possible_crtcs = dcbe->heads; 2031 encoder->possible_clones = 0; 2032 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 2033 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 2034 drm_encoder_helper_add(encoder, &nv50_pior_help); 2035 2036 drm_connector_attach_encoder(connector, encoder); 2037 2038 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 2039 nv50_outp_dump_caps(drm, nv_encoder); 2040 2041 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 2042 } 2043 2044 /****************************************************************************** 2045 * Atomic 2046 *****************************************************************************/ 2047 2048 static void 2049 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 2050 { 2051 struct drm_dp_mst_topology_mgr *mgr; 2052 struct drm_dp_mst_topology_state *mst_state; 2053 struct nouveau_drm *drm = nouveau_drm(state->dev); 2054 struct nv50_disp *disp = nv50_disp(drm->dev); 2055 struct nv50_core *core = disp->core; 2056 struct nv50_mstm *mstm; 2057 int i; 2058 2059 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 2060 2061 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 2062 mstm = nv50_mstm(mgr); 2063 if (mstm->modified) 2064 nv50_mstm_prepare(state, mst_state, mstm); 2065 } 2066 2067 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 2068 core->func->update(core, interlock, true); 2069 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 2070 disp->core->chan.base.device)) 2071 NV_ERROR(drm, "core notifier timeout\n"); 2072 2073 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 2074 mstm = nv50_mstm(mgr); 2075 if (mstm->modified) 2076 nv50_mstm_cleanup(state, mst_state, mstm); 2077 } 2078 } 2079 2080 static void 2081 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2082 { 2083 struct drm_plane_state *new_plane_state; 2084 struct drm_plane *plane; 2085 int i; 2086 2087 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2088 struct nv50_wndw *wndw = nv50_wndw(plane); 2089 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2090 if (wndw->func->update) 2091 wndw->func->update(wndw, interlock); 2092 } 2093 } 2094 } 2095 2096 static void 2097 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2098 { 2099 struct drm_device *dev = state->dev; 2100 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2101 struct drm_crtc *crtc; 2102 struct drm_plane_state *new_plane_state; 2103 struct drm_plane *plane; 2104 struct nouveau_drm *drm = nouveau_drm(dev); 2105 struct nv50_disp *disp = nv50_disp(dev); 2106 struct nv50_atom *atom = nv50_atom(state); 2107 struct nv50_core *core = disp->core; 2108 struct nv50_outp_atom *outp, *outt; 2109 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2110 int i; 2111 bool flushed = false; 2112 2113 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2114 nv50_crc_atomic_stop_reporting(state); 2115 drm_atomic_helper_wait_for_fences(dev, state, false); 2116 drm_atomic_helper_wait_for_dependencies(state); 2117 drm_dp_mst_atomic_wait_for_dependencies(state); 2118 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2119 drm_atomic_helper_calc_timestamping_constants(state); 2120 2121 if (atom->lock_core) 2122 mutex_lock(&disp->mutex); 2123 2124 /* Disable head(s). */ 2125 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2126 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2127 struct nv50_head *head = nv50_head(crtc); 2128 2129 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2130 asyh->clr.mask, asyh->set.mask); 2131 2132 if (old_crtc_state->active && !new_crtc_state->active) { 2133 pm_runtime_put_noidle(dev->dev); 2134 drm_crtc_vblank_off(crtc); 2135 } 2136 2137 if (asyh->clr.mask) { 2138 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2139 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2140 } 2141 } 2142 2143 /* Disable plane(s). */ 2144 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2145 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2146 struct nv50_wndw *wndw = nv50_wndw(plane); 2147 2148 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2149 asyw->clr.mask, asyw->set.mask); 2150 if (!asyw->clr.mask) 2151 continue; 2152 2153 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2154 } 2155 2156 /* Disable output path(s). */ 2157 list_for_each_entry(outp, &atom->outp, head) { 2158 const struct drm_encoder_helper_funcs *help; 2159 struct drm_encoder *encoder; 2160 2161 encoder = outp->encoder; 2162 help = encoder->helper_private; 2163 2164 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2165 outp->clr.mask, outp->set.mask); 2166 2167 if (outp->clr.mask) { 2168 help->atomic_disable(encoder, state); 2169 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2170 if (outp->flush_disable) { 2171 nv50_disp_atomic_commit_wndw(state, interlock); 2172 nv50_disp_atomic_commit_core(state, interlock); 2173 memset(interlock, 0x00, sizeof(interlock)); 2174 2175 flushed = true; 2176 } 2177 } 2178 } 2179 2180 /* Flush disable. */ 2181 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2182 if (atom->flush_disable) { 2183 nv50_disp_atomic_commit_wndw(state, interlock); 2184 nv50_disp_atomic_commit_core(state, interlock); 2185 memset(interlock, 0x00, sizeof(interlock)); 2186 2187 flushed = true; 2188 } 2189 } 2190 2191 if (flushed) 2192 nv50_crc_atomic_release_notifier_contexts(state); 2193 nv50_crc_atomic_init_notifier_contexts(state); 2194 2195 /* Update output path(s). */ 2196 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2197 const struct drm_encoder_helper_funcs *help; 2198 struct drm_encoder *encoder; 2199 2200 encoder = outp->encoder; 2201 help = encoder->helper_private; 2202 2203 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2204 outp->set.mask, outp->clr.mask); 2205 2206 if (outp->set.mask) { 2207 help->atomic_enable(encoder, state); 2208 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2209 } 2210 2211 list_del(&outp->head); 2212 kfree(outp); 2213 } 2214 2215 /* Update head(s). */ 2216 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2217 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2218 struct nv50_head *head = nv50_head(crtc); 2219 2220 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2221 asyh->set.mask, asyh->clr.mask); 2222 2223 if (asyh->set.mask) { 2224 nv50_head_flush_set(head, asyh); 2225 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2226 } 2227 2228 if (new_crtc_state->active) { 2229 if (!old_crtc_state->active) { 2230 drm_crtc_vblank_on(crtc); 2231 pm_runtime_get_noresume(dev->dev); 2232 } 2233 if (new_crtc_state->event) 2234 drm_crtc_vblank_get(crtc); 2235 } 2236 } 2237 2238 /* Update window->head assignment. 2239 * 2240 * This has to happen in an update that's not interlocked with 2241 * any window channels to avoid hitting HW error checks. 2242 * 2243 *TODO: Proper handling of window ownership (Turing apparently 2244 * supports non-fixed mappings). 2245 */ 2246 if (core->assign_windows) { 2247 core->func->wndw.owner(core); 2248 nv50_disp_atomic_commit_core(state, interlock); 2249 core->assign_windows = false; 2250 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2251 } 2252 2253 /* Finish updating head(s)... 2254 * 2255 * NVD is rather picky about both where window assignments can change, 2256 * *and* about certain core and window channel states matching. 2257 * 2258 * The EFI GOP driver on newer GPUs configures window channels with a 2259 * different output format to what we do, and the core channel update 2260 * in the assign_windows case above would result in a state mismatch. 2261 * 2262 * Delay some of the head update until after that point to workaround 2263 * the issue. This only affects the initial modeset. 2264 * 2265 * TODO: handle this better when adding flexible window mapping 2266 */ 2267 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2268 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2269 struct nv50_head *head = nv50_head(crtc); 2270 2271 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2272 asyh->set.mask, asyh->clr.mask); 2273 2274 if (asyh->set.mask) { 2275 nv50_head_flush_set_wndw(head, asyh); 2276 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2277 } 2278 } 2279 2280 /* Update plane(s). */ 2281 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2282 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2283 struct nv50_wndw *wndw = nv50_wndw(plane); 2284 2285 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2286 asyw->set.mask, asyw->clr.mask); 2287 if ( !asyw->set.mask && 2288 (!asyw->clr.mask || atom->flush_disable)) 2289 continue; 2290 2291 nv50_wndw_flush_set(wndw, interlock, asyw); 2292 } 2293 2294 /* Flush update. */ 2295 nv50_disp_atomic_commit_wndw(state, interlock); 2296 2297 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2298 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2299 interlock[NV50_DISP_INTERLOCK_OVLY] || 2300 interlock[NV50_DISP_INTERLOCK_WNDW] || 2301 !atom->state.legacy_cursor_update) 2302 nv50_disp_atomic_commit_core(state, interlock); 2303 else 2304 disp->core->func->update(disp->core, interlock, false); 2305 } 2306 2307 if (atom->lock_core) 2308 mutex_unlock(&disp->mutex); 2309 2310 /* Wait for HW to signal completion. */ 2311 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2312 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2313 struct nv50_wndw *wndw = nv50_wndw(plane); 2314 int ret = nv50_wndw_wait_armed(wndw, asyw); 2315 if (ret) 2316 NV_ERROR(drm, "%s: timeout\n", plane->name); 2317 } 2318 2319 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2320 if (new_crtc_state->event) { 2321 unsigned long flags; 2322 /* Get correct count/ts if racing with vblank irq */ 2323 if (new_crtc_state->active) 2324 drm_crtc_accurate_vblank_count(crtc); 2325 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2326 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2327 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2328 2329 new_crtc_state->event = NULL; 2330 if (new_crtc_state->active) 2331 drm_crtc_vblank_put(crtc); 2332 } 2333 } 2334 2335 nv50_crc_atomic_start_reporting(state); 2336 if (!flushed) 2337 nv50_crc_atomic_release_notifier_contexts(state); 2338 2339 drm_atomic_helper_commit_hw_done(state); 2340 drm_atomic_helper_cleanup_planes(dev, state); 2341 drm_atomic_helper_commit_cleanup_done(state); 2342 drm_atomic_state_put(state); 2343 2344 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2345 pm_runtime_mark_last_busy(dev->dev); 2346 pm_runtime_put_autosuspend(dev->dev); 2347 } 2348 2349 static void 2350 nv50_disp_atomic_commit_work(struct work_struct *work) 2351 { 2352 struct drm_atomic_state *state = 2353 container_of(work, typeof(*state), commit_work); 2354 nv50_disp_atomic_commit_tail(state); 2355 } 2356 2357 static int 2358 nv50_disp_atomic_commit(struct drm_device *dev, 2359 struct drm_atomic_state *state, bool nonblock) 2360 { 2361 struct drm_plane_state *new_plane_state; 2362 struct drm_plane *plane; 2363 int ret, i; 2364 2365 ret = pm_runtime_get_sync(dev->dev); 2366 if (ret < 0 && ret != -EACCES) { 2367 pm_runtime_put_autosuspend(dev->dev); 2368 return ret; 2369 } 2370 2371 ret = drm_atomic_helper_setup_commit(state, nonblock); 2372 if (ret) 2373 goto done; 2374 2375 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2376 2377 ret = drm_atomic_helper_prepare_planes(dev, state); 2378 if (ret) 2379 goto done; 2380 2381 if (!nonblock) { 2382 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2383 if (ret) 2384 goto err_cleanup; 2385 } 2386 2387 ret = drm_atomic_helper_swap_state(state, true); 2388 if (ret) 2389 goto err_cleanup; 2390 2391 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2392 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2393 struct nv50_wndw *wndw = nv50_wndw(plane); 2394 2395 if (asyw->set.image) 2396 nv50_wndw_ntfy_enable(wndw, asyw); 2397 } 2398 2399 drm_atomic_state_get(state); 2400 2401 /* 2402 * Grab another RPM ref for the commit tail, which will release the 2403 * ref when it's finished 2404 */ 2405 pm_runtime_get_noresume(dev->dev); 2406 2407 if (nonblock) 2408 queue_work(system_unbound_wq, &state->commit_work); 2409 else 2410 nv50_disp_atomic_commit_tail(state); 2411 2412 err_cleanup: 2413 if (ret) 2414 drm_atomic_helper_cleanup_planes(dev, state); 2415 done: 2416 pm_runtime_put_autosuspend(dev->dev); 2417 return ret; 2418 } 2419 2420 static struct nv50_outp_atom * 2421 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2422 { 2423 struct nv50_outp_atom *outp; 2424 2425 list_for_each_entry(outp, &atom->outp, head) { 2426 if (outp->encoder == encoder) 2427 return outp; 2428 } 2429 2430 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2431 if (!outp) 2432 return ERR_PTR(-ENOMEM); 2433 2434 list_add(&outp->head, &atom->outp); 2435 outp->encoder = encoder; 2436 return outp; 2437 } 2438 2439 static int 2440 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2441 struct drm_connector_state *old_connector_state) 2442 { 2443 struct drm_encoder *encoder = old_connector_state->best_encoder; 2444 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2445 struct drm_crtc *crtc; 2446 struct nv50_outp_atom *outp; 2447 2448 if (!(crtc = old_connector_state->crtc)) 2449 return 0; 2450 2451 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2452 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2453 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2454 outp = nv50_disp_outp_atomic_add(atom, encoder); 2455 if (IS_ERR(outp)) 2456 return PTR_ERR(outp); 2457 2458 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2459 outp->flush_disable = true; 2460 atom->flush_disable = true; 2461 } 2462 outp->clr.ctrl = true; 2463 atom->lock_core = true; 2464 } 2465 2466 return 0; 2467 } 2468 2469 static int 2470 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2471 struct drm_connector_state *connector_state) 2472 { 2473 struct drm_encoder *encoder = connector_state->best_encoder; 2474 struct drm_crtc_state *new_crtc_state; 2475 struct drm_crtc *crtc; 2476 struct nv50_outp_atom *outp; 2477 2478 if (!(crtc = connector_state->crtc)) 2479 return 0; 2480 2481 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2482 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2483 outp = nv50_disp_outp_atomic_add(atom, encoder); 2484 if (IS_ERR(outp)) 2485 return PTR_ERR(outp); 2486 2487 outp->set.ctrl = true; 2488 atom->lock_core = true; 2489 } 2490 2491 return 0; 2492 } 2493 2494 static int 2495 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2496 { 2497 struct nv50_atom *atom = nv50_atom(state); 2498 struct nv50_core *core = nv50_disp(dev)->core; 2499 struct drm_connector_state *old_connector_state, *new_connector_state; 2500 struct drm_connector *connector; 2501 struct drm_crtc_state *new_crtc_state; 2502 struct drm_crtc *crtc; 2503 struct nv50_head *head; 2504 struct nv50_head_atom *asyh; 2505 int ret, i; 2506 2507 if (core->assign_windows && core->func->head->static_wndw_map) { 2508 drm_for_each_crtc(crtc, dev) { 2509 new_crtc_state = drm_atomic_get_crtc_state(state, 2510 crtc); 2511 if (IS_ERR(new_crtc_state)) 2512 return PTR_ERR(new_crtc_state); 2513 2514 head = nv50_head(crtc); 2515 asyh = nv50_head_atom(new_crtc_state); 2516 core->func->head->static_wndw_map(head, asyh); 2517 } 2518 } 2519 2520 /* We need to handle colour management on a per-plane basis. */ 2521 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2522 if (new_crtc_state->color_mgmt_changed) { 2523 ret = drm_atomic_add_affected_planes(state, crtc); 2524 if (ret) 2525 return ret; 2526 } 2527 } 2528 2529 ret = drm_atomic_helper_check(dev, state); 2530 if (ret) 2531 return ret; 2532 2533 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2534 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2535 if (ret) 2536 return ret; 2537 2538 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2539 if (ret) 2540 return ret; 2541 } 2542 2543 ret = drm_dp_mst_atomic_check(state); 2544 if (ret) 2545 return ret; 2546 2547 nv50_crc_atomic_check_outp(atom); 2548 2549 return 0; 2550 } 2551 2552 static void 2553 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2554 { 2555 struct nv50_atom *atom = nv50_atom(state); 2556 struct nv50_outp_atom *outp, *outt; 2557 2558 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2559 list_del(&outp->head); 2560 kfree(outp); 2561 } 2562 2563 drm_atomic_state_default_clear(state); 2564 } 2565 2566 static void 2567 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2568 { 2569 struct nv50_atom *atom = nv50_atom(state); 2570 drm_atomic_state_default_release(&atom->state); 2571 kfree(atom); 2572 } 2573 2574 static struct drm_atomic_state * 2575 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2576 { 2577 struct nv50_atom *atom; 2578 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2579 drm_atomic_state_init(dev, &atom->state) < 0) { 2580 kfree(atom); 2581 return NULL; 2582 } 2583 INIT_LIST_HEAD(&atom->outp); 2584 return &atom->state; 2585 } 2586 2587 static const struct drm_mode_config_funcs 2588 nv50_disp_func = { 2589 .fb_create = nouveau_user_framebuffer_create, 2590 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2591 .atomic_check = nv50_disp_atomic_check, 2592 .atomic_commit = nv50_disp_atomic_commit, 2593 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2594 .atomic_state_clear = nv50_disp_atomic_state_clear, 2595 .atomic_state_free = nv50_disp_atomic_state_free, 2596 }; 2597 2598 static const struct drm_mode_config_helper_funcs 2599 nv50_disp_helper_func = { 2600 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 2601 }; 2602 2603 /****************************************************************************** 2604 * Init 2605 *****************************************************************************/ 2606 2607 static void 2608 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2609 { 2610 struct nouveau_drm *drm = nouveau_drm(dev); 2611 struct drm_encoder *encoder; 2612 2613 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2614 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2615 nv50_mstm_fini(nouveau_encoder(encoder)); 2616 } 2617 2618 if (!runtime) 2619 cancel_work_sync(&drm->hpd_work); 2620 } 2621 2622 static int 2623 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2624 { 2625 struct nv50_core *core = nv50_disp(dev)->core; 2626 struct drm_encoder *encoder; 2627 2628 if (resume || runtime) 2629 core->func->init(core); 2630 2631 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2632 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2633 struct nouveau_encoder *nv_encoder = 2634 nouveau_encoder(encoder); 2635 nv50_mstm_init(nv_encoder, runtime); 2636 } 2637 } 2638 2639 return 0; 2640 } 2641 2642 static void 2643 nv50_display_destroy(struct drm_device *dev) 2644 { 2645 struct nv50_disp *disp = nv50_disp(dev); 2646 2647 nv50_audio_component_fini(nouveau_drm(dev)); 2648 2649 nvif_object_unmap(&disp->caps); 2650 nvif_object_dtor(&disp->caps); 2651 nv50_core_del(&disp->core); 2652 2653 nouveau_bo_unmap(disp->sync); 2654 if (disp->sync) 2655 nouveau_bo_unpin(disp->sync); 2656 nouveau_bo_ref(NULL, &disp->sync); 2657 2658 nouveau_display(dev)->priv = NULL; 2659 kfree(disp); 2660 } 2661 2662 int 2663 nv50_display_create(struct drm_device *dev) 2664 { 2665 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2666 struct nouveau_drm *drm = nouveau_drm(dev); 2667 struct dcb_table *dcb = &drm->vbios.dcb; 2668 struct drm_connector *connector, *tmp; 2669 struct nv50_disp *disp; 2670 struct dcb_output *dcbe; 2671 int crtcs, ret, i; 2672 bool has_mst = nv50_has_mst(drm); 2673 2674 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2675 if (!disp) 2676 return -ENOMEM; 2677 2678 mutex_init(&disp->mutex); 2679 2680 nouveau_display(dev)->priv = disp; 2681 nouveau_display(dev)->dtor = nv50_display_destroy; 2682 nouveau_display(dev)->init = nv50_display_init; 2683 nouveau_display(dev)->fini = nv50_display_fini; 2684 disp->disp = &nouveau_display(dev)->disp; 2685 dev->mode_config.funcs = &nv50_disp_func; 2686 dev->mode_config.helper_private = &nv50_disp_helper_func; 2687 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2688 dev->mode_config.normalize_zpos = true; 2689 2690 /* small shared memory area we use for notifiers and semaphores */ 2691 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2692 NOUVEAU_GEM_DOMAIN_VRAM, 2693 0, 0x0000, NULL, NULL, &disp->sync); 2694 if (!ret) { 2695 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2696 if (!ret) { 2697 ret = nouveau_bo_map(disp->sync); 2698 if (ret) 2699 nouveau_bo_unpin(disp->sync); 2700 } 2701 if (ret) 2702 nouveau_bo_ref(NULL, &disp->sync); 2703 } 2704 2705 if (ret) 2706 goto out; 2707 2708 /* allocate master evo channel */ 2709 ret = nv50_core_new(drm, &disp->core); 2710 if (ret) 2711 goto out; 2712 2713 disp->core->func->init(disp->core); 2714 if (disp->core->func->caps_init) { 2715 ret = disp->core->func->caps_init(drm, disp); 2716 if (ret) 2717 goto out; 2718 } 2719 2720 /* Assign the correct format modifiers */ 2721 if (disp->disp->object.oclass >= TU102_DISP) 2722 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2723 else 2724 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2725 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2726 else 2727 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2728 2729 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later 2730 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The 2731 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to 2732 * small page allocations in prepare_fb(). When this is implemented, we should also force 2733 * large pages (128K) for ovly fbs in order to fix Kepler ovlys. 2734 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using 2735 * large pages. 2736 */ 2737 if (disp->disp->object.oclass >= GM107_DISP) { 2738 dev->mode_config.cursor_width = 256; 2739 dev->mode_config.cursor_height = 256; 2740 } else if (disp->disp->object.oclass >= GK104_DISP) { 2741 dev->mode_config.cursor_width = 128; 2742 dev->mode_config.cursor_height = 128; 2743 } else { 2744 dev->mode_config.cursor_width = 64; 2745 dev->mode_config.cursor_height = 64; 2746 } 2747 2748 /* create crtc objects to represent the hw heads */ 2749 if (disp->disp->object.oclass >= GV100_DISP) 2750 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2751 else 2752 if (disp->disp->object.oclass >= GF110_DISP) 2753 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2754 else 2755 crtcs = 0x3; 2756 2757 for (i = 0; i < fls(crtcs); i++) { 2758 struct nv50_head *head; 2759 2760 if (!(crtcs & (1 << i))) 2761 continue; 2762 2763 head = nv50_head_create(dev, i); 2764 if (IS_ERR(head)) { 2765 ret = PTR_ERR(head); 2766 goto out; 2767 } 2768 2769 if (has_mst) { 2770 head->msto = nv50_msto_new(dev, head, i); 2771 if (IS_ERR(head->msto)) { 2772 ret = PTR_ERR(head->msto); 2773 head->msto = NULL; 2774 goto out; 2775 } 2776 2777 /* 2778 * FIXME: This is a hack to workaround the following 2779 * issues: 2780 * 2781 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2782 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2783 * 2784 * Once these issues are closed, this should be 2785 * removed 2786 */ 2787 head->msto->encoder.possible_crtcs = crtcs; 2788 } 2789 } 2790 2791 /* create encoder/connector objects based on VBIOS DCB table */ 2792 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2793 connector = nouveau_connector_create(dev, dcbe); 2794 if (IS_ERR(connector)) 2795 continue; 2796 2797 if (dcbe->location == DCB_LOC_ON_CHIP) { 2798 switch (dcbe->type) { 2799 case DCB_OUTPUT_TMDS: 2800 case DCB_OUTPUT_LVDS: 2801 case DCB_OUTPUT_DP: 2802 ret = nv50_sor_create(connector, dcbe); 2803 break; 2804 case DCB_OUTPUT_ANALOG: 2805 ret = nv50_dac_create(connector, dcbe); 2806 break; 2807 default: 2808 ret = -ENODEV; 2809 break; 2810 } 2811 } else { 2812 ret = nv50_pior_create(connector, dcbe); 2813 } 2814 2815 if (ret) { 2816 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2817 dcbe->location, dcbe->type, 2818 ffs(dcbe->or) - 1, ret); 2819 ret = 0; 2820 } 2821 } 2822 2823 /* cull any connectors we created that don't have an encoder */ 2824 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2825 if (connector->possible_encoders) 2826 continue; 2827 2828 NV_WARN(drm, "%s has no encoders, removing\n", 2829 connector->name); 2830 connector->funcs->destroy(connector); 2831 } 2832 2833 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2834 dev->vblank_disable_immediate = true; 2835 2836 nv50_audio_component_init(drm); 2837 2838 out: 2839 if (ret) 2840 nv50_display_destroy(dev); 2841 return ret; 2842 } 2843 2844 /****************************************************************************** 2845 * Format modifiers 2846 *****************************************************************************/ 2847 2848 /**************************************************************** 2849 * Log2(block height) ----------------------------+ * 2850 * Page Kind ----------------------------------+ | * 2851 * Gob Height/Page Kind Generation ------+ | | * 2852 * Sector layout -------+ | | | * 2853 * Compression ------+ | | | | */ 2854 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2855 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2856 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2857 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2858 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2859 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2860 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2861 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2862 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2863 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2864 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2865 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2866 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2867 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2868 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2869 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2870 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2871 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2872 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2873 DRM_FORMAT_MOD_LINEAR, 2874 DRM_FORMAT_MOD_INVALID 2875 }; 2876 2877 /**************************************************************** 2878 * Log2(block height) ----------------------------+ * 2879 * Page Kind ----------------------------------+ | * 2880 * Gob Height/Page Kind Generation ------+ | | * 2881 * Sector layout -------+ | | | * 2882 * Compression ------+ | | | | */ 2883 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2884 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2885 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2886 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2887 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2888 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2889 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2890 DRM_FORMAT_MOD_LINEAR, 2891 DRM_FORMAT_MOD_INVALID 2892 }; 2893