1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_fb_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_probe_helper.h> 41 #include <drm/drm_scdc_helper.h> 42 #include <drm/drm_vblank.h> 43 44 #include <nvif/push507c.h> 45 46 #include <nvif/class.h> 47 #include <nvif/cl0002.h> 48 #include <nvif/cl5070.h> 49 #include <nvif/cl507d.h> 50 #include <nvif/event.h> 51 #include <nvif/timer.h> 52 53 #include <nvhw/class/cl507c.h> 54 #include <nvhw/class/cl507d.h> 55 #include <nvhw/class/cl837d.h> 56 #include <nvhw/class/cl887d.h> 57 #include <nvhw/class/cl907d.h> 58 #include <nvhw/class/cl917d.h> 59 60 #include "nouveau_drv.h" 61 #include "nouveau_dma.h" 62 #include "nouveau_gem.h" 63 #include "nouveau_connector.h" 64 #include "nouveau_encoder.h" 65 #include "nouveau_fence.h" 66 #include "nouveau_fbcon.h" 67 68 #include <subdev/bios/dp.h> 69 70 /****************************************************************************** 71 * EVO channel 72 *****************************************************************************/ 73 74 static int 75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 76 const s32 *oclass, u8 head, void *data, u32 size, 77 struct nv50_chan *chan) 78 { 79 struct nvif_sclass *sclass; 80 int ret, i, n; 81 82 chan->device = device; 83 84 ret = n = nvif_object_sclass_get(disp, &sclass); 85 if (ret < 0) 86 return ret; 87 88 while (oclass[0]) { 89 for (i = 0; i < n; i++) { 90 if (sclass[i].oclass == oclass[0]) { 91 ret = nvif_object_ctor(disp, "kmsChan", 0, 92 oclass[0], data, size, 93 &chan->user); 94 if (ret == 0) 95 nvif_object_map(&chan->user, NULL, 0); 96 nvif_object_sclass_put(&sclass); 97 return ret; 98 } 99 } 100 oclass++; 101 } 102 103 nvif_object_sclass_put(&sclass); 104 return -ENOSYS; 105 } 106 107 static void 108 nv50_chan_destroy(struct nv50_chan *chan) 109 { 110 nvif_object_dtor(&chan->user); 111 } 112 113 /****************************************************************************** 114 * DMA EVO channel 115 *****************************************************************************/ 116 117 void 118 nv50_dmac_destroy(struct nv50_dmac *dmac) 119 { 120 nvif_object_dtor(&dmac->vram); 121 nvif_object_dtor(&dmac->sync); 122 123 nv50_chan_destroy(&dmac->base); 124 125 nvif_mem_dtor(&dmac->_push.mem); 126 } 127 128 static void 129 nv50_dmac_kick(struct nvif_push *push) 130 { 131 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 132 133 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 134 if (dmac->put != dmac->cur) { 135 /* Push buffer fetches are not coherent with BAR1, we need to ensure 136 * writes have been flushed right through to VRAM before writing PUT. 137 */ 138 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 139 struct nvif_device *device = dmac->base.device; 140 nvif_wr32(&device->object, 0x070000, 0x00000001); 141 nvif_msec(device, 2000, 142 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 143 break; 144 ); 145 } 146 147 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 148 dmac->put = dmac->cur; 149 } 150 151 push->bgn = push->cur; 152 } 153 154 static int 155 nv50_dmac_free(struct nv50_dmac *dmac) 156 { 157 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 158 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 159 return get - dmac->cur - 5; 160 return dmac->max - dmac->cur; 161 } 162 163 static int 164 nv50_dmac_wind(struct nv50_dmac *dmac) 165 { 166 /* Wait for GET to depart from the beginning of the push buffer to 167 * prevent writing PUT == GET, which would be ignored by HW. 168 */ 169 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 170 if (get == 0) { 171 /* Corner-case, HW idle, but non-committed work pending. */ 172 if (dmac->put == 0) 173 nv50_dmac_kick(dmac->push); 174 175 if (nvif_msec(dmac->base.device, 2000, 176 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 177 break; 178 ) < 0) 179 return -ETIMEDOUT; 180 } 181 182 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 183 dmac->cur = 0; 184 return 0; 185 } 186 187 static int 188 nv50_dmac_wait(struct nvif_push *push, u32 size) 189 { 190 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 191 int free; 192 193 if (WARN_ON(size > dmac->max)) 194 return -EINVAL; 195 196 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 197 if (dmac->cur + size >= dmac->max) { 198 int ret = nv50_dmac_wind(dmac); 199 if (ret) 200 return ret; 201 202 push->cur = dmac->_push.mem.object.map.ptr; 203 push->cur = push->cur + dmac->cur; 204 nv50_dmac_kick(push); 205 } 206 207 if (nvif_msec(dmac->base.device, 2000, 208 if ((free = nv50_dmac_free(dmac)) >= size) 209 break; 210 ) < 0) { 211 WARN_ON(1); 212 return -ETIMEDOUT; 213 } 214 215 push->bgn = dmac->_push.mem.object.map.ptr; 216 push->bgn = push->bgn + dmac->cur; 217 push->cur = push->bgn; 218 push->end = push->cur + free; 219 return 0; 220 } 221 222 int 223 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 224 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 225 struct nv50_dmac *dmac) 226 { 227 struct nouveau_cli *cli = (void *)device->object.client; 228 struct nv50_disp_core_channel_dma_v0 *args = data; 229 u8 type = NVIF_MEM_COHERENT; 230 int ret; 231 232 mutex_init(&dmac->lock); 233 234 /* Pascal added support for 47-bit physical addresses, but some 235 * parts of EVO still only accept 40-bit PAs. 236 * 237 * To avoid issues on systems with large amounts of RAM, and on 238 * systems where an IOMMU maps pages at a high address, we need 239 * to allocate push buffers in VRAM instead. 240 * 241 * This appears to match NVIDIA's behaviour on Pascal. 242 */ 243 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 244 type |= NVIF_MEM_VRAM; 245 246 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 247 &dmac->_push.mem); 248 if (ret) 249 return ret; 250 251 dmac->ptr = dmac->_push.mem.object.map.ptr; 252 dmac->_push.wait = nv50_dmac_wait; 253 dmac->_push.kick = nv50_dmac_kick; 254 dmac->push = &dmac->_push; 255 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 256 dmac->push->cur = dmac->push->bgn; 257 dmac->push->end = dmac->push->bgn; 258 dmac->max = 0x1000/4 - 1; 259 260 /* EVO channels are affected by a HW bug where the last 12 DWORDs 261 * of the push buffer aren't able to be used safely. 262 */ 263 if (disp->oclass < GV100_DISP) 264 dmac->max -= 12; 265 266 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 267 268 ret = nv50_chan_create(device, disp, oclass, head, data, size, 269 &dmac->base); 270 if (ret) 271 return ret; 272 273 if (!syncbuf) 274 return 0; 275 276 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 277 NV_DMA_IN_MEMORY, 278 &(struct nv_dma_v0) { 279 .target = NV_DMA_V0_TARGET_VRAM, 280 .access = NV_DMA_V0_ACCESS_RDWR, 281 .start = syncbuf + 0x0000, 282 .limit = syncbuf + 0x0fff, 283 }, sizeof(struct nv_dma_v0), 284 &dmac->sync); 285 if (ret) 286 return ret; 287 288 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 289 NV_DMA_IN_MEMORY, 290 &(struct nv_dma_v0) { 291 .target = NV_DMA_V0_TARGET_VRAM, 292 .access = NV_DMA_V0_ACCESS_RDWR, 293 .start = 0, 294 .limit = device->info.ram_user - 1, 295 }, sizeof(struct nv_dma_v0), 296 &dmac->vram); 297 if (ret) 298 return ret; 299 300 return ret; 301 } 302 303 /****************************************************************************** 304 * Output path helpers 305 *****************************************************************************/ 306 static void 307 nv50_outp_release(struct nouveau_encoder *nv_encoder) 308 { 309 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 310 struct { 311 struct nv50_disp_mthd_v1 base; 312 } args = { 313 .base.version = 1, 314 .base.method = NV50_DISP_MTHD_V1_RELEASE, 315 .base.hasht = nv_encoder->dcb->hasht, 316 .base.hashm = nv_encoder->dcb->hashm, 317 }; 318 319 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 320 nv_encoder->or = -1; 321 nv_encoder->link = 0; 322 } 323 324 static int 325 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 326 { 327 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 328 struct nv50_disp *disp = nv50_disp(drm->dev); 329 struct { 330 struct nv50_disp_mthd_v1 base; 331 struct nv50_disp_acquire_v0 info; 332 } args = { 333 .base.version = 1, 334 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 335 .base.hasht = nv_encoder->dcb->hasht, 336 .base.hashm = nv_encoder->dcb->hashm, 337 .info.hda = hda, 338 }; 339 int ret; 340 341 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 342 if (ret) { 343 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 344 return ret; 345 } 346 347 nv_encoder->or = args.info.or; 348 nv_encoder->link = args.info.link; 349 return 0; 350 } 351 352 static int 353 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 354 struct drm_crtc_state *crtc_state, 355 struct drm_connector_state *conn_state, 356 struct drm_display_mode *native_mode) 357 { 358 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 359 struct drm_display_mode *mode = &crtc_state->mode; 360 struct drm_connector *connector = conn_state->connector; 361 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 362 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 363 364 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 365 asyc->scaler.full = false; 366 if (!native_mode) 367 return 0; 368 369 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 370 switch (connector->connector_type) { 371 case DRM_MODE_CONNECTOR_LVDS: 372 case DRM_MODE_CONNECTOR_eDP: 373 /* Don't force scaler for EDID modes with 374 * same size as the native one (e.g. different 375 * refresh rate) 376 */ 377 if (mode->hdisplay == native_mode->hdisplay && 378 mode->vdisplay == native_mode->vdisplay && 379 mode->type & DRM_MODE_TYPE_DRIVER) 380 break; 381 mode = native_mode; 382 asyc->scaler.full = true; 383 break; 384 default: 385 break; 386 } 387 } else { 388 mode = native_mode; 389 } 390 391 if (!drm_mode_equal(adjusted_mode, mode)) { 392 drm_mode_copy(adjusted_mode, mode); 393 crtc_state->mode_changed = true; 394 } 395 396 return 0; 397 } 398 399 static int 400 nv50_outp_atomic_check(struct drm_encoder *encoder, 401 struct drm_crtc_state *crtc_state, 402 struct drm_connector_state *conn_state) 403 { 404 struct drm_connector *connector = conn_state->connector; 405 struct nouveau_connector *nv_connector = nouveau_connector(connector); 406 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 407 int ret; 408 409 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 410 nv_connector->native_mode); 411 if (ret) 412 return ret; 413 414 if (crtc_state->mode_changed || crtc_state->connectors_changed) 415 asyh->or.bpc = connector->display_info.bpc; 416 417 return 0; 418 } 419 420 struct nouveau_connector * 421 nv50_outp_get_new_connector(struct nouveau_encoder *outp, 422 struct drm_atomic_state *state) 423 { 424 struct drm_connector *connector; 425 struct drm_connector_state *connector_state; 426 struct drm_encoder *encoder = to_drm_encoder(outp); 427 int i; 428 429 for_each_new_connector_in_state(state, connector, connector_state, i) { 430 if (connector_state->best_encoder == encoder) 431 return nouveau_connector(connector); 432 } 433 434 return NULL; 435 } 436 437 struct nouveau_connector * 438 nv50_outp_get_old_connector(struct nouveau_encoder *outp, 439 struct drm_atomic_state *state) 440 { 441 struct drm_connector *connector; 442 struct drm_connector_state *connector_state; 443 struct drm_encoder *encoder = to_drm_encoder(outp); 444 int i; 445 446 for_each_old_connector_in_state(state, connector, connector_state, i) { 447 if (connector_state->best_encoder == encoder) 448 return nouveau_connector(connector); 449 } 450 451 return NULL; 452 } 453 454 /****************************************************************************** 455 * DAC 456 *****************************************************************************/ 457 static void 458 nv50_dac_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 459 { 460 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 461 struct nv50_core *core = nv50_disp(encoder->dev)->core; 462 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 463 if (nv_encoder->crtc) 464 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); 465 nv_encoder->crtc = NULL; 466 nv50_outp_release(nv_encoder); 467 } 468 469 static void 470 nv50_dac_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 471 { 472 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 473 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 474 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 475 struct nv50_core *core = nv50_disp(encoder->dev)->core; 476 u32 ctrl = 0; 477 478 switch (nv_crtc->index) { 479 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 480 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 481 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 482 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 483 default: 484 WARN_ON(1); 485 break; 486 } 487 488 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 489 490 nv50_outp_acquire(nv_encoder, false); 491 492 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); 493 asyh->or.depth = 0; 494 495 nv_encoder->crtc = encoder->crtc; 496 } 497 498 static enum drm_connector_status 499 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 500 { 501 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 502 struct nv50_disp *disp = nv50_disp(encoder->dev); 503 struct { 504 struct nv50_disp_mthd_v1 base; 505 struct nv50_disp_dac_load_v0 load; 506 } args = { 507 .base.version = 1, 508 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 509 .base.hasht = nv_encoder->dcb->hasht, 510 .base.hashm = nv_encoder->dcb->hashm, 511 }; 512 int ret; 513 514 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 515 if (args.load.data == 0) 516 args.load.data = 340; 517 518 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 519 if (ret || !args.load.load) 520 return connector_status_disconnected; 521 522 return connector_status_connected; 523 } 524 525 static const struct drm_encoder_helper_funcs 526 nv50_dac_help = { 527 .atomic_check = nv50_outp_atomic_check, 528 .atomic_enable = nv50_dac_enable, 529 .atomic_disable = nv50_dac_disable, 530 .detect = nv50_dac_detect 531 }; 532 533 static void 534 nv50_dac_destroy(struct drm_encoder *encoder) 535 { 536 drm_encoder_cleanup(encoder); 537 kfree(encoder); 538 } 539 540 static const struct drm_encoder_funcs 541 nv50_dac_func = { 542 .destroy = nv50_dac_destroy, 543 }; 544 545 static int 546 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 547 { 548 struct nouveau_drm *drm = nouveau_drm(connector->dev); 549 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 550 struct nvkm_i2c_bus *bus; 551 struct nouveau_encoder *nv_encoder; 552 struct drm_encoder *encoder; 553 int type = DRM_MODE_ENCODER_DAC; 554 555 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 556 if (!nv_encoder) 557 return -ENOMEM; 558 nv_encoder->dcb = dcbe; 559 560 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 561 if (bus) 562 nv_encoder->i2c = &bus->i2c; 563 564 encoder = to_drm_encoder(nv_encoder); 565 encoder->possible_crtcs = dcbe->heads; 566 encoder->possible_clones = 0; 567 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 568 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 569 drm_encoder_helper_add(encoder, &nv50_dac_help); 570 571 drm_connector_attach_encoder(connector, encoder); 572 return 0; 573 } 574 575 /* 576 * audio component binding for ELD notification 577 */ 578 static void 579 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 580 int dev_id) 581 { 582 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 583 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 584 port, dev_id); 585 } 586 587 static int 588 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 589 bool *enabled, unsigned char *buf, int max_bytes) 590 { 591 struct drm_device *drm_dev = dev_get_drvdata(kdev); 592 struct nouveau_drm *drm = nouveau_drm(drm_dev); 593 struct drm_encoder *encoder; 594 struct nouveau_encoder *nv_encoder; 595 struct drm_connector *connector; 596 struct nouveau_crtc *nv_crtc; 597 struct drm_connector_list_iter conn_iter; 598 int ret = 0; 599 600 *enabled = false; 601 602 drm_for_each_encoder(encoder, drm->dev) { 603 struct nouveau_connector *nv_connector = NULL; 604 605 nv_encoder = nouveau_encoder(encoder); 606 607 drm_connector_list_iter_begin(drm_dev, &conn_iter); 608 drm_for_each_connector_iter(connector, &conn_iter) { 609 if (connector->state->best_encoder == encoder) { 610 nv_connector = nouveau_connector(connector); 611 break; 612 } 613 } 614 drm_connector_list_iter_end(&conn_iter); 615 if (!nv_connector) 616 continue; 617 618 nv_crtc = nouveau_crtc(encoder->crtc); 619 if (!nv_crtc || nv_encoder->or != port || 620 nv_crtc->index != dev_id) 621 continue; 622 *enabled = nv_encoder->audio; 623 if (*enabled) { 624 ret = drm_eld_size(nv_connector->base.eld); 625 memcpy(buf, nv_connector->base.eld, 626 min(max_bytes, ret)); 627 } 628 break; 629 } 630 631 return ret; 632 } 633 634 static const struct drm_audio_component_ops nv50_audio_component_ops = { 635 .get_eld = nv50_audio_component_get_eld, 636 }; 637 638 static int 639 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 640 void *data) 641 { 642 struct drm_device *drm_dev = dev_get_drvdata(kdev); 643 struct nouveau_drm *drm = nouveau_drm(drm_dev); 644 struct drm_audio_component *acomp = data; 645 646 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 647 return -ENOMEM; 648 649 drm_modeset_lock_all(drm_dev); 650 acomp->ops = &nv50_audio_component_ops; 651 acomp->dev = kdev; 652 drm->audio.component = acomp; 653 drm_modeset_unlock_all(drm_dev); 654 return 0; 655 } 656 657 static void 658 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 659 void *data) 660 { 661 struct drm_device *drm_dev = dev_get_drvdata(kdev); 662 struct nouveau_drm *drm = nouveau_drm(drm_dev); 663 struct drm_audio_component *acomp = data; 664 665 drm_modeset_lock_all(drm_dev); 666 drm->audio.component = NULL; 667 acomp->ops = NULL; 668 acomp->dev = NULL; 669 drm_modeset_unlock_all(drm_dev); 670 } 671 672 static const struct component_ops nv50_audio_component_bind_ops = { 673 .bind = nv50_audio_component_bind, 674 .unbind = nv50_audio_component_unbind, 675 }; 676 677 static void 678 nv50_audio_component_init(struct nouveau_drm *drm) 679 { 680 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 681 drm->audio.component_registered = true; 682 } 683 684 static void 685 nv50_audio_component_fini(struct nouveau_drm *drm) 686 { 687 if (drm->audio.component_registered) { 688 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 689 drm->audio.component_registered = false; 690 } 691 } 692 693 /****************************************************************************** 694 * Audio 695 *****************************************************************************/ 696 static void 697 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 698 { 699 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 700 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 701 struct nv50_disp *disp = nv50_disp(encoder->dev); 702 struct { 703 struct nv50_disp_mthd_v1 base; 704 struct nv50_disp_sor_hda_eld_v0 eld; 705 } args = { 706 .base.version = 1, 707 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 708 .base.hasht = nv_encoder->dcb->hasht, 709 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 710 (0x0100 << nv_crtc->index), 711 }; 712 713 if (!nv_encoder->audio) 714 return; 715 716 nv_encoder->audio = false; 717 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 718 719 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 720 nv_crtc->index); 721 } 722 723 static void 724 nv50_audio_enable(struct drm_encoder *encoder, struct drm_atomic_state *state, 725 struct drm_display_mode *mode) 726 { 727 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 728 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 729 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 730 struct nouveau_connector *nv_connector; 731 struct nv50_disp *disp = nv50_disp(encoder->dev); 732 struct __packed { 733 struct { 734 struct nv50_disp_mthd_v1 mthd; 735 struct nv50_disp_sor_hda_eld_v0 eld; 736 } base; 737 u8 data[sizeof(nv_connector->base.eld)]; 738 } args = { 739 .base.mthd.version = 1, 740 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 741 .base.mthd.hasht = nv_encoder->dcb->hasht, 742 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 743 (0x0100 << nv_crtc->index), 744 }; 745 746 nv_connector = nv50_outp_get_new_connector(nv_encoder, state); 747 if (!drm_detect_monitor_audio(nv_connector->edid)) 748 return; 749 750 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 751 752 nvif_mthd(&disp->disp->object, 0, &args, 753 sizeof(args.base) + drm_eld_size(args.data)); 754 nv_encoder->audio = true; 755 756 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 757 nv_crtc->index); 758 } 759 760 /****************************************************************************** 761 * HDMI 762 *****************************************************************************/ 763 static void 764 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 765 { 766 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 767 struct nv50_disp *disp = nv50_disp(encoder->dev); 768 struct { 769 struct nv50_disp_mthd_v1 base; 770 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 771 } args = { 772 .base.version = 1, 773 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 774 .base.hasht = nv_encoder->dcb->hasht, 775 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 776 (0x0100 << nv_crtc->index), 777 }; 778 779 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 780 } 781 782 static void 783 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_atomic_state *state, 784 struct drm_display_mode *mode) 785 { 786 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 787 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 788 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 789 struct nv50_disp *disp = nv50_disp(encoder->dev); 790 struct { 791 struct nv50_disp_mthd_v1 base; 792 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 793 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 794 } args = { 795 .base.version = 1, 796 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 797 .base.hasht = nv_encoder->dcb->hasht, 798 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 799 (0x0100 << nv_crtc->index), 800 .pwr.state = 1, 801 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 802 }; 803 struct nouveau_connector *nv_connector; 804 struct drm_hdmi_info *hdmi; 805 u32 max_ac_packet; 806 union hdmi_infoframe avi_frame; 807 union hdmi_infoframe vendor_frame; 808 bool high_tmds_clock_ratio = false, scrambling = false; 809 u8 config; 810 int ret; 811 int size; 812 813 nv_connector = nv50_outp_get_new_connector(nv_encoder, state); 814 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 815 return; 816 817 hdmi = &nv_connector->base.display_info.hdmi; 818 819 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 820 &nv_connector->base, mode); 821 if (!ret) { 822 /* We have an AVI InfoFrame, populate it to the display */ 823 args.pwr.avi_infoframe_length 824 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 825 } 826 827 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 828 &nv_connector->base, mode); 829 if (!ret) { 830 /* We have a Vendor InfoFrame, populate it to the display */ 831 args.pwr.vendor_infoframe_length 832 = hdmi_infoframe_pack(&vendor_frame, 833 args.infoframes 834 + args.pwr.avi_infoframe_length, 835 17); 836 } 837 838 max_ac_packet = mode->htotal - mode->hdisplay; 839 max_ac_packet -= args.pwr.rekey; 840 max_ac_packet -= 18; /* constant from tegra */ 841 args.pwr.max_ac_packet = max_ac_packet / 32; 842 843 if (hdmi->scdc.scrambling.supported) { 844 high_tmds_clock_ratio = mode->clock > 340000; 845 scrambling = high_tmds_clock_ratio || 846 hdmi->scdc.scrambling.low_rates; 847 } 848 849 args.pwr.scdc = 850 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 851 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 852 853 size = sizeof(args.base) 854 + sizeof(args.pwr) 855 + args.pwr.avi_infoframe_length 856 + args.pwr.vendor_infoframe_length; 857 nvif_mthd(&disp->disp->object, 0, &args, size); 858 859 nv50_audio_enable(encoder, state, mode); 860 861 /* If SCDC is supported by the downstream monitor, update 862 * divider / scrambling settings to what we programmed above. 863 */ 864 if (!hdmi->scdc.scrambling.supported) 865 return; 866 867 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 868 if (ret < 0) { 869 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 870 return; 871 } 872 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 873 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 874 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 875 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 876 if (ret < 0) 877 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 878 config, ret); 879 } 880 881 /****************************************************************************** 882 * MST 883 *****************************************************************************/ 884 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 885 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 886 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 887 888 struct nv50_mstc { 889 struct nv50_mstm *mstm; 890 struct drm_dp_mst_port *port; 891 struct drm_connector connector; 892 893 struct drm_display_mode *native; 894 struct edid *edid; 895 }; 896 897 struct nv50_msto { 898 struct drm_encoder encoder; 899 900 struct nv50_head *head; 901 struct nv50_mstc *mstc; 902 bool disabled; 903 }; 904 905 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 906 { 907 struct nv50_msto *msto; 908 909 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 910 return nouveau_encoder(encoder); 911 912 msto = nv50_msto(encoder); 913 if (!msto->mstc) 914 return NULL; 915 return msto->mstc->mstm->outp; 916 } 917 918 static struct drm_dp_payload * 919 nv50_msto_payload(struct nv50_msto *msto) 920 { 921 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 922 struct nv50_mstc *mstc = msto->mstc; 923 struct nv50_mstm *mstm = mstc->mstm; 924 int vcpi = mstc->port->vcpi.vcpi, i; 925 926 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 927 928 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 929 for (i = 0; i < mstm->mgr.max_payloads; i++) { 930 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 931 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 932 mstm->outp->base.base.name, i, payload->vcpi, 933 payload->start_slot, payload->num_slots); 934 } 935 936 for (i = 0; i < mstm->mgr.max_payloads; i++) { 937 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 938 if (payload->vcpi == vcpi) 939 return payload; 940 } 941 942 return NULL; 943 } 944 945 static void 946 nv50_msto_cleanup(struct nv50_msto *msto) 947 { 948 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 949 struct nv50_mstc *mstc = msto->mstc; 950 struct nv50_mstm *mstm = mstc->mstm; 951 952 if (!msto->disabled) 953 return; 954 955 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 956 957 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 958 959 msto->mstc = NULL; 960 msto->disabled = false; 961 } 962 963 static void 964 nv50_msto_prepare(struct nv50_msto *msto) 965 { 966 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 967 struct nv50_mstc *mstc = msto->mstc; 968 struct nv50_mstm *mstm = mstc->mstm; 969 struct { 970 struct nv50_disp_mthd_v1 base; 971 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 972 } args = { 973 .base.version = 1, 974 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 975 .base.hasht = mstm->outp->dcb->hasht, 976 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 977 (0x0100 << msto->head->base.index), 978 }; 979 980 mutex_lock(&mstm->mgr.payload_lock); 981 982 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 983 if (mstc->port->vcpi.vcpi > 0) { 984 struct drm_dp_payload *payload = nv50_msto_payload(msto); 985 if (payload) { 986 args.vcpi.start_slot = payload->start_slot; 987 args.vcpi.num_slots = payload->num_slots; 988 args.vcpi.pbn = mstc->port->vcpi.pbn; 989 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 990 } 991 } 992 993 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 994 msto->encoder.name, msto->head->base.base.name, 995 args.vcpi.start_slot, args.vcpi.num_slots, 996 args.vcpi.pbn, args.vcpi.aligned_pbn); 997 998 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 999 mutex_unlock(&mstm->mgr.payload_lock); 1000 } 1001 1002 static int 1003 nv50_msto_atomic_check(struct drm_encoder *encoder, 1004 struct drm_crtc_state *crtc_state, 1005 struct drm_connector_state *conn_state) 1006 { 1007 struct drm_atomic_state *state = crtc_state->state; 1008 struct drm_connector *connector = conn_state->connector; 1009 struct nv50_mstc *mstc = nv50_mstc(connector); 1010 struct nv50_mstm *mstm = mstc->mstm; 1011 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 1012 int slots; 1013 int ret; 1014 1015 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 1016 mstc->native); 1017 if (ret) 1018 return ret; 1019 1020 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 1021 return 0; 1022 1023 /* 1024 * When restoring duplicated states, we need to make sure that the bw 1025 * remains the same and avoid recalculating it, as the connector's bpc 1026 * may have changed after the state was duplicated 1027 */ 1028 if (!state->duplicated) { 1029 const int clock = crtc_state->adjusted_mode.clock; 1030 1031 asyh->or.bpc = connector->display_info.bpc; 1032 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 1033 false); 1034 } 1035 1036 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 1037 asyh->dp.pbn, 0); 1038 if (slots < 0) 1039 return slots; 1040 1041 asyh->dp.tu = slots; 1042 1043 return 0; 1044 } 1045 1046 static u8 1047 nv50_dp_bpc_to_depth(unsigned int bpc) 1048 { 1049 switch (bpc) { 1050 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1051 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1052 case 10: 1053 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1054 } 1055 } 1056 1057 static void 1058 nv50_msto_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1059 { 1060 struct nv50_head *head = nv50_head(encoder->crtc); 1061 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 1062 struct nv50_msto *msto = nv50_msto(encoder); 1063 struct nv50_mstc *mstc = NULL; 1064 struct nv50_mstm *mstm = NULL; 1065 struct drm_connector *connector; 1066 struct drm_connector_list_iter conn_iter; 1067 u8 proto; 1068 bool r; 1069 1070 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1071 drm_for_each_connector_iter(connector, &conn_iter) { 1072 if (connector->state->best_encoder == &msto->encoder) { 1073 mstc = nv50_mstc(connector); 1074 mstm = mstc->mstm; 1075 break; 1076 } 1077 } 1078 drm_connector_list_iter_end(&conn_iter); 1079 1080 if (WARN_ON(!mstc)) 1081 return; 1082 1083 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 1084 armh->dp.tu); 1085 if (!r) 1086 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 1087 1088 if (!mstm->links++) 1089 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 1090 1091 if (mstm->outp->link & 1) 1092 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1093 else 1094 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1095 1096 mstm->outp->update(mstm->outp, head->base.index, armh, proto, 1097 nv50_dp_bpc_to_depth(armh->or.bpc)); 1098 1099 msto->mstc = mstc; 1100 mstm->modified = true; 1101 } 1102 1103 static void 1104 nv50_msto_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1105 { 1106 struct nv50_msto *msto = nv50_msto(encoder); 1107 struct nv50_mstc *mstc = msto->mstc; 1108 struct nv50_mstm *mstm = mstc->mstm; 1109 1110 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 1111 1112 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1113 mstm->modified = true; 1114 if (!--mstm->links) 1115 mstm->disabled = true; 1116 msto->disabled = true; 1117 } 1118 1119 static const struct drm_encoder_helper_funcs 1120 nv50_msto_help = { 1121 .atomic_disable = nv50_msto_disable, 1122 .atomic_enable = nv50_msto_enable, 1123 .atomic_check = nv50_msto_atomic_check, 1124 }; 1125 1126 static void 1127 nv50_msto_destroy(struct drm_encoder *encoder) 1128 { 1129 struct nv50_msto *msto = nv50_msto(encoder); 1130 drm_encoder_cleanup(&msto->encoder); 1131 kfree(msto); 1132 } 1133 1134 static const struct drm_encoder_funcs 1135 nv50_msto = { 1136 .destroy = nv50_msto_destroy, 1137 }; 1138 1139 static struct nv50_msto * 1140 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1141 { 1142 struct nv50_msto *msto; 1143 int ret; 1144 1145 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1146 if (!msto) 1147 return ERR_PTR(-ENOMEM); 1148 1149 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1150 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1151 if (ret) { 1152 kfree(msto); 1153 return ERR_PTR(ret); 1154 } 1155 1156 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1157 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1158 msto->head = head; 1159 return msto; 1160 } 1161 1162 static struct drm_encoder * 1163 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1164 struct drm_connector_state *connector_state) 1165 { 1166 struct nv50_mstc *mstc = nv50_mstc(connector); 1167 struct drm_crtc *crtc = connector_state->crtc; 1168 1169 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1170 return NULL; 1171 1172 return &nv50_head(crtc)->msto->encoder; 1173 } 1174 1175 static enum drm_mode_status 1176 nv50_mstc_mode_valid(struct drm_connector *connector, 1177 struct drm_display_mode *mode) 1178 { 1179 struct nv50_mstc *mstc = nv50_mstc(connector); 1180 struct nouveau_encoder *outp = mstc->mstm->outp; 1181 1182 /* TODO: calculate the PBN from the dotclock and validate against the 1183 * MSTB's max possible PBN 1184 */ 1185 1186 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1187 } 1188 1189 static int 1190 nv50_mstc_get_modes(struct drm_connector *connector) 1191 { 1192 struct nv50_mstc *mstc = nv50_mstc(connector); 1193 int ret = 0; 1194 1195 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1196 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1197 if (mstc->edid) 1198 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1199 1200 /* 1201 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1202 * to 8 to save bandwidth on the topology. In the future, we'll want 1203 * to properly fix this by dynamically selecting the highest possible 1204 * bpc that would fit in the topology 1205 */ 1206 if (connector->display_info.bpc) 1207 connector->display_info.bpc = 1208 clamp(connector->display_info.bpc, 6U, 8U); 1209 else 1210 connector->display_info.bpc = 8; 1211 1212 if (mstc->native) 1213 drm_mode_destroy(mstc->connector.dev, mstc->native); 1214 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1215 return ret; 1216 } 1217 1218 static int 1219 nv50_mstc_atomic_check(struct drm_connector *connector, 1220 struct drm_atomic_state *state) 1221 { 1222 struct nv50_mstc *mstc = nv50_mstc(connector); 1223 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1224 struct drm_connector_state *new_conn_state = 1225 drm_atomic_get_new_connector_state(state, connector); 1226 struct drm_connector_state *old_conn_state = 1227 drm_atomic_get_old_connector_state(state, connector); 1228 struct drm_crtc_state *crtc_state; 1229 struct drm_crtc *new_crtc = new_conn_state->crtc; 1230 1231 if (!old_conn_state->crtc) 1232 return 0; 1233 1234 /* We only want to free VCPI if this state disables the CRTC on this 1235 * connector 1236 */ 1237 if (new_crtc) { 1238 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1239 1240 if (!crtc_state || 1241 !drm_atomic_crtc_needs_modeset(crtc_state) || 1242 crtc_state->enable) 1243 return 0; 1244 } 1245 1246 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1247 } 1248 1249 static int 1250 nv50_mstc_detect(struct drm_connector *connector, 1251 struct drm_modeset_acquire_ctx *ctx, bool force) 1252 { 1253 struct nv50_mstc *mstc = nv50_mstc(connector); 1254 int ret; 1255 1256 if (drm_connector_is_unregistered(connector)) 1257 return connector_status_disconnected; 1258 1259 ret = pm_runtime_get_sync(connector->dev->dev); 1260 if (ret < 0 && ret != -EACCES) { 1261 pm_runtime_put_autosuspend(connector->dev->dev); 1262 return connector_status_disconnected; 1263 } 1264 1265 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1266 mstc->port); 1267 if (ret != connector_status_connected) 1268 goto out; 1269 1270 out: 1271 pm_runtime_mark_last_busy(connector->dev->dev); 1272 pm_runtime_put_autosuspend(connector->dev->dev); 1273 return ret; 1274 } 1275 1276 static const struct drm_connector_helper_funcs 1277 nv50_mstc_help = { 1278 .get_modes = nv50_mstc_get_modes, 1279 .mode_valid = nv50_mstc_mode_valid, 1280 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1281 .atomic_check = nv50_mstc_atomic_check, 1282 .detect_ctx = nv50_mstc_detect, 1283 }; 1284 1285 static void 1286 nv50_mstc_destroy(struct drm_connector *connector) 1287 { 1288 struct nv50_mstc *mstc = nv50_mstc(connector); 1289 1290 drm_connector_cleanup(&mstc->connector); 1291 drm_dp_mst_put_port_malloc(mstc->port); 1292 1293 kfree(mstc); 1294 } 1295 1296 static const struct drm_connector_funcs 1297 nv50_mstc = { 1298 .reset = nouveau_conn_reset, 1299 .fill_modes = drm_helper_probe_single_connector_modes, 1300 .destroy = nv50_mstc_destroy, 1301 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1302 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1303 .atomic_set_property = nouveau_conn_atomic_set_property, 1304 .atomic_get_property = nouveau_conn_atomic_get_property, 1305 }; 1306 1307 static int 1308 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1309 const char *path, struct nv50_mstc **pmstc) 1310 { 1311 struct drm_device *dev = mstm->outp->base.base.dev; 1312 struct drm_crtc *crtc; 1313 struct nv50_mstc *mstc; 1314 int ret; 1315 1316 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1317 return -ENOMEM; 1318 mstc->mstm = mstm; 1319 mstc->port = port; 1320 1321 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1322 DRM_MODE_CONNECTOR_DisplayPort); 1323 if (ret) { 1324 kfree(*pmstc); 1325 *pmstc = NULL; 1326 return ret; 1327 } 1328 1329 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1330 1331 mstc->connector.funcs->reset(&mstc->connector); 1332 nouveau_conn_attach_properties(&mstc->connector); 1333 1334 drm_for_each_crtc(crtc, dev) { 1335 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1336 continue; 1337 1338 drm_connector_attach_encoder(&mstc->connector, 1339 &nv50_head(crtc)->msto->encoder); 1340 } 1341 1342 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1343 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1344 drm_connector_set_path_property(&mstc->connector, path); 1345 drm_dp_mst_get_port_malloc(port); 1346 return 0; 1347 } 1348 1349 static void 1350 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1351 { 1352 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1353 struct drm_encoder *encoder; 1354 int ret; 1355 1356 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1357 ret = drm_dp_check_act_status(&mstm->mgr); 1358 1359 ret = drm_dp_update_payload_part2(&mstm->mgr); 1360 1361 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1362 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1363 struct nv50_msto *msto = nv50_msto(encoder); 1364 struct nv50_mstc *mstc = msto->mstc; 1365 if (mstc && mstc->mstm == mstm) 1366 nv50_msto_cleanup(msto); 1367 } 1368 } 1369 1370 mstm->modified = false; 1371 } 1372 1373 static void 1374 nv50_mstm_prepare(struct nv50_mstm *mstm) 1375 { 1376 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1377 struct drm_encoder *encoder; 1378 int ret; 1379 1380 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1381 ret = drm_dp_update_payload_part1(&mstm->mgr); 1382 1383 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1384 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1385 struct nv50_msto *msto = nv50_msto(encoder); 1386 struct nv50_mstc *mstc = msto->mstc; 1387 if (mstc && mstc->mstm == mstm) 1388 nv50_msto_prepare(msto); 1389 } 1390 } 1391 1392 if (mstm->disabled) { 1393 if (!mstm->links) 1394 nv50_outp_release(mstm->outp); 1395 mstm->disabled = false; 1396 } 1397 } 1398 1399 static struct drm_connector * 1400 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1401 struct drm_dp_mst_port *port, const char *path) 1402 { 1403 struct nv50_mstm *mstm = nv50_mstm(mgr); 1404 struct nv50_mstc *mstc; 1405 int ret; 1406 1407 ret = nv50_mstc_new(mstm, port, path, &mstc); 1408 if (ret) 1409 return NULL; 1410 1411 return &mstc->connector; 1412 } 1413 1414 static const struct drm_dp_mst_topology_cbs 1415 nv50_mstm = { 1416 .add_connector = nv50_mstm_add_connector, 1417 }; 1418 1419 bool 1420 nv50_mstm_service(struct nouveau_drm *drm, 1421 struct nouveau_connector *nv_connector, 1422 struct nv50_mstm *mstm) 1423 { 1424 struct drm_dp_aux *aux = &nv_connector->aux; 1425 bool handled = true, ret = true; 1426 int rc; 1427 u8 esi[8] = {}; 1428 1429 while (handled) { 1430 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1431 if (rc != 8) { 1432 ret = false; 1433 break; 1434 } 1435 1436 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1437 if (!handled) 1438 break; 1439 1440 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 1441 3); 1442 if (rc != 3) { 1443 ret = false; 1444 break; 1445 } 1446 } 1447 1448 if (!ret) 1449 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1450 nv_connector->base.name, rc); 1451 1452 return ret; 1453 } 1454 1455 void 1456 nv50_mstm_remove(struct nv50_mstm *mstm) 1457 { 1458 mstm->is_mst = false; 1459 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1460 } 1461 1462 static int 1463 nv50_mstm_enable(struct nv50_mstm *mstm, int state) 1464 { 1465 struct nouveau_encoder *outp = mstm->outp; 1466 struct { 1467 struct nv50_disp_mthd_v1 base; 1468 struct nv50_disp_sor_dp_mst_link_v0 mst; 1469 } args = { 1470 .base.version = 1, 1471 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1472 .base.hasht = outp->dcb->hasht, 1473 .base.hashm = outp->dcb->hashm, 1474 .mst.state = state, 1475 }; 1476 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1477 struct nvif_object *disp = &drm->display->disp.object; 1478 1479 return nvif_mthd(disp, 0, &args, sizeof(args)); 1480 } 1481 1482 int 1483 nv50_mstm_detect(struct nouveau_encoder *outp) 1484 { 1485 struct nv50_mstm *mstm = outp->dp.mstm; 1486 struct drm_dp_aux *aux; 1487 int ret; 1488 1489 if (!mstm || !mstm->can_mst) 1490 return 0; 1491 1492 aux = mstm->mgr.aux; 1493 1494 /* Clear any leftover MST state we didn't set ourselves by first 1495 * disabling MST if it was already enabled 1496 */ 1497 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1498 if (ret < 0) 1499 return ret; 1500 1501 /* And start enabling */ 1502 ret = nv50_mstm_enable(mstm, true); 1503 if (ret) 1504 return ret; 1505 1506 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1507 if (ret) { 1508 nv50_mstm_enable(mstm, false); 1509 return ret; 1510 } 1511 1512 mstm->is_mst = true; 1513 return 1; 1514 } 1515 1516 static void 1517 nv50_mstm_fini(struct nouveau_encoder *outp) 1518 { 1519 struct nv50_mstm *mstm = outp->dp.mstm; 1520 1521 if (!mstm) 1522 return; 1523 1524 /* Don't change the MST state of this connector until we've finished 1525 * resuming, since we can't safely grab hpd_irq_lock in our resume 1526 * path to protect mstm->is_mst without potentially deadlocking 1527 */ 1528 mutex_lock(&outp->dp.hpd_irq_lock); 1529 mstm->suspended = true; 1530 mutex_unlock(&outp->dp.hpd_irq_lock); 1531 1532 if (mstm->is_mst) 1533 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1534 } 1535 1536 static void 1537 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1538 { 1539 struct nv50_mstm *mstm = outp->dp.mstm; 1540 int ret = 0; 1541 1542 if (!mstm) 1543 return; 1544 1545 if (mstm->is_mst) { 1546 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1547 if (ret == -1) 1548 nv50_mstm_remove(mstm); 1549 } 1550 1551 mutex_lock(&outp->dp.hpd_irq_lock); 1552 mstm->suspended = false; 1553 mutex_unlock(&outp->dp.hpd_irq_lock); 1554 1555 if (ret == -1) 1556 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1557 } 1558 1559 static void 1560 nv50_mstm_del(struct nv50_mstm **pmstm) 1561 { 1562 struct nv50_mstm *mstm = *pmstm; 1563 if (mstm) { 1564 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1565 kfree(*pmstm); 1566 *pmstm = NULL; 1567 } 1568 } 1569 1570 static int 1571 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1572 int conn_base_id, struct nv50_mstm **pmstm) 1573 { 1574 const int max_payloads = hweight8(outp->dcb->heads); 1575 struct drm_device *dev = outp->base.base.dev; 1576 struct nv50_mstm *mstm; 1577 int ret; 1578 1579 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1580 return -ENOMEM; 1581 mstm->outp = outp; 1582 mstm->mgr.cbs = &nv50_mstm; 1583 1584 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1585 max_payloads, conn_base_id); 1586 if (ret) 1587 return ret; 1588 1589 return 0; 1590 } 1591 1592 /****************************************************************************** 1593 * SOR 1594 *****************************************************************************/ 1595 static void 1596 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1597 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1598 { 1599 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1600 struct nv50_core *core = disp->core; 1601 1602 if (!asyh) { 1603 nv_encoder->ctrl &= ~BIT(head); 1604 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1605 nv_encoder->ctrl = 0; 1606 } else { 1607 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1608 nv_encoder->ctrl |= BIT(head); 1609 asyh->or.depth = depth; 1610 } 1611 1612 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1613 } 1614 1615 static void 1616 nv50_sor_disable(struct drm_encoder *encoder, 1617 struct drm_atomic_state *state) 1618 { 1619 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1620 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1621 struct nouveau_connector *nv_connector = 1622 nv50_outp_get_old_connector(nv_encoder, state); 1623 1624 nv_encoder->crtc = NULL; 1625 1626 if (nv_crtc) { 1627 struct drm_dp_aux *aux = &nv_connector->aux; 1628 u8 pwr; 1629 1630 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1631 int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1632 1633 if (ret == 0) { 1634 pwr &= ~DP_SET_POWER_MASK; 1635 pwr |= DP_SET_POWER_D3; 1636 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1637 } 1638 } 1639 1640 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1641 nv50_audio_disable(encoder, nv_crtc); 1642 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1643 nv50_outp_release(nv_encoder); 1644 } 1645 } 1646 1647 static void 1648 nv50_sor_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1649 { 1650 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1651 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1652 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1653 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1654 struct { 1655 struct nv50_disp_mthd_v1 base; 1656 struct nv50_disp_sor_lvds_script_v0 lvds; 1657 } lvds = { 1658 .base.version = 1, 1659 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1660 .base.hasht = nv_encoder->dcb->hasht, 1661 .base.hashm = nv_encoder->dcb->hashm, 1662 }; 1663 struct nv50_disp *disp = nv50_disp(encoder->dev); 1664 struct drm_device *dev = encoder->dev; 1665 struct nouveau_drm *drm = nouveau_drm(dev); 1666 struct nouveau_connector *nv_connector; 1667 struct nvbios *bios = &drm->vbios; 1668 bool hda = false; 1669 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1670 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1671 1672 nv_connector = nv50_outp_get_new_connector(nv_encoder, state); 1673 nv_encoder->crtc = encoder->crtc; 1674 1675 if ((disp->disp->object.oclass == GT214_DISP || 1676 disp->disp->object.oclass >= GF110_DISP) && 1677 drm_detect_monitor_audio(nv_connector->edid)) 1678 hda = true; 1679 nv50_outp_acquire(nv_encoder, hda); 1680 1681 switch (nv_encoder->dcb->type) { 1682 case DCB_OUTPUT_TMDS: 1683 if (nv_encoder->link & 1) { 1684 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1685 /* Only enable dual-link if: 1686 * - Need to (i.e. rate > 165MHz) 1687 * - DCB says we can 1688 * - Not an HDMI monitor, since there's no dual-link 1689 * on HDMI. 1690 */ 1691 if (mode->clock >= 165000 && 1692 nv_encoder->dcb->duallink_possible && 1693 !drm_detect_hdmi_monitor(nv_connector->edid)) 1694 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1695 } else { 1696 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1697 } 1698 1699 nv50_hdmi_enable(&nv_encoder->base.base, state, mode); 1700 break; 1701 case DCB_OUTPUT_LVDS: 1702 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1703 1704 if (bios->fp_no_ddc) { 1705 if (bios->fp.dual_link) 1706 lvds.lvds.script |= 0x0100; 1707 if (bios->fp.if_is_24bit) 1708 lvds.lvds.script |= 0x0200; 1709 } else { 1710 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1711 if (((u8 *)nv_connector->edid)[121] == 2) 1712 lvds.lvds.script |= 0x0100; 1713 } else 1714 if (mode->clock >= bios->fp.duallink_transition_clk) { 1715 lvds.lvds.script |= 0x0100; 1716 } 1717 1718 if (lvds.lvds.script & 0x0100) { 1719 if (bios->fp.strapless_is_24bit & 2) 1720 lvds.lvds.script |= 0x0200; 1721 } else { 1722 if (bios->fp.strapless_is_24bit & 1) 1723 lvds.lvds.script |= 0x0200; 1724 } 1725 1726 if (asyh->or.bpc == 8) 1727 lvds.lvds.script |= 0x0200; 1728 } 1729 1730 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1731 break; 1732 case DCB_OUTPUT_DP: 1733 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1734 1735 if (nv_encoder->link & 1) 1736 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1737 else 1738 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1739 1740 nv50_audio_enable(encoder, state, mode); 1741 break; 1742 default: 1743 BUG(); 1744 break; 1745 } 1746 1747 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1748 } 1749 1750 static const struct drm_encoder_helper_funcs 1751 nv50_sor_help = { 1752 .atomic_check = nv50_outp_atomic_check, 1753 .atomic_enable = nv50_sor_enable, 1754 .atomic_disable = nv50_sor_disable, 1755 }; 1756 1757 static void 1758 nv50_sor_destroy(struct drm_encoder *encoder) 1759 { 1760 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1761 nv50_mstm_del(&nv_encoder->dp.mstm); 1762 drm_encoder_cleanup(encoder); 1763 1764 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1765 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1766 1767 kfree(encoder); 1768 } 1769 1770 static const struct drm_encoder_funcs 1771 nv50_sor_func = { 1772 .destroy = nv50_sor_destroy, 1773 }; 1774 1775 static bool nv50_has_mst(struct nouveau_drm *drm) 1776 { 1777 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1778 u32 data; 1779 u8 ver, hdr, cnt, len; 1780 1781 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1782 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1783 } 1784 1785 static int 1786 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1787 { 1788 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1789 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1790 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1791 struct nouveau_encoder *nv_encoder; 1792 struct drm_encoder *encoder; 1793 struct nv50_disp *disp = nv50_disp(connector->dev); 1794 int type, ret; 1795 1796 switch (dcbe->type) { 1797 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1798 case DCB_OUTPUT_TMDS: 1799 case DCB_OUTPUT_DP: 1800 default: 1801 type = DRM_MODE_ENCODER_TMDS; 1802 break; 1803 } 1804 1805 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1806 if (!nv_encoder) 1807 return -ENOMEM; 1808 nv_encoder->dcb = dcbe; 1809 nv_encoder->update = nv50_sor_update; 1810 1811 encoder = to_drm_encoder(nv_encoder); 1812 encoder->possible_crtcs = dcbe->heads; 1813 encoder->possible_clones = 0; 1814 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1815 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1816 drm_encoder_helper_add(encoder, &nv50_sor_help); 1817 1818 drm_connector_attach_encoder(connector, encoder); 1819 1820 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1821 1822 if (dcbe->type == DCB_OUTPUT_DP) { 1823 struct nvkm_i2c_aux *aux = 1824 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1825 1826 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1827 1828 if (aux) { 1829 if (disp->disp->object.oclass < GF110_DISP) { 1830 /* HW has no support for address-only 1831 * transactions, so we're required to 1832 * use custom I2C-over-AUX code. 1833 */ 1834 nv_encoder->i2c = &aux->i2c; 1835 } else { 1836 nv_encoder->i2c = &nv_connector->aux.ddc; 1837 } 1838 nv_encoder->aux = aux; 1839 } 1840 1841 if (nv_connector->type != DCB_CONNECTOR_eDP && 1842 nv50_has_mst(drm)) { 1843 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1844 16, nv_connector->base.base.id, 1845 &nv_encoder->dp.mstm); 1846 if (ret) 1847 return ret; 1848 } 1849 } else { 1850 struct nvkm_i2c_bus *bus = 1851 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1852 if (bus) 1853 nv_encoder->i2c = &bus->i2c; 1854 } 1855 1856 return 0; 1857 } 1858 1859 /****************************************************************************** 1860 * PIOR 1861 *****************************************************************************/ 1862 static int 1863 nv50_pior_atomic_check(struct drm_encoder *encoder, 1864 struct drm_crtc_state *crtc_state, 1865 struct drm_connector_state *conn_state) 1866 { 1867 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1868 if (ret) 1869 return ret; 1870 crtc_state->adjusted_mode.clock *= 2; 1871 return 0; 1872 } 1873 1874 static void 1875 nv50_pior_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1876 { 1877 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1878 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1879 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1880 if (nv_encoder->crtc) 1881 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); 1882 nv_encoder->crtc = NULL; 1883 nv50_outp_release(nv_encoder); 1884 } 1885 1886 static void 1887 nv50_pior_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1888 { 1889 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1890 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1891 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1892 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1893 u32 ctrl = 0; 1894 1895 switch (nv_crtc->index) { 1896 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1897 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1898 default: 1899 WARN_ON(1); 1900 break; 1901 } 1902 1903 nv50_outp_acquire(nv_encoder, false); 1904 1905 switch (asyh->or.bpc) { 1906 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1907 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1908 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1909 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1910 } 1911 1912 switch (nv_encoder->dcb->type) { 1913 case DCB_OUTPUT_TMDS: 1914 case DCB_OUTPUT_DP: 1915 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1916 break; 1917 default: 1918 BUG(); 1919 break; 1920 } 1921 1922 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); 1923 nv_encoder->crtc = &nv_crtc->base; 1924 } 1925 1926 static const struct drm_encoder_helper_funcs 1927 nv50_pior_help = { 1928 .atomic_check = nv50_pior_atomic_check, 1929 .atomic_enable = nv50_pior_enable, 1930 .atomic_disable = nv50_pior_disable, 1931 }; 1932 1933 static void 1934 nv50_pior_destroy(struct drm_encoder *encoder) 1935 { 1936 drm_encoder_cleanup(encoder); 1937 kfree(encoder); 1938 } 1939 1940 static const struct drm_encoder_funcs 1941 nv50_pior_func = { 1942 .destroy = nv50_pior_destroy, 1943 }; 1944 1945 static int 1946 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1947 { 1948 struct drm_device *dev = connector->dev; 1949 struct nouveau_drm *drm = nouveau_drm(dev); 1950 struct nv50_disp *disp = nv50_disp(dev); 1951 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1952 struct nvkm_i2c_bus *bus = NULL; 1953 struct nvkm_i2c_aux *aux = NULL; 1954 struct i2c_adapter *ddc; 1955 struct nouveau_encoder *nv_encoder; 1956 struct drm_encoder *encoder; 1957 int type; 1958 1959 switch (dcbe->type) { 1960 case DCB_OUTPUT_TMDS: 1961 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1962 ddc = bus ? &bus->i2c : NULL; 1963 type = DRM_MODE_ENCODER_TMDS; 1964 break; 1965 case DCB_OUTPUT_DP: 1966 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1967 ddc = aux ? &aux->i2c : NULL; 1968 type = DRM_MODE_ENCODER_TMDS; 1969 break; 1970 default: 1971 return -ENODEV; 1972 } 1973 1974 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1975 if (!nv_encoder) 1976 return -ENOMEM; 1977 nv_encoder->dcb = dcbe; 1978 nv_encoder->i2c = ddc; 1979 nv_encoder->aux = aux; 1980 1981 encoder = to_drm_encoder(nv_encoder); 1982 encoder->possible_crtcs = dcbe->heads; 1983 encoder->possible_clones = 0; 1984 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1985 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1986 drm_encoder_helper_add(encoder, &nv50_pior_help); 1987 1988 drm_connector_attach_encoder(connector, encoder); 1989 1990 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1991 1992 return 0; 1993 } 1994 1995 /****************************************************************************** 1996 * Atomic 1997 *****************************************************************************/ 1998 1999 static void 2000 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 2001 { 2002 struct nouveau_drm *drm = nouveau_drm(state->dev); 2003 struct nv50_disp *disp = nv50_disp(drm->dev); 2004 struct nv50_core *core = disp->core; 2005 struct nv50_mstm *mstm; 2006 struct drm_encoder *encoder; 2007 2008 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 2009 2010 drm_for_each_encoder(encoder, drm->dev) { 2011 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2012 mstm = nouveau_encoder(encoder)->dp.mstm; 2013 if (mstm && mstm->modified) 2014 nv50_mstm_prepare(mstm); 2015 } 2016 } 2017 2018 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 2019 core->func->update(core, interlock, true); 2020 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 2021 disp->core->chan.base.device)) 2022 NV_ERROR(drm, "core notifier timeout\n"); 2023 2024 drm_for_each_encoder(encoder, drm->dev) { 2025 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2026 mstm = nouveau_encoder(encoder)->dp.mstm; 2027 if (mstm && mstm->modified) 2028 nv50_mstm_cleanup(mstm); 2029 } 2030 } 2031 } 2032 2033 static void 2034 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2035 { 2036 struct drm_plane_state *new_plane_state; 2037 struct drm_plane *plane; 2038 int i; 2039 2040 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2041 struct nv50_wndw *wndw = nv50_wndw(plane); 2042 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2043 if (wndw->func->update) 2044 wndw->func->update(wndw, interlock); 2045 } 2046 } 2047 } 2048 2049 static void 2050 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2051 { 2052 struct drm_device *dev = state->dev; 2053 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2054 struct drm_crtc *crtc; 2055 struct drm_plane_state *new_plane_state; 2056 struct drm_plane *plane; 2057 struct nouveau_drm *drm = nouveau_drm(dev); 2058 struct nv50_disp *disp = nv50_disp(dev); 2059 struct nv50_atom *atom = nv50_atom(state); 2060 struct nv50_core *core = disp->core; 2061 struct nv50_outp_atom *outp, *outt; 2062 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2063 int i; 2064 bool flushed = false; 2065 2066 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2067 nv50_crc_atomic_stop_reporting(state); 2068 drm_atomic_helper_wait_for_fences(dev, state, false); 2069 drm_atomic_helper_wait_for_dependencies(state); 2070 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2071 drm_atomic_helper_calc_timestamping_constants(state); 2072 2073 if (atom->lock_core) 2074 mutex_lock(&disp->mutex); 2075 2076 /* Disable head(s). */ 2077 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2078 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2079 struct nv50_head *head = nv50_head(crtc); 2080 2081 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2082 asyh->clr.mask, asyh->set.mask); 2083 2084 if (old_crtc_state->active && !new_crtc_state->active) { 2085 pm_runtime_put_noidle(dev->dev); 2086 drm_crtc_vblank_off(crtc); 2087 } 2088 2089 if (asyh->clr.mask) { 2090 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2091 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2092 } 2093 } 2094 2095 /* Disable plane(s). */ 2096 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2097 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2098 struct nv50_wndw *wndw = nv50_wndw(plane); 2099 2100 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2101 asyw->clr.mask, asyw->set.mask); 2102 if (!asyw->clr.mask) 2103 continue; 2104 2105 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2106 } 2107 2108 /* Disable output path(s). */ 2109 list_for_each_entry(outp, &atom->outp, head) { 2110 const struct drm_encoder_helper_funcs *help; 2111 struct drm_encoder *encoder; 2112 2113 encoder = outp->encoder; 2114 help = encoder->helper_private; 2115 2116 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2117 outp->clr.mask, outp->set.mask); 2118 2119 if (outp->clr.mask) { 2120 help->atomic_disable(encoder, state); 2121 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2122 if (outp->flush_disable) { 2123 nv50_disp_atomic_commit_wndw(state, interlock); 2124 nv50_disp_atomic_commit_core(state, interlock); 2125 memset(interlock, 0x00, sizeof(interlock)); 2126 2127 flushed = true; 2128 } 2129 } 2130 } 2131 2132 /* Flush disable. */ 2133 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2134 if (atom->flush_disable) { 2135 nv50_disp_atomic_commit_wndw(state, interlock); 2136 nv50_disp_atomic_commit_core(state, interlock); 2137 memset(interlock, 0x00, sizeof(interlock)); 2138 2139 flushed = true; 2140 } 2141 } 2142 2143 if (flushed) 2144 nv50_crc_atomic_release_notifier_contexts(state); 2145 nv50_crc_atomic_init_notifier_contexts(state); 2146 2147 /* Update output path(s). */ 2148 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2149 const struct drm_encoder_helper_funcs *help; 2150 struct drm_encoder *encoder; 2151 2152 encoder = outp->encoder; 2153 help = encoder->helper_private; 2154 2155 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2156 outp->set.mask, outp->clr.mask); 2157 2158 if (outp->set.mask) { 2159 help->atomic_enable(encoder, state); 2160 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2161 } 2162 2163 list_del(&outp->head); 2164 kfree(outp); 2165 } 2166 2167 /* Update head(s). */ 2168 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2169 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2170 struct nv50_head *head = nv50_head(crtc); 2171 2172 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2173 asyh->set.mask, asyh->clr.mask); 2174 2175 if (asyh->set.mask) { 2176 nv50_head_flush_set(head, asyh); 2177 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2178 } 2179 2180 if (new_crtc_state->active) { 2181 if (!old_crtc_state->active) { 2182 drm_crtc_vblank_on(crtc); 2183 pm_runtime_get_noresume(dev->dev); 2184 } 2185 if (new_crtc_state->event) 2186 drm_crtc_vblank_get(crtc); 2187 } 2188 } 2189 2190 /* Update window->head assignment. 2191 * 2192 * This has to happen in an update that's not interlocked with 2193 * any window channels to avoid hitting HW error checks. 2194 * 2195 *TODO: Proper handling of window ownership (Turing apparently 2196 * supports non-fixed mappings). 2197 */ 2198 if (core->assign_windows) { 2199 core->func->wndw.owner(core); 2200 nv50_disp_atomic_commit_core(state, interlock); 2201 core->assign_windows = false; 2202 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2203 } 2204 2205 /* Update plane(s). */ 2206 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2207 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2208 struct nv50_wndw *wndw = nv50_wndw(plane); 2209 2210 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2211 asyw->set.mask, asyw->clr.mask); 2212 if ( !asyw->set.mask && 2213 (!asyw->clr.mask || atom->flush_disable)) 2214 continue; 2215 2216 nv50_wndw_flush_set(wndw, interlock, asyw); 2217 } 2218 2219 /* Flush update. */ 2220 nv50_disp_atomic_commit_wndw(state, interlock); 2221 2222 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2223 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2224 interlock[NV50_DISP_INTERLOCK_OVLY] || 2225 interlock[NV50_DISP_INTERLOCK_WNDW] || 2226 !atom->state.legacy_cursor_update) 2227 nv50_disp_atomic_commit_core(state, interlock); 2228 else 2229 disp->core->func->update(disp->core, interlock, false); 2230 } 2231 2232 if (atom->lock_core) 2233 mutex_unlock(&disp->mutex); 2234 2235 /* Wait for HW to signal completion. */ 2236 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2237 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2238 struct nv50_wndw *wndw = nv50_wndw(plane); 2239 int ret = nv50_wndw_wait_armed(wndw, asyw); 2240 if (ret) 2241 NV_ERROR(drm, "%s: timeout\n", plane->name); 2242 } 2243 2244 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2245 if (new_crtc_state->event) { 2246 unsigned long flags; 2247 /* Get correct count/ts if racing with vblank irq */ 2248 if (new_crtc_state->active) 2249 drm_crtc_accurate_vblank_count(crtc); 2250 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2251 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2252 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2253 2254 new_crtc_state->event = NULL; 2255 if (new_crtc_state->active) 2256 drm_crtc_vblank_put(crtc); 2257 } 2258 } 2259 2260 nv50_crc_atomic_start_reporting(state); 2261 if (!flushed) 2262 nv50_crc_atomic_release_notifier_contexts(state); 2263 drm_atomic_helper_commit_hw_done(state); 2264 drm_atomic_helper_cleanup_planes(dev, state); 2265 drm_atomic_helper_commit_cleanup_done(state); 2266 drm_atomic_state_put(state); 2267 2268 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2269 pm_runtime_mark_last_busy(dev->dev); 2270 pm_runtime_put_autosuspend(dev->dev); 2271 } 2272 2273 static void 2274 nv50_disp_atomic_commit_work(struct work_struct *work) 2275 { 2276 struct drm_atomic_state *state = 2277 container_of(work, typeof(*state), commit_work); 2278 nv50_disp_atomic_commit_tail(state); 2279 } 2280 2281 static int 2282 nv50_disp_atomic_commit(struct drm_device *dev, 2283 struct drm_atomic_state *state, bool nonblock) 2284 { 2285 struct drm_plane_state *new_plane_state; 2286 struct drm_plane *plane; 2287 int ret, i; 2288 2289 ret = pm_runtime_get_sync(dev->dev); 2290 if (ret < 0 && ret != -EACCES) { 2291 pm_runtime_put_autosuspend(dev->dev); 2292 return ret; 2293 } 2294 2295 ret = drm_atomic_helper_setup_commit(state, nonblock); 2296 if (ret) 2297 goto done; 2298 2299 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2300 2301 ret = drm_atomic_helper_prepare_planes(dev, state); 2302 if (ret) 2303 goto done; 2304 2305 if (!nonblock) { 2306 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2307 if (ret) 2308 goto err_cleanup; 2309 } 2310 2311 ret = drm_atomic_helper_swap_state(state, true); 2312 if (ret) 2313 goto err_cleanup; 2314 2315 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2316 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2317 struct nv50_wndw *wndw = nv50_wndw(plane); 2318 2319 if (asyw->set.image) 2320 nv50_wndw_ntfy_enable(wndw, asyw); 2321 } 2322 2323 drm_atomic_state_get(state); 2324 2325 /* 2326 * Grab another RPM ref for the commit tail, which will release the 2327 * ref when it's finished 2328 */ 2329 pm_runtime_get_noresume(dev->dev); 2330 2331 if (nonblock) 2332 queue_work(system_unbound_wq, &state->commit_work); 2333 else 2334 nv50_disp_atomic_commit_tail(state); 2335 2336 err_cleanup: 2337 if (ret) 2338 drm_atomic_helper_cleanup_planes(dev, state); 2339 done: 2340 pm_runtime_put_autosuspend(dev->dev); 2341 return ret; 2342 } 2343 2344 static struct nv50_outp_atom * 2345 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2346 { 2347 struct nv50_outp_atom *outp; 2348 2349 list_for_each_entry(outp, &atom->outp, head) { 2350 if (outp->encoder == encoder) 2351 return outp; 2352 } 2353 2354 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2355 if (!outp) 2356 return ERR_PTR(-ENOMEM); 2357 2358 list_add(&outp->head, &atom->outp); 2359 outp->encoder = encoder; 2360 return outp; 2361 } 2362 2363 static int 2364 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2365 struct drm_connector_state *old_connector_state) 2366 { 2367 struct drm_encoder *encoder = old_connector_state->best_encoder; 2368 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2369 struct drm_crtc *crtc; 2370 struct nv50_outp_atom *outp; 2371 2372 if (!(crtc = old_connector_state->crtc)) 2373 return 0; 2374 2375 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2376 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2377 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2378 outp = nv50_disp_outp_atomic_add(atom, encoder); 2379 if (IS_ERR(outp)) 2380 return PTR_ERR(outp); 2381 2382 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2383 outp->flush_disable = true; 2384 atom->flush_disable = true; 2385 } 2386 outp->clr.ctrl = true; 2387 atom->lock_core = true; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static int 2394 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2395 struct drm_connector_state *connector_state) 2396 { 2397 struct drm_encoder *encoder = connector_state->best_encoder; 2398 struct drm_crtc_state *new_crtc_state; 2399 struct drm_crtc *crtc; 2400 struct nv50_outp_atom *outp; 2401 2402 if (!(crtc = connector_state->crtc)) 2403 return 0; 2404 2405 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2406 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2407 outp = nv50_disp_outp_atomic_add(atom, encoder); 2408 if (IS_ERR(outp)) 2409 return PTR_ERR(outp); 2410 2411 outp->set.ctrl = true; 2412 atom->lock_core = true; 2413 } 2414 2415 return 0; 2416 } 2417 2418 static int 2419 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2420 { 2421 struct nv50_atom *atom = nv50_atom(state); 2422 struct nv50_core *core = nv50_disp(dev)->core; 2423 struct drm_connector_state *old_connector_state, *new_connector_state; 2424 struct drm_connector *connector; 2425 struct drm_crtc_state *new_crtc_state; 2426 struct drm_crtc *crtc; 2427 struct nv50_head *head; 2428 struct nv50_head_atom *asyh; 2429 int ret, i; 2430 2431 if (core->assign_windows && core->func->head->static_wndw_map) { 2432 drm_for_each_crtc(crtc, dev) { 2433 new_crtc_state = drm_atomic_get_crtc_state(state, 2434 crtc); 2435 if (IS_ERR(new_crtc_state)) 2436 return PTR_ERR(new_crtc_state); 2437 2438 head = nv50_head(crtc); 2439 asyh = nv50_head_atom(new_crtc_state); 2440 core->func->head->static_wndw_map(head, asyh); 2441 } 2442 } 2443 2444 /* We need to handle colour management on a per-plane basis. */ 2445 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2446 if (new_crtc_state->color_mgmt_changed) { 2447 ret = drm_atomic_add_affected_planes(state, crtc); 2448 if (ret) 2449 return ret; 2450 } 2451 } 2452 2453 ret = drm_atomic_helper_check(dev, state); 2454 if (ret) 2455 return ret; 2456 2457 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2458 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2459 if (ret) 2460 return ret; 2461 2462 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2463 if (ret) 2464 return ret; 2465 } 2466 2467 ret = drm_dp_mst_atomic_check(state); 2468 if (ret) 2469 return ret; 2470 2471 nv50_crc_atomic_check_outp(atom); 2472 2473 return 0; 2474 } 2475 2476 static void 2477 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2478 { 2479 struct nv50_atom *atom = nv50_atom(state); 2480 struct nv50_outp_atom *outp, *outt; 2481 2482 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2483 list_del(&outp->head); 2484 kfree(outp); 2485 } 2486 2487 drm_atomic_state_default_clear(state); 2488 } 2489 2490 static void 2491 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2492 { 2493 struct nv50_atom *atom = nv50_atom(state); 2494 drm_atomic_state_default_release(&atom->state); 2495 kfree(atom); 2496 } 2497 2498 static struct drm_atomic_state * 2499 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2500 { 2501 struct nv50_atom *atom; 2502 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2503 drm_atomic_state_init(dev, &atom->state) < 0) { 2504 kfree(atom); 2505 return NULL; 2506 } 2507 INIT_LIST_HEAD(&atom->outp); 2508 return &atom->state; 2509 } 2510 2511 static const struct drm_mode_config_funcs 2512 nv50_disp_func = { 2513 .fb_create = nouveau_user_framebuffer_create, 2514 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2515 .atomic_check = nv50_disp_atomic_check, 2516 .atomic_commit = nv50_disp_atomic_commit, 2517 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2518 .atomic_state_clear = nv50_disp_atomic_state_clear, 2519 .atomic_state_free = nv50_disp_atomic_state_free, 2520 }; 2521 2522 /****************************************************************************** 2523 * Init 2524 *****************************************************************************/ 2525 2526 static void 2527 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2528 { 2529 struct nouveau_drm *drm = nouveau_drm(dev); 2530 struct drm_encoder *encoder; 2531 struct drm_plane *plane; 2532 2533 drm_for_each_plane(plane, dev) { 2534 struct nv50_wndw *wndw = nv50_wndw(plane); 2535 if (plane->funcs != &nv50_wndw) 2536 continue; 2537 nv50_wndw_fini(wndw); 2538 } 2539 2540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2541 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2542 nv50_mstm_fini(nouveau_encoder(encoder)); 2543 } 2544 2545 if (!runtime) 2546 cancel_work_sync(&drm->hpd_work); 2547 } 2548 2549 static int 2550 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2551 { 2552 struct nv50_core *core = nv50_disp(dev)->core; 2553 struct drm_encoder *encoder; 2554 struct drm_plane *plane; 2555 2556 if (resume || runtime) 2557 core->func->init(core); 2558 2559 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2560 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2561 struct nouveau_encoder *nv_encoder = 2562 nouveau_encoder(encoder); 2563 nv50_mstm_init(nv_encoder, runtime); 2564 } 2565 } 2566 2567 drm_for_each_plane(plane, dev) { 2568 struct nv50_wndw *wndw = nv50_wndw(plane); 2569 if (plane->funcs != &nv50_wndw) 2570 continue; 2571 nv50_wndw_init(wndw); 2572 } 2573 2574 return 0; 2575 } 2576 2577 static void 2578 nv50_display_destroy(struct drm_device *dev) 2579 { 2580 struct nv50_disp *disp = nv50_disp(dev); 2581 2582 nv50_audio_component_fini(nouveau_drm(dev)); 2583 2584 nvif_object_unmap(&disp->caps); 2585 nvif_object_dtor(&disp->caps); 2586 nv50_core_del(&disp->core); 2587 2588 nouveau_bo_unmap(disp->sync); 2589 if (disp->sync) 2590 nouveau_bo_unpin(disp->sync); 2591 nouveau_bo_ref(NULL, &disp->sync); 2592 2593 nouveau_display(dev)->priv = NULL; 2594 kfree(disp); 2595 } 2596 2597 int 2598 nv50_display_create(struct drm_device *dev) 2599 { 2600 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2601 struct nouveau_drm *drm = nouveau_drm(dev); 2602 struct dcb_table *dcb = &drm->vbios.dcb; 2603 struct drm_connector *connector, *tmp; 2604 struct nv50_disp *disp; 2605 struct dcb_output *dcbe; 2606 int crtcs, ret, i; 2607 bool has_mst = nv50_has_mst(drm); 2608 2609 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2610 if (!disp) 2611 return -ENOMEM; 2612 2613 mutex_init(&disp->mutex); 2614 2615 nouveau_display(dev)->priv = disp; 2616 nouveau_display(dev)->dtor = nv50_display_destroy; 2617 nouveau_display(dev)->init = nv50_display_init; 2618 nouveau_display(dev)->fini = nv50_display_fini; 2619 disp->disp = &nouveau_display(dev)->disp; 2620 dev->mode_config.funcs = &nv50_disp_func; 2621 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2622 dev->mode_config.normalize_zpos = true; 2623 2624 /* small shared memory area we use for notifiers and semaphores */ 2625 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2626 NOUVEAU_GEM_DOMAIN_VRAM, 2627 0, 0x0000, NULL, NULL, &disp->sync); 2628 if (!ret) { 2629 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2630 if (!ret) { 2631 ret = nouveau_bo_map(disp->sync); 2632 if (ret) 2633 nouveau_bo_unpin(disp->sync); 2634 } 2635 if (ret) 2636 nouveau_bo_ref(NULL, &disp->sync); 2637 } 2638 2639 if (ret) 2640 goto out; 2641 2642 /* allocate master evo channel */ 2643 ret = nv50_core_new(drm, &disp->core); 2644 if (ret) 2645 goto out; 2646 2647 disp->core->func->init(disp->core); 2648 if (disp->core->func->caps_init) { 2649 ret = disp->core->func->caps_init(drm, disp); 2650 if (ret) 2651 goto out; 2652 } 2653 2654 /* Assign the correct format modifiers */ 2655 if (disp->disp->object.oclass >= TU102_DISP) 2656 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2657 else 2658 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2659 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2660 else 2661 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2662 2663 /* create crtc objects to represent the hw heads */ 2664 if (disp->disp->object.oclass >= GV100_DISP) 2665 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2666 else 2667 if (disp->disp->object.oclass >= GF110_DISP) 2668 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2669 else 2670 crtcs = 0x3; 2671 2672 for (i = 0; i < fls(crtcs); i++) { 2673 struct nv50_head *head; 2674 2675 if (!(crtcs & (1 << i))) 2676 continue; 2677 2678 head = nv50_head_create(dev, i); 2679 if (IS_ERR(head)) { 2680 ret = PTR_ERR(head); 2681 goto out; 2682 } 2683 2684 if (has_mst) { 2685 head->msto = nv50_msto_new(dev, head, i); 2686 if (IS_ERR(head->msto)) { 2687 ret = PTR_ERR(head->msto); 2688 head->msto = NULL; 2689 goto out; 2690 } 2691 2692 /* 2693 * FIXME: This is a hack to workaround the following 2694 * issues: 2695 * 2696 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2697 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2698 * 2699 * Once these issues are closed, this should be 2700 * removed 2701 */ 2702 head->msto->encoder.possible_crtcs = crtcs; 2703 } 2704 } 2705 2706 /* create encoder/connector objects based on VBIOS DCB table */ 2707 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2708 connector = nouveau_connector_create(dev, dcbe); 2709 if (IS_ERR(connector)) 2710 continue; 2711 2712 if (dcbe->location == DCB_LOC_ON_CHIP) { 2713 switch (dcbe->type) { 2714 case DCB_OUTPUT_TMDS: 2715 case DCB_OUTPUT_LVDS: 2716 case DCB_OUTPUT_DP: 2717 ret = nv50_sor_create(connector, dcbe); 2718 break; 2719 case DCB_OUTPUT_ANALOG: 2720 ret = nv50_dac_create(connector, dcbe); 2721 break; 2722 default: 2723 ret = -ENODEV; 2724 break; 2725 } 2726 } else { 2727 ret = nv50_pior_create(connector, dcbe); 2728 } 2729 2730 if (ret) { 2731 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2732 dcbe->location, dcbe->type, 2733 ffs(dcbe->or) - 1, ret); 2734 ret = 0; 2735 } 2736 } 2737 2738 /* cull any connectors we created that don't have an encoder */ 2739 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2740 if (connector->possible_encoders) 2741 continue; 2742 2743 NV_WARN(drm, "%s has no encoders, removing\n", 2744 connector->name); 2745 connector->funcs->destroy(connector); 2746 } 2747 2748 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2749 dev->vblank_disable_immediate = true; 2750 2751 nv50_audio_component_init(drm); 2752 2753 out: 2754 if (ret) 2755 nv50_display_destroy(dev); 2756 return ret; 2757 } 2758 2759 /****************************************************************************** 2760 * Format modifiers 2761 *****************************************************************************/ 2762 2763 /**************************************************************** 2764 * Log2(block height) ----------------------------+ * 2765 * Page Kind ----------------------------------+ | * 2766 * Gob Height/Page Kind Generation ------+ | | * 2767 * Sector layout -------+ | | | * 2768 * Compression ------+ | | | | */ 2769 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2770 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2771 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2772 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2773 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2774 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2775 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2776 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2777 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2778 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2779 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2780 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2781 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2782 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2783 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2784 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2785 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2786 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2787 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2788 DRM_FORMAT_MOD_LINEAR, 2789 DRM_FORMAT_MOD_INVALID 2790 }; 2791 2792 /**************************************************************** 2793 * Log2(block height) ----------------------------+ * 2794 * Page Kind ----------------------------------+ | * 2795 * Gob Height/Page Kind Generation ------+ | | * 2796 * Sector layout -------+ | | | * 2797 * Compression ------+ | | | | */ 2798 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2799 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2800 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2801 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2802 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2803 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2804 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2805 DRM_FORMAT_MOD_LINEAR, 2806 DRM_FORMAT_MOD_INVALID 2807 }; 2808