1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fb_helper.h> 37 #include <drm/drm_plane_helper.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_scdc_helper.h> 40 #include <drm/drm_edid.h> 41 42 #include <nvif/class.h> 43 #include <nvif/cl0002.h> 44 #include <nvif/cl5070.h> 45 #include <nvif/cl507d.h> 46 #include <nvif/event.h> 47 48 #include "nouveau_drv.h" 49 #include "nouveau_dma.h" 50 #include "nouveau_gem.h" 51 #include "nouveau_connector.h" 52 #include "nouveau_encoder.h" 53 #include "nouveau_fence.h" 54 #include "nouveau_fbcon.h" 55 56 #include <subdev/bios/dp.h> 57 58 /****************************************************************************** 59 * Atomic state 60 *****************************************************************************/ 61 62 struct nv50_outp_atom { 63 struct list_head head; 64 65 struct drm_encoder *encoder; 66 bool flush_disable; 67 68 union nv50_outp_atom_mask { 69 struct { 70 bool ctrl:1; 71 }; 72 u8 mask; 73 } set, clr; 74 }; 75 76 /****************************************************************************** 77 * EVO channel 78 *****************************************************************************/ 79 80 static int 81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 82 const s32 *oclass, u8 head, void *data, u32 size, 83 struct nv50_chan *chan) 84 { 85 struct nvif_sclass *sclass; 86 int ret, i, n; 87 88 chan->device = device; 89 90 ret = n = nvif_object_sclass_get(disp, &sclass); 91 if (ret < 0) 92 return ret; 93 94 while (oclass[0]) { 95 for (i = 0; i < n; i++) { 96 if (sclass[i].oclass == oclass[0]) { 97 ret = nvif_object_init(disp, 0, oclass[0], 98 data, size, &chan->user); 99 if (ret == 0) 100 nvif_object_map(&chan->user, NULL, 0); 101 nvif_object_sclass_put(&sclass); 102 return ret; 103 } 104 } 105 oclass++; 106 } 107 108 nvif_object_sclass_put(&sclass); 109 return -ENOSYS; 110 } 111 112 static void 113 nv50_chan_destroy(struct nv50_chan *chan) 114 { 115 nvif_object_fini(&chan->user); 116 } 117 118 /****************************************************************************** 119 * DMA EVO channel 120 *****************************************************************************/ 121 122 void 123 nv50_dmac_destroy(struct nv50_dmac *dmac) 124 { 125 nvif_object_fini(&dmac->vram); 126 nvif_object_fini(&dmac->sync); 127 128 nv50_chan_destroy(&dmac->base); 129 130 nvif_mem_fini(&dmac->push); 131 } 132 133 int 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 136 struct nv50_dmac *dmac) 137 { 138 struct nouveau_cli *cli = (void *)device->object.client; 139 struct nv50_disp_core_channel_dma_v0 *args = data; 140 u8 type = NVIF_MEM_COHERENT; 141 int ret; 142 143 mutex_init(&dmac->lock); 144 145 /* Pascal added support for 47-bit physical addresses, but some 146 * parts of EVO still only accept 40-bit PAs. 147 * 148 * To avoid issues on systems with large amounts of RAM, and on 149 * systems where an IOMMU maps pages at a high address, we need 150 * to allocate push buffers in VRAM instead. 151 * 152 * This appears to match NVIDIA's behaviour on Pascal. 153 */ 154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 155 type |= NVIF_MEM_VRAM; 156 157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 158 if (ret) 159 return ret; 160 161 dmac->ptr = dmac->push.object.map.ptr; 162 163 args->pushbuf = nvif_handle(&dmac->push.object); 164 165 ret = nv50_chan_create(device, disp, oclass, head, data, size, 166 &dmac->base); 167 if (ret) 168 return ret; 169 170 if (!syncbuf) 171 return 0; 172 173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 174 &(struct nv_dma_v0) { 175 .target = NV_DMA_V0_TARGET_VRAM, 176 .access = NV_DMA_V0_ACCESS_RDWR, 177 .start = syncbuf + 0x0000, 178 .limit = syncbuf + 0x0fff, 179 }, sizeof(struct nv_dma_v0), 180 &dmac->sync); 181 if (ret) 182 return ret; 183 184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 185 &(struct nv_dma_v0) { 186 .target = NV_DMA_V0_TARGET_VRAM, 187 .access = NV_DMA_V0_ACCESS_RDWR, 188 .start = 0, 189 .limit = device->info.ram_user - 1, 190 }, sizeof(struct nv_dma_v0), 191 &dmac->vram); 192 if (ret) 193 return ret; 194 195 return ret; 196 } 197 198 /****************************************************************************** 199 * EVO channel helpers 200 *****************************************************************************/ 201 static void 202 evo_flush(struct nv50_dmac *dmac) 203 { 204 /* Push buffer fetches are not coherent with BAR1, we need to ensure 205 * writes have been flushed right through to VRAM before writing PUT. 206 */ 207 if (dmac->push.type & NVIF_MEM_VRAM) { 208 struct nvif_device *device = dmac->base.device; 209 nvif_wr32(&device->object, 0x070000, 0x00000001); 210 nvif_msec(device, 2000, 211 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 212 break; 213 ); 214 } 215 } 216 217 u32 * 218 evo_wait(struct nv50_dmac *evoc, int nr) 219 { 220 struct nv50_dmac *dmac = evoc; 221 struct nvif_device *device = dmac->base.device; 222 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 223 224 mutex_lock(&dmac->lock); 225 if (put + nr >= (PAGE_SIZE / 4) - 8) { 226 dmac->ptr[put] = 0x20000000; 227 evo_flush(dmac); 228 229 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 230 if (nvif_msec(device, 2000, 231 if (!nvif_rd32(&dmac->base.user, 0x0004)) 232 break; 233 ) < 0) { 234 mutex_unlock(&dmac->lock); 235 pr_err("nouveau: evo channel stalled\n"); 236 return NULL; 237 } 238 239 put = 0; 240 } 241 242 return dmac->ptr + put; 243 } 244 245 void 246 evo_kick(u32 *push, struct nv50_dmac *evoc) 247 { 248 struct nv50_dmac *dmac = evoc; 249 250 evo_flush(dmac); 251 252 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 253 mutex_unlock(&dmac->lock); 254 } 255 256 /****************************************************************************** 257 * Output path helpers 258 *****************************************************************************/ 259 static void 260 nv50_outp_release(struct nouveau_encoder *nv_encoder) 261 { 262 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 263 struct { 264 struct nv50_disp_mthd_v1 base; 265 } args = { 266 .base.version = 1, 267 .base.method = NV50_DISP_MTHD_V1_RELEASE, 268 .base.hasht = nv_encoder->dcb->hasht, 269 .base.hashm = nv_encoder->dcb->hashm, 270 }; 271 272 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 273 nv_encoder->or = -1; 274 nv_encoder->link = 0; 275 } 276 277 static int 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder) 279 { 280 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 281 struct nv50_disp *disp = nv50_disp(drm->dev); 282 struct { 283 struct nv50_disp_mthd_v1 base; 284 struct nv50_disp_acquire_v0 info; 285 } args = { 286 .base.version = 1, 287 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 288 .base.hasht = nv_encoder->dcb->hasht, 289 .base.hashm = nv_encoder->dcb->hashm, 290 }; 291 int ret; 292 293 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 294 if (ret) { 295 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 296 return ret; 297 } 298 299 nv_encoder->or = args.info.or; 300 nv_encoder->link = args.info.link; 301 return 0; 302 } 303 304 static int 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 306 struct drm_crtc_state *crtc_state, 307 struct drm_connector_state *conn_state, 308 struct drm_display_mode *native_mode) 309 { 310 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 311 struct drm_display_mode *mode = &crtc_state->mode; 312 struct drm_connector *connector = conn_state->connector; 313 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 314 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 315 316 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 317 asyc->scaler.full = false; 318 if (!native_mode) 319 return 0; 320 321 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 322 switch (connector->connector_type) { 323 case DRM_MODE_CONNECTOR_LVDS: 324 case DRM_MODE_CONNECTOR_eDP: 325 /* Don't force scaler for EDID modes with 326 * same size as the native one (e.g. different 327 * refresh rate) 328 */ 329 if (adjusted_mode->hdisplay == native_mode->hdisplay && 330 adjusted_mode->vdisplay == native_mode->vdisplay && 331 adjusted_mode->type & DRM_MODE_TYPE_DRIVER) 332 break; 333 mode = native_mode; 334 asyc->scaler.full = true; 335 break; 336 default: 337 break; 338 } 339 } else { 340 mode = native_mode; 341 } 342 343 if (!drm_mode_equal(adjusted_mode, mode)) { 344 drm_mode_copy(adjusted_mode, mode); 345 crtc_state->mode_changed = true; 346 } 347 348 return 0; 349 } 350 351 static int 352 nv50_outp_atomic_check(struct drm_encoder *encoder, 353 struct drm_crtc_state *crtc_state, 354 struct drm_connector_state *conn_state) 355 { 356 struct nouveau_connector *nv_connector = 357 nouveau_connector(conn_state->connector); 358 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 359 nv_connector->native_mode); 360 } 361 362 /****************************************************************************** 363 * DAC 364 *****************************************************************************/ 365 static void 366 nv50_dac_disable(struct drm_encoder *encoder) 367 { 368 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 369 struct nv50_core *core = nv50_disp(encoder->dev)->core; 370 if (nv_encoder->crtc) 371 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 372 nv_encoder->crtc = NULL; 373 nv50_outp_release(nv_encoder); 374 } 375 376 static void 377 nv50_dac_enable(struct drm_encoder *encoder) 378 { 379 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 380 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 381 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 382 struct nv50_core *core = nv50_disp(encoder->dev)->core; 383 384 nv50_outp_acquire(nv_encoder); 385 386 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 387 asyh->or.depth = 0; 388 389 nv_encoder->crtc = encoder->crtc; 390 } 391 392 static enum drm_connector_status 393 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 394 { 395 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 396 struct nv50_disp *disp = nv50_disp(encoder->dev); 397 struct { 398 struct nv50_disp_mthd_v1 base; 399 struct nv50_disp_dac_load_v0 load; 400 } args = { 401 .base.version = 1, 402 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 403 .base.hasht = nv_encoder->dcb->hasht, 404 .base.hashm = nv_encoder->dcb->hashm, 405 }; 406 int ret; 407 408 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 409 if (args.load.data == 0) 410 args.load.data = 340; 411 412 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 413 if (ret || !args.load.load) 414 return connector_status_disconnected; 415 416 return connector_status_connected; 417 } 418 419 static const struct drm_encoder_helper_funcs 420 nv50_dac_help = { 421 .atomic_check = nv50_outp_atomic_check, 422 .enable = nv50_dac_enable, 423 .disable = nv50_dac_disable, 424 .detect = nv50_dac_detect 425 }; 426 427 static void 428 nv50_dac_destroy(struct drm_encoder *encoder) 429 { 430 drm_encoder_cleanup(encoder); 431 kfree(encoder); 432 } 433 434 static const struct drm_encoder_funcs 435 nv50_dac_func = { 436 .destroy = nv50_dac_destroy, 437 }; 438 439 static int 440 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 441 { 442 struct nouveau_drm *drm = nouveau_drm(connector->dev); 443 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 444 struct nvkm_i2c_bus *bus; 445 struct nouveau_encoder *nv_encoder; 446 struct drm_encoder *encoder; 447 int type = DRM_MODE_ENCODER_DAC; 448 449 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 450 if (!nv_encoder) 451 return -ENOMEM; 452 nv_encoder->dcb = dcbe; 453 454 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 455 if (bus) 456 nv_encoder->i2c = &bus->i2c; 457 458 encoder = to_drm_encoder(nv_encoder); 459 encoder->possible_crtcs = dcbe->heads; 460 encoder->possible_clones = 0; 461 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 462 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 463 drm_encoder_helper_add(encoder, &nv50_dac_help); 464 465 drm_connector_attach_encoder(connector, encoder); 466 return 0; 467 } 468 469 /****************************************************************************** 470 * Audio 471 *****************************************************************************/ 472 static void 473 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 474 { 475 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 476 struct nv50_disp *disp = nv50_disp(encoder->dev); 477 struct { 478 struct nv50_disp_mthd_v1 base; 479 struct nv50_disp_sor_hda_eld_v0 eld; 480 } args = { 481 .base.version = 1, 482 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 483 .base.hasht = nv_encoder->dcb->hasht, 484 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 485 (0x0100 << nv_crtc->index), 486 }; 487 488 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 489 } 490 491 static void 492 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 493 { 494 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 495 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 496 struct nouveau_connector *nv_connector; 497 struct nv50_disp *disp = nv50_disp(encoder->dev); 498 struct __packed { 499 struct { 500 struct nv50_disp_mthd_v1 mthd; 501 struct nv50_disp_sor_hda_eld_v0 eld; 502 } base; 503 u8 data[sizeof(nv_connector->base.eld)]; 504 } args = { 505 .base.mthd.version = 1, 506 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 507 .base.mthd.hasht = nv_encoder->dcb->hasht, 508 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 509 (0x0100 << nv_crtc->index), 510 }; 511 512 nv_connector = nouveau_encoder_connector_get(nv_encoder); 513 if (!drm_detect_monitor_audio(nv_connector->edid)) 514 return; 515 516 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 517 518 nvif_mthd(&disp->disp->object, 0, &args, 519 sizeof(args.base) + drm_eld_size(args.data)); 520 } 521 522 /****************************************************************************** 523 * HDMI 524 *****************************************************************************/ 525 static void 526 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 527 { 528 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 529 struct nv50_disp *disp = nv50_disp(encoder->dev); 530 struct { 531 struct nv50_disp_mthd_v1 base; 532 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 533 } args = { 534 .base.version = 1, 535 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 536 .base.hasht = nv_encoder->dcb->hasht, 537 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 538 (0x0100 << nv_crtc->index), 539 }; 540 541 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 542 } 543 544 static void 545 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 546 { 547 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 548 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 549 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 550 struct nv50_disp *disp = nv50_disp(encoder->dev); 551 struct { 552 struct nv50_disp_mthd_v1 base; 553 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 554 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 555 } args = { 556 .base.version = 1, 557 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 558 .base.hasht = nv_encoder->dcb->hasht, 559 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 560 (0x0100 << nv_crtc->index), 561 .pwr.state = 1, 562 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 563 }; 564 struct nouveau_connector *nv_connector; 565 struct drm_hdmi_info *hdmi; 566 u32 max_ac_packet; 567 union hdmi_infoframe avi_frame; 568 union hdmi_infoframe vendor_frame; 569 bool high_tmds_clock_ratio = false, scrambling = false; 570 u8 config; 571 int ret; 572 int size; 573 574 nv_connector = nouveau_encoder_connector_get(nv_encoder); 575 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 576 return; 577 578 hdmi = &nv_connector->base.display_info.hdmi; 579 580 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 581 &nv_connector->base, mode); 582 if (!ret) { 583 /* We have an AVI InfoFrame, populate it to the display */ 584 args.pwr.avi_infoframe_length 585 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 586 } 587 588 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 589 &nv_connector->base, mode); 590 if (!ret) { 591 /* We have a Vendor InfoFrame, populate it to the display */ 592 args.pwr.vendor_infoframe_length 593 = hdmi_infoframe_pack(&vendor_frame, 594 args.infoframes 595 + args.pwr.avi_infoframe_length, 596 17); 597 } 598 599 max_ac_packet = mode->htotal - mode->hdisplay; 600 max_ac_packet -= args.pwr.rekey; 601 max_ac_packet -= 18; /* constant from tegra */ 602 args.pwr.max_ac_packet = max_ac_packet / 32; 603 604 if (hdmi->scdc.scrambling.supported) { 605 high_tmds_clock_ratio = mode->clock > 340000; 606 scrambling = high_tmds_clock_ratio || 607 hdmi->scdc.scrambling.low_rates; 608 } 609 610 args.pwr.scdc = 611 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 612 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 613 614 size = sizeof(args.base) 615 + sizeof(args.pwr) 616 + args.pwr.avi_infoframe_length 617 + args.pwr.vendor_infoframe_length; 618 nvif_mthd(&disp->disp->object, 0, &args, size); 619 620 nv50_audio_enable(encoder, mode); 621 622 /* If SCDC is supported by the downstream monitor, update 623 * divider / scrambling settings to what we programmed above. 624 */ 625 if (!hdmi->scdc.scrambling.supported) 626 return; 627 628 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 629 if (ret < 0) { 630 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 631 return; 632 } 633 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 634 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 635 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 636 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 637 if (ret < 0) 638 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 639 config, ret); 640 } 641 642 /****************************************************************************** 643 * MST 644 *****************************************************************************/ 645 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 646 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 647 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 648 649 struct nv50_mstm { 650 struct nouveau_encoder *outp; 651 652 struct drm_dp_mst_topology_mgr mgr; 653 struct nv50_msto *msto[4]; 654 655 bool modified; 656 bool disabled; 657 int links; 658 }; 659 660 struct nv50_mstc { 661 struct nv50_mstm *mstm; 662 struct drm_dp_mst_port *port; 663 struct drm_connector connector; 664 665 struct drm_display_mode *native; 666 struct edid *edid; 667 }; 668 669 struct nv50_msto { 670 struct drm_encoder encoder; 671 672 struct nv50_head *head; 673 struct nv50_mstc *mstc; 674 bool disabled; 675 }; 676 677 static struct drm_dp_payload * 678 nv50_msto_payload(struct nv50_msto *msto) 679 { 680 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 681 struct nv50_mstc *mstc = msto->mstc; 682 struct nv50_mstm *mstm = mstc->mstm; 683 int vcpi = mstc->port->vcpi.vcpi, i; 684 685 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 686 687 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 688 for (i = 0; i < mstm->mgr.max_payloads; i++) { 689 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 690 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 691 mstm->outp->base.base.name, i, payload->vcpi, 692 payload->start_slot, payload->num_slots); 693 } 694 695 for (i = 0; i < mstm->mgr.max_payloads; i++) { 696 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 697 if (payload->vcpi == vcpi) 698 return payload; 699 } 700 701 return NULL; 702 } 703 704 static void 705 nv50_msto_cleanup(struct nv50_msto *msto) 706 { 707 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 708 struct nv50_mstc *mstc = msto->mstc; 709 struct nv50_mstm *mstm = mstc->mstm; 710 711 if (!msto->disabled) 712 return; 713 714 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 715 716 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 717 718 msto->mstc = NULL; 719 msto->head = NULL; 720 msto->disabled = false; 721 } 722 723 static void 724 nv50_msto_prepare(struct nv50_msto *msto) 725 { 726 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 727 struct nv50_mstc *mstc = msto->mstc; 728 struct nv50_mstm *mstm = mstc->mstm; 729 struct { 730 struct nv50_disp_mthd_v1 base; 731 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 732 } args = { 733 .base.version = 1, 734 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 735 .base.hasht = mstm->outp->dcb->hasht, 736 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 737 (0x0100 << msto->head->base.index), 738 }; 739 740 mutex_lock(&mstm->mgr.payload_lock); 741 742 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 743 if (mstc->port->vcpi.vcpi > 0) { 744 struct drm_dp_payload *payload = nv50_msto_payload(msto); 745 if (payload) { 746 args.vcpi.start_slot = payload->start_slot; 747 args.vcpi.num_slots = payload->num_slots; 748 args.vcpi.pbn = mstc->port->vcpi.pbn; 749 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 750 } 751 } 752 753 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 754 msto->encoder.name, msto->head->base.base.name, 755 args.vcpi.start_slot, args.vcpi.num_slots, 756 args.vcpi.pbn, args.vcpi.aligned_pbn); 757 758 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 759 mutex_unlock(&mstm->mgr.payload_lock); 760 } 761 762 static int 763 nv50_msto_atomic_check(struct drm_encoder *encoder, 764 struct drm_crtc_state *crtc_state, 765 struct drm_connector_state *conn_state) 766 { 767 struct drm_atomic_state *state = crtc_state->state; 768 struct drm_connector *connector = conn_state->connector; 769 struct nv50_mstc *mstc = nv50_mstc(connector); 770 struct nv50_mstm *mstm = mstc->mstm; 771 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 772 int slots; 773 774 if (crtc_state->mode_changed || crtc_state->connectors_changed) { 775 /* 776 * When restoring duplicated states, we need to make sure that 777 * the bw remains the same and avoid recalculating it, as the 778 * connector's bpc may have changed after the state was 779 * duplicated 780 */ 781 if (!state->duplicated) { 782 const int bpp = connector->display_info.bpc * 3; 783 const int clock = crtc_state->adjusted_mode.clock; 784 785 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp); 786 } 787 788 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, 789 mstc->port, 790 asyh->dp.pbn); 791 if (slots < 0) 792 return slots; 793 794 asyh->dp.tu = slots; 795 } 796 797 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 798 mstc->native); 799 } 800 801 static void 802 nv50_msto_enable(struct drm_encoder *encoder) 803 { 804 struct nv50_head *head = nv50_head(encoder->crtc); 805 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 806 struct nv50_msto *msto = nv50_msto(encoder); 807 struct nv50_mstc *mstc = NULL; 808 struct nv50_mstm *mstm = NULL; 809 struct drm_connector *connector; 810 struct drm_connector_list_iter conn_iter; 811 u8 proto, depth; 812 bool r; 813 814 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 815 drm_for_each_connector_iter(connector, &conn_iter) { 816 if (connector->state->best_encoder == &msto->encoder) { 817 mstc = nv50_mstc(connector); 818 mstm = mstc->mstm; 819 break; 820 } 821 } 822 drm_connector_list_iter_end(&conn_iter); 823 824 if (WARN_ON(!mstc)) 825 return; 826 827 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 828 armh->dp.tu); 829 if (!r) 830 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 831 832 if (!mstm->links++) 833 nv50_outp_acquire(mstm->outp); 834 835 if (mstm->outp->link & 1) 836 proto = 0x8; 837 else 838 proto = 0x9; 839 840 switch (mstc->connector.display_info.bpc) { 841 case 6: depth = 0x2; break; 842 case 8: depth = 0x5; break; 843 case 10: 844 default: depth = 0x6; break; 845 } 846 847 mstm->outp->update(mstm->outp, head->base.index, armh, proto, depth); 848 849 msto->head = head; 850 msto->mstc = mstc; 851 mstm->modified = true; 852 } 853 854 static void 855 nv50_msto_disable(struct drm_encoder *encoder) 856 { 857 struct nv50_msto *msto = nv50_msto(encoder); 858 struct nv50_mstc *mstc = msto->mstc; 859 struct nv50_mstm *mstm = mstc->mstm; 860 861 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 862 863 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 864 mstm->modified = true; 865 if (!--mstm->links) 866 mstm->disabled = true; 867 msto->disabled = true; 868 } 869 870 static const struct drm_encoder_helper_funcs 871 nv50_msto_help = { 872 .disable = nv50_msto_disable, 873 .enable = nv50_msto_enable, 874 .atomic_check = nv50_msto_atomic_check, 875 }; 876 877 static void 878 nv50_msto_destroy(struct drm_encoder *encoder) 879 { 880 struct nv50_msto *msto = nv50_msto(encoder); 881 drm_encoder_cleanup(&msto->encoder); 882 kfree(msto); 883 } 884 885 static const struct drm_encoder_funcs 886 nv50_msto = { 887 .destroy = nv50_msto_destroy, 888 }; 889 890 static int 891 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, 892 struct nv50_msto **pmsto) 893 { 894 struct nv50_msto *msto; 895 int ret; 896 897 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) 898 return -ENOMEM; 899 900 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 901 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); 902 if (ret) { 903 kfree(*pmsto); 904 *pmsto = NULL; 905 return ret; 906 } 907 908 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 909 msto->encoder.possible_crtcs = heads; 910 return 0; 911 } 912 913 static struct drm_encoder * 914 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 915 struct drm_connector_state *connector_state) 916 { 917 struct nv50_head *head = nv50_head(connector_state->crtc); 918 struct nv50_mstc *mstc = nv50_mstc(connector); 919 920 return &mstc->mstm->msto[head->base.index]->encoder; 921 } 922 923 static struct drm_encoder * 924 nv50_mstc_best_encoder(struct drm_connector *connector) 925 { 926 struct nv50_mstc *mstc = nv50_mstc(connector); 927 928 return &mstc->mstm->msto[0]->encoder; 929 } 930 931 static enum drm_mode_status 932 nv50_mstc_mode_valid(struct drm_connector *connector, 933 struct drm_display_mode *mode) 934 { 935 return MODE_OK; 936 } 937 938 static int 939 nv50_mstc_get_modes(struct drm_connector *connector) 940 { 941 struct nv50_mstc *mstc = nv50_mstc(connector); 942 int ret = 0; 943 944 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 945 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 946 if (mstc->edid) 947 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 948 949 if (!mstc->connector.display_info.bpc) 950 mstc->connector.display_info.bpc = 8; 951 952 if (mstc->native) 953 drm_mode_destroy(mstc->connector.dev, mstc->native); 954 mstc->native = nouveau_conn_native_mode(&mstc->connector); 955 return ret; 956 } 957 958 static int 959 nv50_mstc_atomic_check(struct drm_connector *connector, 960 struct drm_atomic_state *state) 961 { 962 struct nv50_mstc *mstc = nv50_mstc(connector); 963 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 964 struct drm_connector_state *new_conn_state = 965 drm_atomic_get_new_connector_state(state, connector); 966 struct drm_connector_state *old_conn_state = 967 drm_atomic_get_old_connector_state(state, connector); 968 struct drm_crtc_state *crtc_state; 969 struct drm_crtc *new_crtc = new_conn_state->crtc; 970 971 if (!old_conn_state->crtc) 972 return 0; 973 974 /* We only want to free VCPI if this state disables the CRTC on this 975 * connector 976 */ 977 if (new_crtc) { 978 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 979 980 if (!crtc_state || 981 !drm_atomic_crtc_needs_modeset(crtc_state) || 982 crtc_state->enable) 983 return 0; 984 } 985 986 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 987 } 988 989 static const struct drm_connector_helper_funcs 990 nv50_mstc_help = { 991 .get_modes = nv50_mstc_get_modes, 992 .mode_valid = nv50_mstc_mode_valid, 993 .best_encoder = nv50_mstc_best_encoder, 994 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 995 .atomic_check = nv50_mstc_atomic_check, 996 }; 997 998 static enum drm_connector_status 999 nv50_mstc_detect(struct drm_connector *connector, bool force) 1000 { 1001 struct nv50_mstc *mstc = nv50_mstc(connector); 1002 enum drm_connector_status conn_status; 1003 int ret; 1004 1005 if (drm_connector_is_unregistered(connector)) 1006 return connector_status_disconnected; 1007 1008 ret = pm_runtime_get_sync(connector->dev->dev); 1009 if (ret < 0 && ret != -EACCES) 1010 return connector_status_disconnected; 1011 1012 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr, 1013 mstc->port); 1014 1015 pm_runtime_mark_last_busy(connector->dev->dev); 1016 pm_runtime_put_autosuspend(connector->dev->dev); 1017 return conn_status; 1018 } 1019 1020 static void 1021 nv50_mstc_destroy(struct drm_connector *connector) 1022 { 1023 struct nv50_mstc *mstc = nv50_mstc(connector); 1024 1025 drm_connector_cleanup(&mstc->connector); 1026 drm_dp_mst_put_port_malloc(mstc->port); 1027 1028 kfree(mstc); 1029 } 1030 1031 static const struct drm_connector_funcs 1032 nv50_mstc = { 1033 .reset = nouveau_conn_reset, 1034 .detect = nv50_mstc_detect, 1035 .fill_modes = drm_helper_probe_single_connector_modes, 1036 .destroy = nv50_mstc_destroy, 1037 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1038 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1039 .atomic_set_property = nouveau_conn_atomic_set_property, 1040 .atomic_get_property = nouveau_conn_atomic_get_property, 1041 }; 1042 1043 static int 1044 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1045 const char *path, struct nv50_mstc **pmstc) 1046 { 1047 struct drm_device *dev = mstm->outp->base.base.dev; 1048 struct nv50_mstc *mstc; 1049 int ret, i; 1050 1051 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1052 return -ENOMEM; 1053 mstc->mstm = mstm; 1054 mstc->port = port; 1055 1056 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1057 DRM_MODE_CONNECTOR_DisplayPort); 1058 if (ret) { 1059 kfree(*pmstc); 1060 *pmstc = NULL; 1061 return ret; 1062 } 1063 1064 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1065 1066 mstc->connector.funcs->reset(&mstc->connector); 1067 nouveau_conn_attach_properties(&mstc->connector); 1068 1069 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) 1070 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); 1071 1072 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1073 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1074 drm_connector_set_path_property(&mstc->connector, path); 1075 drm_dp_mst_get_port_malloc(port); 1076 return 0; 1077 } 1078 1079 static void 1080 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1081 { 1082 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1083 struct drm_encoder *encoder; 1084 int ret; 1085 1086 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1087 ret = drm_dp_check_act_status(&mstm->mgr); 1088 1089 ret = drm_dp_update_payload_part2(&mstm->mgr); 1090 1091 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1092 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1093 struct nv50_msto *msto = nv50_msto(encoder); 1094 struct nv50_mstc *mstc = msto->mstc; 1095 if (mstc && mstc->mstm == mstm) 1096 nv50_msto_cleanup(msto); 1097 } 1098 } 1099 1100 mstm->modified = false; 1101 } 1102 1103 static void 1104 nv50_mstm_prepare(struct nv50_mstm *mstm) 1105 { 1106 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1107 struct drm_encoder *encoder; 1108 int ret; 1109 1110 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1111 ret = drm_dp_update_payload_part1(&mstm->mgr); 1112 1113 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1114 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1115 struct nv50_msto *msto = nv50_msto(encoder); 1116 struct nv50_mstc *mstc = msto->mstc; 1117 if (mstc && mstc->mstm == mstm) 1118 nv50_msto_prepare(msto); 1119 } 1120 } 1121 1122 if (mstm->disabled) { 1123 if (!mstm->links) 1124 nv50_outp_release(mstm->outp); 1125 mstm->disabled = false; 1126 } 1127 } 1128 1129 static void 1130 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 1131 struct drm_connector *connector) 1132 { 1133 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1134 struct nv50_mstc *mstc = nv50_mstc(connector); 1135 1136 drm_connector_unregister(&mstc->connector); 1137 1138 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 1139 1140 drm_connector_put(&mstc->connector); 1141 } 1142 1143 static void 1144 nv50_mstm_register_connector(struct drm_connector *connector) 1145 { 1146 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1147 1148 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 1149 1150 drm_connector_register(connector); 1151 } 1152 1153 static struct drm_connector * 1154 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1155 struct drm_dp_mst_port *port, const char *path) 1156 { 1157 struct nv50_mstm *mstm = nv50_mstm(mgr); 1158 struct nv50_mstc *mstc; 1159 int ret; 1160 1161 ret = nv50_mstc_new(mstm, port, path, &mstc); 1162 if (ret) 1163 return NULL; 1164 1165 return &mstc->connector; 1166 } 1167 1168 static const struct drm_dp_mst_topology_cbs 1169 nv50_mstm = { 1170 .add_connector = nv50_mstm_add_connector, 1171 .register_connector = nv50_mstm_register_connector, 1172 .destroy_connector = nv50_mstm_destroy_connector, 1173 }; 1174 1175 void 1176 nv50_mstm_service(struct nv50_mstm *mstm) 1177 { 1178 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1179 bool handled = true; 1180 int ret; 1181 u8 esi[8] = {}; 1182 1183 if (!aux) 1184 return; 1185 1186 while (handled) { 1187 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1188 if (ret != 8) { 1189 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1190 return; 1191 } 1192 1193 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1194 if (!handled) 1195 break; 1196 1197 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1198 } 1199 } 1200 1201 void 1202 nv50_mstm_remove(struct nv50_mstm *mstm) 1203 { 1204 if (mstm) 1205 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1206 } 1207 1208 static int 1209 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1210 { 1211 struct nouveau_encoder *outp = mstm->outp; 1212 struct { 1213 struct nv50_disp_mthd_v1 base; 1214 struct nv50_disp_sor_dp_mst_link_v0 mst; 1215 } args = { 1216 .base.version = 1, 1217 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1218 .base.hasht = outp->dcb->hasht, 1219 .base.hashm = outp->dcb->hashm, 1220 .mst.state = state, 1221 }; 1222 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1223 struct nvif_object *disp = &drm->display->disp.object; 1224 int ret; 1225 1226 if (dpcd >= 0x12) { 1227 /* Even if we're enabling MST, start with disabling the 1228 * branching unit to clear any sink-side MST topology state 1229 * that wasn't set by us 1230 */ 1231 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1232 if (ret < 0) 1233 return ret; 1234 1235 if (state) { 1236 /* Now, start initializing */ 1237 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1238 DP_MST_EN); 1239 if (ret < 0) 1240 return ret; 1241 } 1242 } 1243 1244 return nvif_mthd(disp, 0, &args, sizeof(args)); 1245 } 1246 1247 int 1248 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1249 { 1250 struct drm_dp_aux *aux; 1251 int ret; 1252 bool old_state, new_state; 1253 u8 mstm_ctrl; 1254 1255 if (!mstm) 1256 return 0; 1257 1258 mutex_lock(&mstm->mgr.lock); 1259 1260 old_state = mstm->mgr.mst_state; 1261 new_state = old_state; 1262 aux = mstm->mgr.aux; 1263 1264 if (old_state) { 1265 /* Just check that the MST hub is still as we expect it */ 1266 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1267 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1268 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1269 new_state = false; 1270 } 1271 } else if (dpcd[0] >= 0x12) { 1272 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1273 if (ret < 0) 1274 goto probe_error; 1275 1276 if (!(dpcd[1] & DP_MST_CAP)) 1277 dpcd[0] = 0x11; 1278 else 1279 new_state = allow; 1280 } 1281 1282 if (new_state == old_state) { 1283 mutex_unlock(&mstm->mgr.lock); 1284 return new_state; 1285 } 1286 1287 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1288 if (ret) 1289 goto probe_error; 1290 1291 mutex_unlock(&mstm->mgr.lock); 1292 1293 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1294 if (ret) 1295 return nv50_mstm_enable(mstm, dpcd[0], 0); 1296 1297 return new_state; 1298 1299 probe_error: 1300 mutex_unlock(&mstm->mgr.lock); 1301 return ret; 1302 } 1303 1304 static void 1305 nv50_mstm_fini(struct nv50_mstm *mstm) 1306 { 1307 if (mstm && mstm->mgr.mst_state) 1308 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1309 } 1310 1311 static void 1312 nv50_mstm_init(struct nv50_mstm *mstm) 1313 { 1314 int ret; 1315 1316 if (!mstm || !mstm->mgr.mst_state) 1317 return; 1318 1319 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr); 1320 if (ret == -1) { 1321 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1322 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1323 } 1324 } 1325 1326 static void 1327 nv50_mstm_del(struct nv50_mstm **pmstm) 1328 { 1329 struct nv50_mstm *mstm = *pmstm; 1330 if (mstm) { 1331 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1332 kfree(*pmstm); 1333 *pmstm = NULL; 1334 } 1335 } 1336 1337 static int 1338 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1339 int conn_base_id, struct nv50_mstm **pmstm) 1340 { 1341 const int max_payloads = hweight8(outp->dcb->heads); 1342 struct drm_device *dev = outp->base.base.dev; 1343 struct nv50_mstm *mstm; 1344 int ret, i; 1345 u8 dpcd; 1346 1347 /* This is a workaround for some monitors not functioning 1348 * correctly in MST mode on initial module load. I think 1349 * some bad interaction with the VBIOS may be responsible. 1350 * 1351 * A good ol' off and on again seems to work here ;) 1352 */ 1353 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1354 if (ret >= 0 && dpcd >= 0x12) 1355 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1356 1357 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1358 return -ENOMEM; 1359 mstm->outp = outp; 1360 mstm->mgr.cbs = &nv50_mstm; 1361 1362 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1363 max_payloads, conn_base_id); 1364 if (ret) 1365 return ret; 1366 1367 for (i = 0; i < max_payloads; i++) { 1368 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, 1369 i, &mstm->msto[i]); 1370 if (ret) 1371 return ret; 1372 } 1373 1374 return 0; 1375 } 1376 1377 /****************************************************************************** 1378 * SOR 1379 *****************************************************************************/ 1380 static void 1381 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1382 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1383 { 1384 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1385 struct nv50_core *core = disp->core; 1386 1387 if (!asyh) { 1388 nv_encoder->ctrl &= ~BIT(head); 1389 if (!(nv_encoder->ctrl & 0x0000000f)) 1390 nv_encoder->ctrl = 0; 1391 } else { 1392 nv_encoder->ctrl |= proto << 8; 1393 nv_encoder->ctrl |= BIT(head); 1394 asyh->or.depth = depth; 1395 } 1396 1397 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1398 } 1399 1400 static void 1401 nv50_sor_disable(struct drm_encoder *encoder) 1402 { 1403 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1404 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1405 1406 nv_encoder->crtc = NULL; 1407 1408 if (nv_crtc) { 1409 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1410 u8 pwr; 1411 1412 if (aux) { 1413 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1414 if (ret == 0) { 1415 pwr &= ~DP_SET_POWER_MASK; 1416 pwr |= DP_SET_POWER_D3; 1417 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1418 } 1419 } 1420 1421 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1422 nv50_audio_disable(encoder, nv_crtc); 1423 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1424 nv50_outp_release(nv_encoder); 1425 } 1426 } 1427 1428 static void 1429 nv50_sor_enable(struct drm_encoder *encoder) 1430 { 1431 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1432 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1433 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1434 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1435 struct { 1436 struct nv50_disp_mthd_v1 base; 1437 struct nv50_disp_sor_lvds_script_v0 lvds; 1438 } lvds = { 1439 .base.version = 1, 1440 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1441 .base.hasht = nv_encoder->dcb->hasht, 1442 .base.hashm = nv_encoder->dcb->hashm, 1443 }; 1444 struct nv50_disp *disp = nv50_disp(encoder->dev); 1445 struct drm_device *dev = encoder->dev; 1446 struct nouveau_drm *drm = nouveau_drm(dev); 1447 struct nouveau_connector *nv_connector; 1448 struct nvbios *bios = &drm->vbios; 1449 u8 proto = 0xf; 1450 u8 depth = 0x0; 1451 1452 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1453 nv_encoder->crtc = encoder->crtc; 1454 nv50_outp_acquire(nv_encoder); 1455 1456 switch (nv_encoder->dcb->type) { 1457 case DCB_OUTPUT_TMDS: 1458 if (nv_encoder->link & 1) { 1459 proto = 0x1; 1460 /* Only enable dual-link if: 1461 * - Need to (i.e. rate > 165MHz) 1462 * - DCB says we can 1463 * - Not an HDMI monitor, since there's no dual-link 1464 * on HDMI. 1465 */ 1466 if (mode->clock >= 165000 && 1467 nv_encoder->dcb->duallink_possible && 1468 !drm_detect_hdmi_monitor(nv_connector->edid)) 1469 proto |= 0x4; 1470 } else { 1471 proto = 0x2; 1472 } 1473 1474 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1475 break; 1476 case DCB_OUTPUT_LVDS: 1477 proto = 0x0; 1478 1479 if (bios->fp_no_ddc) { 1480 if (bios->fp.dual_link) 1481 lvds.lvds.script |= 0x0100; 1482 if (bios->fp.if_is_24bit) 1483 lvds.lvds.script |= 0x0200; 1484 } else { 1485 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1486 if (((u8 *)nv_connector->edid)[121] == 2) 1487 lvds.lvds.script |= 0x0100; 1488 } else 1489 if (mode->clock >= bios->fp.duallink_transition_clk) { 1490 lvds.lvds.script |= 0x0100; 1491 } 1492 1493 if (lvds.lvds.script & 0x0100) { 1494 if (bios->fp.strapless_is_24bit & 2) 1495 lvds.lvds.script |= 0x0200; 1496 } else { 1497 if (bios->fp.strapless_is_24bit & 1) 1498 lvds.lvds.script |= 0x0200; 1499 } 1500 1501 if (nv_connector->base.display_info.bpc == 8) 1502 lvds.lvds.script |= 0x0200; 1503 } 1504 1505 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1506 break; 1507 case DCB_OUTPUT_DP: 1508 if (nv_connector->base.display_info.bpc == 6) 1509 depth = 0x2; 1510 else 1511 if (nv_connector->base.display_info.bpc == 8) 1512 depth = 0x5; 1513 else 1514 depth = 0x6; 1515 1516 if (nv_encoder->link & 1) 1517 proto = 0x8; 1518 else 1519 proto = 0x9; 1520 1521 nv50_audio_enable(encoder, mode); 1522 break; 1523 default: 1524 BUG(); 1525 break; 1526 } 1527 1528 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1529 } 1530 1531 static const struct drm_encoder_helper_funcs 1532 nv50_sor_help = { 1533 .atomic_check = nv50_outp_atomic_check, 1534 .enable = nv50_sor_enable, 1535 .disable = nv50_sor_disable, 1536 }; 1537 1538 static void 1539 nv50_sor_destroy(struct drm_encoder *encoder) 1540 { 1541 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1542 nv50_mstm_del(&nv_encoder->dp.mstm); 1543 drm_encoder_cleanup(encoder); 1544 kfree(encoder); 1545 } 1546 1547 static const struct drm_encoder_funcs 1548 nv50_sor_func = { 1549 .destroy = nv50_sor_destroy, 1550 }; 1551 1552 static int 1553 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1554 { 1555 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1556 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1557 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1558 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1559 struct nouveau_encoder *nv_encoder; 1560 struct drm_encoder *encoder; 1561 u8 ver, hdr, cnt, len; 1562 u32 data; 1563 int type, ret; 1564 1565 switch (dcbe->type) { 1566 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1567 case DCB_OUTPUT_TMDS: 1568 case DCB_OUTPUT_DP: 1569 default: 1570 type = DRM_MODE_ENCODER_TMDS; 1571 break; 1572 } 1573 1574 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1575 if (!nv_encoder) 1576 return -ENOMEM; 1577 nv_encoder->dcb = dcbe; 1578 nv_encoder->update = nv50_sor_update; 1579 1580 encoder = to_drm_encoder(nv_encoder); 1581 encoder->possible_crtcs = dcbe->heads; 1582 encoder->possible_clones = 0; 1583 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1584 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1585 drm_encoder_helper_add(encoder, &nv50_sor_help); 1586 1587 drm_connector_attach_encoder(connector, encoder); 1588 1589 if (dcbe->type == DCB_OUTPUT_DP) { 1590 struct nv50_disp *disp = nv50_disp(encoder->dev); 1591 struct nvkm_i2c_aux *aux = 1592 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1593 if (aux) { 1594 if (disp->disp->object.oclass < GF110_DISP) { 1595 /* HW has no support for address-only 1596 * transactions, so we're required to 1597 * use custom I2C-over-AUX code. 1598 */ 1599 nv_encoder->i2c = &aux->i2c; 1600 } else { 1601 nv_encoder->i2c = &nv_connector->aux.ddc; 1602 } 1603 nv_encoder->aux = aux; 1604 } 1605 1606 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && 1607 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) { 1608 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, 1609 nv_connector->base.base.id, 1610 &nv_encoder->dp.mstm); 1611 if (ret) 1612 return ret; 1613 } 1614 } else { 1615 struct nvkm_i2c_bus *bus = 1616 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1617 if (bus) 1618 nv_encoder->i2c = &bus->i2c; 1619 } 1620 1621 return 0; 1622 } 1623 1624 /****************************************************************************** 1625 * PIOR 1626 *****************************************************************************/ 1627 static int 1628 nv50_pior_atomic_check(struct drm_encoder *encoder, 1629 struct drm_crtc_state *crtc_state, 1630 struct drm_connector_state *conn_state) 1631 { 1632 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1633 if (ret) 1634 return ret; 1635 crtc_state->adjusted_mode.clock *= 2; 1636 return 0; 1637 } 1638 1639 static void 1640 nv50_pior_disable(struct drm_encoder *encoder) 1641 { 1642 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1643 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1644 if (nv_encoder->crtc) 1645 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1646 nv_encoder->crtc = NULL; 1647 nv50_outp_release(nv_encoder); 1648 } 1649 1650 static void 1651 nv50_pior_enable(struct drm_encoder *encoder) 1652 { 1653 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1654 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1655 struct nouveau_connector *nv_connector; 1656 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1657 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1658 u8 owner = 1 << nv_crtc->index; 1659 u8 proto; 1660 1661 nv50_outp_acquire(nv_encoder); 1662 1663 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1664 switch (nv_connector->base.display_info.bpc) { 1665 case 10: asyh->or.depth = 0x6; break; 1666 case 8: asyh->or.depth = 0x5; break; 1667 case 6: asyh->or.depth = 0x2; break; 1668 default: asyh->or.depth = 0x0; break; 1669 } 1670 1671 switch (nv_encoder->dcb->type) { 1672 case DCB_OUTPUT_TMDS: 1673 case DCB_OUTPUT_DP: 1674 proto = 0x0; 1675 break; 1676 default: 1677 BUG(); 1678 break; 1679 } 1680 1681 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1682 nv_encoder->crtc = encoder->crtc; 1683 } 1684 1685 static const struct drm_encoder_helper_funcs 1686 nv50_pior_help = { 1687 .atomic_check = nv50_pior_atomic_check, 1688 .enable = nv50_pior_enable, 1689 .disable = nv50_pior_disable, 1690 }; 1691 1692 static void 1693 nv50_pior_destroy(struct drm_encoder *encoder) 1694 { 1695 drm_encoder_cleanup(encoder); 1696 kfree(encoder); 1697 } 1698 1699 static const struct drm_encoder_funcs 1700 nv50_pior_func = { 1701 .destroy = nv50_pior_destroy, 1702 }; 1703 1704 static int 1705 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1706 { 1707 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1708 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1709 struct nvkm_i2c_bus *bus = NULL; 1710 struct nvkm_i2c_aux *aux = NULL; 1711 struct i2c_adapter *ddc; 1712 struct nouveau_encoder *nv_encoder; 1713 struct drm_encoder *encoder; 1714 int type; 1715 1716 switch (dcbe->type) { 1717 case DCB_OUTPUT_TMDS: 1718 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1719 ddc = bus ? &bus->i2c : NULL; 1720 type = DRM_MODE_ENCODER_TMDS; 1721 break; 1722 case DCB_OUTPUT_DP: 1723 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1724 ddc = aux ? &aux->i2c : NULL; 1725 type = DRM_MODE_ENCODER_TMDS; 1726 break; 1727 default: 1728 return -ENODEV; 1729 } 1730 1731 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1732 if (!nv_encoder) 1733 return -ENOMEM; 1734 nv_encoder->dcb = dcbe; 1735 nv_encoder->i2c = ddc; 1736 nv_encoder->aux = aux; 1737 1738 encoder = to_drm_encoder(nv_encoder); 1739 encoder->possible_crtcs = dcbe->heads; 1740 encoder->possible_clones = 0; 1741 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1742 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1743 drm_encoder_helper_add(encoder, &nv50_pior_help); 1744 1745 drm_connector_attach_encoder(connector, encoder); 1746 return 0; 1747 } 1748 1749 /****************************************************************************** 1750 * Atomic 1751 *****************************************************************************/ 1752 1753 static void 1754 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1755 { 1756 struct nouveau_drm *drm = nouveau_drm(state->dev); 1757 struct nv50_disp *disp = nv50_disp(drm->dev); 1758 struct nv50_core *core = disp->core; 1759 struct nv50_mstm *mstm; 1760 struct drm_encoder *encoder; 1761 1762 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1763 1764 drm_for_each_encoder(encoder, drm->dev) { 1765 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1766 mstm = nouveau_encoder(encoder)->dp.mstm; 1767 if (mstm && mstm->modified) 1768 nv50_mstm_prepare(mstm); 1769 } 1770 } 1771 1772 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1773 core->func->update(core, interlock, true); 1774 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1775 disp->core->chan.base.device)) 1776 NV_ERROR(drm, "core notifier timeout\n"); 1777 1778 drm_for_each_encoder(encoder, drm->dev) { 1779 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1780 mstm = nouveau_encoder(encoder)->dp.mstm; 1781 if (mstm && mstm->modified) 1782 nv50_mstm_cleanup(mstm); 1783 } 1784 } 1785 } 1786 1787 static void 1788 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1789 { 1790 struct drm_plane_state *new_plane_state; 1791 struct drm_plane *plane; 1792 int i; 1793 1794 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1795 struct nv50_wndw *wndw = nv50_wndw(plane); 1796 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1797 if (wndw->func->update) 1798 wndw->func->update(wndw, interlock); 1799 } 1800 } 1801 } 1802 1803 static void 1804 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1805 { 1806 struct drm_device *dev = state->dev; 1807 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1808 struct drm_crtc *crtc; 1809 struct drm_plane_state *new_plane_state; 1810 struct drm_plane *plane; 1811 struct nouveau_drm *drm = nouveau_drm(dev); 1812 struct nv50_disp *disp = nv50_disp(dev); 1813 struct nv50_atom *atom = nv50_atom(state); 1814 struct nv50_outp_atom *outp, *outt; 1815 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1816 int i; 1817 1818 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1819 drm_atomic_helper_wait_for_fences(dev, state, false); 1820 drm_atomic_helper_wait_for_dependencies(state); 1821 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1822 1823 if (atom->lock_core) 1824 mutex_lock(&disp->mutex); 1825 1826 /* Disable head(s). */ 1827 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1828 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1829 struct nv50_head *head = nv50_head(crtc); 1830 1831 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1832 asyh->clr.mask, asyh->set.mask); 1833 if (old_crtc_state->active && !new_crtc_state->active) 1834 drm_crtc_vblank_off(crtc); 1835 1836 if (asyh->clr.mask) { 1837 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1838 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1839 } 1840 } 1841 1842 /* Disable plane(s). */ 1843 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1844 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1845 struct nv50_wndw *wndw = nv50_wndw(plane); 1846 1847 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1848 asyw->clr.mask, asyw->set.mask); 1849 if (!asyw->clr.mask) 1850 continue; 1851 1852 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1853 } 1854 1855 /* Disable output path(s). */ 1856 list_for_each_entry(outp, &atom->outp, head) { 1857 const struct drm_encoder_helper_funcs *help; 1858 struct drm_encoder *encoder; 1859 1860 encoder = outp->encoder; 1861 help = encoder->helper_private; 1862 1863 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1864 outp->clr.mask, outp->set.mask); 1865 1866 if (outp->clr.mask) { 1867 help->disable(encoder); 1868 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1869 if (outp->flush_disable) { 1870 nv50_disp_atomic_commit_wndw(state, interlock); 1871 nv50_disp_atomic_commit_core(state, interlock); 1872 memset(interlock, 0x00, sizeof(interlock)); 1873 } 1874 } 1875 } 1876 1877 /* Flush disable. */ 1878 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1879 if (atom->flush_disable) { 1880 nv50_disp_atomic_commit_wndw(state, interlock); 1881 nv50_disp_atomic_commit_core(state, interlock); 1882 memset(interlock, 0x00, sizeof(interlock)); 1883 } 1884 } 1885 1886 /* Update output path(s). */ 1887 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1888 const struct drm_encoder_helper_funcs *help; 1889 struct drm_encoder *encoder; 1890 1891 encoder = outp->encoder; 1892 help = encoder->helper_private; 1893 1894 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 1895 outp->set.mask, outp->clr.mask); 1896 1897 if (outp->set.mask) { 1898 help->enable(encoder); 1899 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1900 } 1901 1902 list_del(&outp->head); 1903 kfree(outp); 1904 } 1905 1906 /* Update head(s). */ 1907 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1908 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1909 struct nv50_head *head = nv50_head(crtc); 1910 1911 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 1912 asyh->set.mask, asyh->clr.mask); 1913 1914 if (asyh->set.mask) { 1915 nv50_head_flush_set(head, asyh); 1916 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1917 } 1918 1919 if (new_crtc_state->active) { 1920 if (!old_crtc_state->active) 1921 drm_crtc_vblank_on(crtc); 1922 if (new_crtc_state->event) 1923 drm_crtc_vblank_get(crtc); 1924 } 1925 } 1926 1927 /* Update plane(s). */ 1928 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1929 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1930 struct nv50_wndw *wndw = nv50_wndw(plane); 1931 1932 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 1933 asyw->set.mask, asyw->clr.mask); 1934 if ( !asyw->set.mask && 1935 (!asyw->clr.mask || atom->flush_disable)) 1936 continue; 1937 1938 nv50_wndw_flush_set(wndw, interlock, asyw); 1939 } 1940 1941 /* Flush update. */ 1942 nv50_disp_atomic_commit_wndw(state, interlock); 1943 1944 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1945 if (interlock[NV50_DISP_INTERLOCK_BASE] || 1946 interlock[NV50_DISP_INTERLOCK_OVLY] || 1947 interlock[NV50_DISP_INTERLOCK_WNDW] || 1948 !atom->state.legacy_cursor_update) 1949 nv50_disp_atomic_commit_core(state, interlock); 1950 else 1951 disp->core->func->update(disp->core, interlock, false); 1952 } 1953 1954 if (atom->lock_core) 1955 mutex_unlock(&disp->mutex); 1956 1957 /* Wait for HW to signal completion. */ 1958 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1959 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1960 struct nv50_wndw *wndw = nv50_wndw(plane); 1961 int ret = nv50_wndw_wait_armed(wndw, asyw); 1962 if (ret) 1963 NV_ERROR(drm, "%s: timeout\n", plane->name); 1964 } 1965 1966 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 1967 if (new_crtc_state->event) { 1968 unsigned long flags; 1969 /* Get correct count/ts if racing with vblank irq */ 1970 if (new_crtc_state->active) 1971 drm_crtc_accurate_vblank_count(crtc); 1972 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1973 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 1974 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1975 1976 new_crtc_state->event = NULL; 1977 if (new_crtc_state->active) 1978 drm_crtc_vblank_put(crtc); 1979 } 1980 } 1981 1982 drm_atomic_helper_commit_hw_done(state); 1983 drm_atomic_helper_cleanup_planes(dev, state); 1984 drm_atomic_helper_commit_cleanup_done(state); 1985 drm_atomic_state_put(state); 1986 } 1987 1988 static void 1989 nv50_disp_atomic_commit_work(struct work_struct *work) 1990 { 1991 struct drm_atomic_state *state = 1992 container_of(work, typeof(*state), commit_work); 1993 nv50_disp_atomic_commit_tail(state); 1994 } 1995 1996 static int 1997 nv50_disp_atomic_commit(struct drm_device *dev, 1998 struct drm_atomic_state *state, bool nonblock) 1999 { 2000 struct nouveau_drm *drm = nouveau_drm(dev); 2001 struct drm_plane_state *new_plane_state; 2002 struct drm_plane *plane; 2003 struct drm_crtc *crtc; 2004 bool active = false; 2005 int ret, i; 2006 2007 ret = pm_runtime_get_sync(dev->dev); 2008 if (ret < 0 && ret != -EACCES) 2009 return ret; 2010 2011 ret = drm_atomic_helper_setup_commit(state, nonblock); 2012 if (ret) 2013 goto done; 2014 2015 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2016 2017 ret = drm_atomic_helper_prepare_planes(dev, state); 2018 if (ret) 2019 goto done; 2020 2021 if (!nonblock) { 2022 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2023 if (ret) 2024 goto err_cleanup; 2025 } 2026 2027 ret = drm_atomic_helper_swap_state(state, true); 2028 if (ret) 2029 goto err_cleanup; 2030 2031 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2032 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2033 struct nv50_wndw *wndw = nv50_wndw(plane); 2034 2035 if (asyw->set.image) 2036 nv50_wndw_ntfy_enable(wndw, asyw); 2037 } 2038 2039 drm_atomic_state_get(state); 2040 2041 if (nonblock) 2042 queue_work(system_unbound_wq, &state->commit_work); 2043 else 2044 nv50_disp_atomic_commit_tail(state); 2045 2046 drm_for_each_crtc(crtc, dev) { 2047 if (crtc->state->active) { 2048 if (!drm->have_disp_power_ref) { 2049 drm->have_disp_power_ref = true; 2050 return 0; 2051 } 2052 active = true; 2053 break; 2054 } 2055 } 2056 2057 if (!active && drm->have_disp_power_ref) { 2058 pm_runtime_put_autosuspend(dev->dev); 2059 drm->have_disp_power_ref = false; 2060 } 2061 2062 err_cleanup: 2063 if (ret) 2064 drm_atomic_helper_cleanup_planes(dev, state); 2065 done: 2066 pm_runtime_put_autosuspend(dev->dev); 2067 return ret; 2068 } 2069 2070 static struct nv50_outp_atom * 2071 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2072 { 2073 struct nv50_outp_atom *outp; 2074 2075 list_for_each_entry(outp, &atom->outp, head) { 2076 if (outp->encoder == encoder) 2077 return outp; 2078 } 2079 2080 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2081 if (!outp) 2082 return ERR_PTR(-ENOMEM); 2083 2084 list_add(&outp->head, &atom->outp); 2085 outp->encoder = encoder; 2086 return outp; 2087 } 2088 2089 static int 2090 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2091 struct drm_connector_state *old_connector_state) 2092 { 2093 struct drm_encoder *encoder = old_connector_state->best_encoder; 2094 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2095 struct drm_crtc *crtc; 2096 struct nv50_outp_atom *outp; 2097 2098 if (!(crtc = old_connector_state->crtc)) 2099 return 0; 2100 2101 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2102 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2103 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2104 outp = nv50_disp_outp_atomic_add(atom, encoder); 2105 if (IS_ERR(outp)) 2106 return PTR_ERR(outp); 2107 2108 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2109 outp->flush_disable = true; 2110 atom->flush_disable = true; 2111 } 2112 outp->clr.ctrl = true; 2113 atom->lock_core = true; 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int 2120 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2121 struct drm_connector_state *connector_state) 2122 { 2123 struct drm_encoder *encoder = connector_state->best_encoder; 2124 struct drm_crtc_state *new_crtc_state; 2125 struct drm_crtc *crtc; 2126 struct nv50_outp_atom *outp; 2127 2128 if (!(crtc = connector_state->crtc)) 2129 return 0; 2130 2131 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2132 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2133 outp = nv50_disp_outp_atomic_add(atom, encoder); 2134 if (IS_ERR(outp)) 2135 return PTR_ERR(outp); 2136 2137 outp->set.ctrl = true; 2138 atom->lock_core = true; 2139 } 2140 2141 return 0; 2142 } 2143 2144 static int 2145 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2146 { 2147 struct nv50_atom *atom = nv50_atom(state); 2148 struct drm_connector_state *old_connector_state, *new_connector_state; 2149 struct drm_connector *connector; 2150 struct drm_crtc_state *new_crtc_state; 2151 struct drm_crtc *crtc; 2152 int ret, i; 2153 2154 /* We need to handle colour management on a per-plane basis. */ 2155 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2156 if (new_crtc_state->color_mgmt_changed) { 2157 ret = drm_atomic_add_affected_planes(state, crtc); 2158 if (ret) 2159 return ret; 2160 } 2161 } 2162 2163 ret = drm_atomic_helper_check(dev, state); 2164 if (ret) 2165 return ret; 2166 2167 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2168 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2169 if (ret) 2170 return ret; 2171 2172 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2173 if (ret) 2174 return ret; 2175 } 2176 2177 ret = drm_dp_mst_atomic_check(state); 2178 if (ret) 2179 return ret; 2180 2181 return 0; 2182 } 2183 2184 static void 2185 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2186 { 2187 struct nv50_atom *atom = nv50_atom(state); 2188 struct nv50_outp_atom *outp, *outt; 2189 2190 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2191 list_del(&outp->head); 2192 kfree(outp); 2193 } 2194 2195 drm_atomic_state_default_clear(state); 2196 } 2197 2198 static void 2199 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2200 { 2201 struct nv50_atom *atom = nv50_atom(state); 2202 drm_atomic_state_default_release(&atom->state); 2203 kfree(atom); 2204 } 2205 2206 static struct drm_atomic_state * 2207 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2208 { 2209 struct nv50_atom *atom; 2210 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2211 drm_atomic_state_init(dev, &atom->state) < 0) { 2212 kfree(atom); 2213 return NULL; 2214 } 2215 INIT_LIST_HEAD(&atom->outp); 2216 return &atom->state; 2217 } 2218 2219 static const struct drm_mode_config_funcs 2220 nv50_disp_func = { 2221 .fb_create = nouveau_user_framebuffer_create, 2222 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2223 .atomic_check = nv50_disp_atomic_check, 2224 .atomic_commit = nv50_disp_atomic_commit, 2225 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2226 .atomic_state_clear = nv50_disp_atomic_state_clear, 2227 .atomic_state_free = nv50_disp_atomic_state_free, 2228 }; 2229 2230 /****************************************************************************** 2231 * Init 2232 *****************************************************************************/ 2233 2234 static void 2235 nv50_display_fini(struct drm_device *dev, bool suspend) 2236 { 2237 struct nouveau_encoder *nv_encoder; 2238 struct drm_encoder *encoder; 2239 struct drm_plane *plane; 2240 2241 drm_for_each_plane(plane, dev) { 2242 struct nv50_wndw *wndw = nv50_wndw(plane); 2243 if (plane->funcs != &nv50_wndw) 2244 continue; 2245 nv50_wndw_fini(wndw); 2246 } 2247 2248 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2249 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2250 nv_encoder = nouveau_encoder(encoder); 2251 nv50_mstm_fini(nv_encoder->dp.mstm); 2252 } 2253 } 2254 } 2255 2256 static int 2257 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2258 { 2259 struct nv50_core *core = nv50_disp(dev)->core; 2260 struct drm_encoder *encoder; 2261 struct drm_plane *plane; 2262 2263 core->func->init(core); 2264 2265 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2266 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2267 struct nouveau_encoder *nv_encoder = 2268 nouveau_encoder(encoder); 2269 nv50_mstm_init(nv_encoder->dp.mstm); 2270 } 2271 } 2272 2273 drm_for_each_plane(plane, dev) { 2274 struct nv50_wndw *wndw = nv50_wndw(plane); 2275 if (plane->funcs != &nv50_wndw) 2276 continue; 2277 nv50_wndw_init(wndw); 2278 } 2279 2280 return 0; 2281 } 2282 2283 static void 2284 nv50_display_destroy(struct drm_device *dev) 2285 { 2286 struct nv50_disp *disp = nv50_disp(dev); 2287 2288 nv50_core_del(&disp->core); 2289 2290 nouveau_bo_unmap(disp->sync); 2291 if (disp->sync) 2292 nouveau_bo_unpin(disp->sync); 2293 nouveau_bo_ref(NULL, &disp->sync); 2294 2295 nouveau_display(dev)->priv = NULL; 2296 kfree(disp); 2297 } 2298 2299 int 2300 nv50_display_create(struct drm_device *dev) 2301 { 2302 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2303 struct nouveau_drm *drm = nouveau_drm(dev); 2304 struct dcb_table *dcb = &drm->vbios.dcb; 2305 struct drm_connector *connector, *tmp; 2306 struct nv50_disp *disp; 2307 struct dcb_output *dcbe; 2308 int crtcs, ret, i; 2309 2310 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2311 if (!disp) 2312 return -ENOMEM; 2313 2314 mutex_init(&disp->mutex); 2315 2316 nouveau_display(dev)->priv = disp; 2317 nouveau_display(dev)->dtor = nv50_display_destroy; 2318 nouveau_display(dev)->init = nv50_display_init; 2319 nouveau_display(dev)->fini = nv50_display_fini; 2320 disp->disp = &nouveau_display(dev)->disp; 2321 dev->mode_config.funcs = &nv50_disp_func; 2322 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2323 2324 /* small shared memory area we use for notifiers and semaphores */ 2325 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2326 0, 0x0000, NULL, NULL, &disp->sync); 2327 if (!ret) { 2328 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2329 if (!ret) { 2330 ret = nouveau_bo_map(disp->sync); 2331 if (ret) 2332 nouveau_bo_unpin(disp->sync); 2333 } 2334 if (ret) 2335 nouveau_bo_ref(NULL, &disp->sync); 2336 } 2337 2338 if (ret) 2339 goto out; 2340 2341 /* allocate master evo channel */ 2342 ret = nv50_core_new(drm, &disp->core); 2343 if (ret) 2344 goto out; 2345 2346 /* create crtc objects to represent the hw heads */ 2347 if (disp->disp->object.oclass >= GV100_DISP) 2348 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2349 else 2350 if (disp->disp->object.oclass >= GF110_DISP) 2351 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2352 else 2353 crtcs = 0x3; 2354 2355 for (i = 0; i < fls(crtcs); i++) { 2356 if (!(crtcs & (1 << i))) 2357 continue; 2358 ret = nv50_head_create(dev, i); 2359 if (ret) 2360 goto out; 2361 } 2362 2363 /* create encoder/connector objects based on VBIOS DCB table */ 2364 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2365 connector = nouveau_connector_create(dev, dcbe); 2366 if (IS_ERR(connector)) 2367 continue; 2368 2369 if (dcbe->location == DCB_LOC_ON_CHIP) { 2370 switch (dcbe->type) { 2371 case DCB_OUTPUT_TMDS: 2372 case DCB_OUTPUT_LVDS: 2373 case DCB_OUTPUT_DP: 2374 ret = nv50_sor_create(connector, dcbe); 2375 break; 2376 case DCB_OUTPUT_ANALOG: 2377 ret = nv50_dac_create(connector, dcbe); 2378 break; 2379 default: 2380 ret = -ENODEV; 2381 break; 2382 } 2383 } else { 2384 ret = nv50_pior_create(connector, dcbe); 2385 } 2386 2387 if (ret) { 2388 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2389 dcbe->location, dcbe->type, 2390 ffs(dcbe->or) - 1, ret); 2391 ret = 0; 2392 } 2393 } 2394 2395 /* cull any connectors we created that don't have an encoder */ 2396 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2397 if (connector->encoder_ids[0]) 2398 continue; 2399 2400 NV_WARN(drm, "%s has no encoders, removing\n", 2401 connector->name); 2402 connector->funcs->destroy(connector); 2403 } 2404 2405 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2406 dev->vblank_disable_immediate = true; 2407 2408 out: 2409 if (ret) 2410 nv50_display_destroy(dev); 2411 return ret; 2412 } 2413