1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fb_helper.h> 37 #include <drm/drm_plane_helper.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_scdc_helper.h> 40 #include <drm/drm_edid.h> 41 42 #include <nvif/class.h> 43 #include <nvif/cl0002.h> 44 #include <nvif/cl5070.h> 45 #include <nvif/cl507d.h> 46 #include <nvif/event.h> 47 48 #include "nouveau_drv.h" 49 #include "nouveau_dma.h" 50 #include "nouveau_gem.h" 51 #include "nouveau_connector.h" 52 #include "nouveau_encoder.h" 53 #include "nouveau_fence.h" 54 #include "nouveau_fbcon.h" 55 56 #include <subdev/bios/dp.h> 57 58 /****************************************************************************** 59 * Atomic state 60 *****************************************************************************/ 61 62 struct nv50_outp_atom { 63 struct list_head head; 64 65 struct drm_encoder *encoder; 66 bool flush_disable; 67 68 union nv50_outp_atom_mask { 69 struct { 70 bool ctrl:1; 71 }; 72 u8 mask; 73 } set, clr; 74 }; 75 76 /****************************************************************************** 77 * EVO channel 78 *****************************************************************************/ 79 80 static int 81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 82 const s32 *oclass, u8 head, void *data, u32 size, 83 struct nv50_chan *chan) 84 { 85 struct nvif_sclass *sclass; 86 int ret, i, n; 87 88 chan->device = device; 89 90 ret = n = nvif_object_sclass_get(disp, &sclass); 91 if (ret < 0) 92 return ret; 93 94 while (oclass[0]) { 95 for (i = 0; i < n; i++) { 96 if (sclass[i].oclass == oclass[0]) { 97 ret = nvif_object_init(disp, 0, oclass[0], 98 data, size, &chan->user); 99 if (ret == 0) 100 nvif_object_map(&chan->user, NULL, 0); 101 nvif_object_sclass_put(&sclass); 102 return ret; 103 } 104 } 105 oclass++; 106 } 107 108 nvif_object_sclass_put(&sclass); 109 return -ENOSYS; 110 } 111 112 static void 113 nv50_chan_destroy(struct nv50_chan *chan) 114 { 115 nvif_object_fini(&chan->user); 116 } 117 118 /****************************************************************************** 119 * DMA EVO channel 120 *****************************************************************************/ 121 122 void 123 nv50_dmac_destroy(struct nv50_dmac *dmac) 124 { 125 nvif_object_fini(&dmac->vram); 126 nvif_object_fini(&dmac->sync); 127 128 nv50_chan_destroy(&dmac->base); 129 130 nvif_mem_fini(&dmac->push); 131 } 132 133 int 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 136 struct nv50_dmac *dmac) 137 { 138 struct nouveau_cli *cli = (void *)device->object.client; 139 struct nv50_disp_core_channel_dma_v0 *args = data; 140 u8 type = NVIF_MEM_COHERENT; 141 int ret; 142 143 mutex_init(&dmac->lock); 144 145 /* Pascal added support for 47-bit physical addresses, but some 146 * parts of EVO still only accept 40-bit PAs. 147 * 148 * To avoid issues on systems with large amounts of RAM, and on 149 * systems where an IOMMU maps pages at a high address, we need 150 * to allocate push buffers in VRAM instead. 151 * 152 * This appears to match NVIDIA's behaviour on Pascal. 153 */ 154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 155 type |= NVIF_MEM_VRAM; 156 157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 158 if (ret) 159 return ret; 160 161 dmac->ptr = dmac->push.object.map.ptr; 162 163 args->pushbuf = nvif_handle(&dmac->push.object); 164 165 ret = nv50_chan_create(device, disp, oclass, head, data, size, 166 &dmac->base); 167 if (ret) 168 return ret; 169 170 if (!syncbuf) 171 return 0; 172 173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 174 &(struct nv_dma_v0) { 175 .target = NV_DMA_V0_TARGET_VRAM, 176 .access = NV_DMA_V0_ACCESS_RDWR, 177 .start = syncbuf + 0x0000, 178 .limit = syncbuf + 0x0fff, 179 }, sizeof(struct nv_dma_v0), 180 &dmac->sync); 181 if (ret) 182 return ret; 183 184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 185 &(struct nv_dma_v0) { 186 .target = NV_DMA_V0_TARGET_VRAM, 187 .access = NV_DMA_V0_ACCESS_RDWR, 188 .start = 0, 189 .limit = device->info.ram_user - 1, 190 }, sizeof(struct nv_dma_v0), 191 &dmac->vram); 192 if (ret) 193 return ret; 194 195 return ret; 196 } 197 198 /****************************************************************************** 199 * EVO channel helpers 200 *****************************************************************************/ 201 static void 202 evo_flush(struct nv50_dmac *dmac) 203 { 204 /* Push buffer fetches are not coherent with BAR1, we need to ensure 205 * writes have been flushed right through to VRAM before writing PUT. 206 */ 207 if (dmac->push.type & NVIF_MEM_VRAM) { 208 struct nvif_device *device = dmac->base.device; 209 nvif_wr32(&device->object, 0x070000, 0x00000001); 210 nvif_msec(device, 2000, 211 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 212 break; 213 ); 214 } 215 } 216 217 u32 * 218 evo_wait(struct nv50_dmac *evoc, int nr) 219 { 220 struct nv50_dmac *dmac = evoc; 221 struct nvif_device *device = dmac->base.device; 222 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 223 224 mutex_lock(&dmac->lock); 225 if (put + nr >= (PAGE_SIZE / 4) - 8) { 226 dmac->ptr[put] = 0x20000000; 227 evo_flush(dmac); 228 229 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 230 if (nvif_msec(device, 2000, 231 if (!nvif_rd32(&dmac->base.user, 0x0004)) 232 break; 233 ) < 0) { 234 mutex_unlock(&dmac->lock); 235 pr_err("nouveau: evo channel stalled\n"); 236 return NULL; 237 } 238 239 put = 0; 240 } 241 242 return dmac->ptr + put; 243 } 244 245 void 246 evo_kick(u32 *push, struct nv50_dmac *evoc) 247 { 248 struct nv50_dmac *dmac = evoc; 249 250 evo_flush(dmac); 251 252 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 253 mutex_unlock(&dmac->lock); 254 } 255 256 /****************************************************************************** 257 * Output path helpers 258 *****************************************************************************/ 259 static void 260 nv50_outp_release(struct nouveau_encoder *nv_encoder) 261 { 262 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 263 struct { 264 struct nv50_disp_mthd_v1 base; 265 } args = { 266 .base.version = 1, 267 .base.method = NV50_DISP_MTHD_V1_RELEASE, 268 .base.hasht = nv_encoder->dcb->hasht, 269 .base.hashm = nv_encoder->dcb->hashm, 270 }; 271 272 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 273 nv_encoder->or = -1; 274 nv_encoder->link = 0; 275 } 276 277 static int 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder) 279 { 280 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 281 struct nv50_disp *disp = nv50_disp(drm->dev); 282 struct { 283 struct nv50_disp_mthd_v1 base; 284 struct nv50_disp_acquire_v0 info; 285 } args = { 286 .base.version = 1, 287 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 288 .base.hasht = nv_encoder->dcb->hasht, 289 .base.hashm = nv_encoder->dcb->hashm, 290 }; 291 int ret; 292 293 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 294 if (ret) { 295 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 296 return ret; 297 } 298 299 nv_encoder->or = args.info.or; 300 nv_encoder->link = args.info.link; 301 return 0; 302 } 303 304 static int 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 306 struct drm_crtc_state *crtc_state, 307 struct drm_connector_state *conn_state, 308 struct drm_display_mode *native_mode) 309 { 310 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 311 struct drm_display_mode *mode = &crtc_state->mode; 312 struct drm_connector *connector = conn_state->connector; 313 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 314 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 315 316 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 317 asyc->scaler.full = false; 318 if (!native_mode) 319 return 0; 320 321 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 322 switch (connector->connector_type) { 323 case DRM_MODE_CONNECTOR_LVDS: 324 case DRM_MODE_CONNECTOR_eDP: 325 /* Force use of scaler for non-EDID modes. */ 326 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) 327 break; 328 mode = native_mode; 329 asyc->scaler.full = true; 330 break; 331 default: 332 break; 333 } 334 } else { 335 mode = native_mode; 336 } 337 338 if (!drm_mode_equal(adjusted_mode, mode)) { 339 drm_mode_copy(adjusted_mode, mode); 340 crtc_state->mode_changed = true; 341 } 342 343 return 0; 344 } 345 346 static int 347 nv50_outp_atomic_check(struct drm_encoder *encoder, 348 struct drm_crtc_state *crtc_state, 349 struct drm_connector_state *conn_state) 350 { 351 struct nouveau_connector *nv_connector = 352 nouveau_connector(conn_state->connector); 353 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 354 nv_connector->native_mode); 355 } 356 357 /****************************************************************************** 358 * DAC 359 *****************************************************************************/ 360 static void 361 nv50_dac_disable(struct drm_encoder *encoder) 362 { 363 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 364 struct nv50_core *core = nv50_disp(encoder->dev)->core; 365 if (nv_encoder->crtc) 366 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 367 nv_encoder->crtc = NULL; 368 nv50_outp_release(nv_encoder); 369 } 370 371 static void 372 nv50_dac_enable(struct drm_encoder *encoder) 373 { 374 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 375 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 376 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 377 struct nv50_core *core = nv50_disp(encoder->dev)->core; 378 379 nv50_outp_acquire(nv_encoder); 380 381 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 382 asyh->or.depth = 0; 383 384 nv_encoder->crtc = encoder->crtc; 385 } 386 387 static enum drm_connector_status 388 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 389 { 390 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 391 struct nv50_disp *disp = nv50_disp(encoder->dev); 392 struct { 393 struct nv50_disp_mthd_v1 base; 394 struct nv50_disp_dac_load_v0 load; 395 } args = { 396 .base.version = 1, 397 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 398 .base.hasht = nv_encoder->dcb->hasht, 399 .base.hashm = nv_encoder->dcb->hashm, 400 }; 401 int ret; 402 403 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 404 if (args.load.data == 0) 405 args.load.data = 340; 406 407 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 408 if (ret || !args.load.load) 409 return connector_status_disconnected; 410 411 return connector_status_connected; 412 } 413 414 static const struct drm_encoder_helper_funcs 415 nv50_dac_help = { 416 .atomic_check = nv50_outp_atomic_check, 417 .enable = nv50_dac_enable, 418 .disable = nv50_dac_disable, 419 .detect = nv50_dac_detect 420 }; 421 422 static void 423 nv50_dac_destroy(struct drm_encoder *encoder) 424 { 425 drm_encoder_cleanup(encoder); 426 kfree(encoder); 427 } 428 429 static const struct drm_encoder_funcs 430 nv50_dac_func = { 431 .destroy = nv50_dac_destroy, 432 }; 433 434 static int 435 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 436 { 437 struct nouveau_drm *drm = nouveau_drm(connector->dev); 438 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 439 struct nvkm_i2c_bus *bus; 440 struct nouveau_encoder *nv_encoder; 441 struct drm_encoder *encoder; 442 int type = DRM_MODE_ENCODER_DAC; 443 444 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 445 if (!nv_encoder) 446 return -ENOMEM; 447 nv_encoder->dcb = dcbe; 448 449 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 450 if (bus) 451 nv_encoder->i2c = &bus->i2c; 452 453 encoder = to_drm_encoder(nv_encoder); 454 encoder->possible_crtcs = dcbe->heads; 455 encoder->possible_clones = 0; 456 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 457 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 458 drm_encoder_helper_add(encoder, &nv50_dac_help); 459 460 drm_connector_attach_encoder(connector, encoder); 461 return 0; 462 } 463 464 /****************************************************************************** 465 * Audio 466 *****************************************************************************/ 467 static void 468 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 469 { 470 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 471 struct nv50_disp *disp = nv50_disp(encoder->dev); 472 struct { 473 struct nv50_disp_mthd_v1 base; 474 struct nv50_disp_sor_hda_eld_v0 eld; 475 } args = { 476 .base.version = 1, 477 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 478 .base.hasht = nv_encoder->dcb->hasht, 479 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 480 (0x0100 << nv_crtc->index), 481 }; 482 483 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 484 } 485 486 static void 487 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 488 { 489 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 490 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 491 struct nouveau_connector *nv_connector; 492 struct nv50_disp *disp = nv50_disp(encoder->dev); 493 struct __packed { 494 struct { 495 struct nv50_disp_mthd_v1 mthd; 496 struct nv50_disp_sor_hda_eld_v0 eld; 497 } base; 498 u8 data[sizeof(nv_connector->base.eld)]; 499 } args = { 500 .base.mthd.version = 1, 501 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 502 .base.mthd.hasht = nv_encoder->dcb->hasht, 503 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 504 (0x0100 << nv_crtc->index), 505 }; 506 507 nv_connector = nouveau_encoder_connector_get(nv_encoder); 508 if (!drm_detect_monitor_audio(nv_connector->edid)) 509 return; 510 511 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 512 513 nvif_mthd(&disp->disp->object, 0, &args, 514 sizeof(args.base) + drm_eld_size(args.data)); 515 } 516 517 /****************************************************************************** 518 * HDMI 519 *****************************************************************************/ 520 static void 521 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 522 { 523 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 524 struct nv50_disp *disp = nv50_disp(encoder->dev); 525 struct { 526 struct nv50_disp_mthd_v1 base; 527 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 528 } args = { 529 .base.version = 1, 530 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 531 .base.hasht = nv_encoder->dcb->hasht, 532 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 533 (0x0100 << nv_crtc->index), 534 }; 535 536 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 537 } 538 539 static void 540 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 541 { 542 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 543 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 544 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 545 struct nv50_disp *disp = nv50_disp(encoder->dev); 546 struct { 547 struct nv50_disp_mthd_v1 base; 548 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 549 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 550 } args = { 551 .base.version = 1, 552 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 553 .base.hasht = nv_encoder->dcb->hasht, 554 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 555 (0x0100 << nv_crtc->index), 556 .pwr.state = 1, 557 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 558 }; 559 struct nouveau_connector *nv_connector; 560 struct drm_hdmi_info *hdmi; 561 u32 max_ac_packet; 562 union hdmi_infoframe avi_frame; 563 union hdmi_infoframe vendor_frame; 564 bool high_tmds_clock_ratio = false, scrambling = false; 565 u8 config; 566 int ret; 567 int size; 568 569 nv_connector = nouveau_encoder_connector_get(nv_encoder); 570 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 571 return; 572 573 hdmi = &nv_connector->base.display_info.hdmi; 574 575 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 576 &nv_connector->base, mode); 577 if (!ret) { 578 /* We have an AVI InfoFrame, populate it to the display */ 579 args.pwr.avi_infoframe_length 580 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 581 } 582 583 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 584 &nv_connector->base, mode); 585 if (!ret) { 586 /* We have a Vendor InfoFrame, populate it to the display */ 587 args.pwr.vendor_infoframe_length 588 = hdmi_infoframe_pack(&vendor_frame, 589 args.infoframes 590 + args.pwr.avi_infoframe_length, 591 17); 592 } 593 594 max_ac_packet = mode->htotal - mode->hdisplay; 595 max_ac_packet -= args.pwr.rekey; 596 max_ac_packet -= 18; /* constant from tegra */ 597 args.pwr.max_ac_packet = max_ac_packet / 32; 598 599 if (hdmi->scdc.scrambling.supported) { 600 high_tmds_clock_ratio = mode->clock > 340000; 601 scrambling = high_tmds_clock_ratio || 602 hdmi->scdc.scrambling.low_rates; 603 } 604 605 args.pwr.scdc = 606 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 607 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 608 609 size = sizeof(args.base) 610 + sizeof(args.pwr) 611 + args.pwr.avi_infoframe_length 612 + args.pwr.vendor_infoframe_length; 613 nvif_mthd(&disp->disp->object, 0, &args, size); 614 615 nv50_audio_enable(encoder, mode); 616 617 /* If SCDC is supported by the downstream monitor, update 618 * divider / scrambling settings to what we programmed above. 619 */ 620 if (!hdmi->scdc.scrambling.supported) 621 return; 622 623 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 624 if (ret < 0) { 625 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 626 return; 627 } 628 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 629 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 630 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 631 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 632 if (ret < 0) 633 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 634 config, ret); 635 } 636 637 /****************************************************************************** 638 * MST 639 *****************************************************************************/ 640 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 641 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 642 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 643 644 struct nv50_mstm { 645 struct nouveau_encoder *outp; 646 647 struct drm_dp_mst_topology_mgr mgr; 648 struct nv50_msto *msto[4]; 649 650 bool modified; 651 bool disabled; 652 int links; 653 }; 654 655 struct nv50_mstc { 656 struct nv50_mstm *mstm; 657 struct drm_dp_mst_port *port; 658 struct drm_connector connector; 659 660 struct drm_display_mode *native; 661 struct edid *edid; 662 }; 663 664 struct nv50_msto { 665 struct drm_encoder encoder; 666 667 struct nv50_head *head; 668 struct nv50_mstc *mstc; 669 bool disabled; 670 }; 671 672 static struct drm_dp_payload * 673 nv50_msto_payload(struct nv50_msto *msto) 674 { 675 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 676 struct nv50_mstc *mstc = msto->mstc; 677 struct nv50_mstm *mstm = mstc->mstm; 678 int vcpi = mstc->port->vcpi.vcpi, i; 679 680 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 681 682 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 683 for (i = 0; i < mstm->mgr.max_payloads; i++) { 684 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 685 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 686 mstm->outp->base.base.name, i, payload->vcpi, 687 payload->start_slot, payload->num_slots); 688 } 689 690 for (i = 0; i < mstm->mgr.max_payloads; i++) { 691 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 692 if (payload->vcpi == vcpi) 693 return payload; 694 } 695 696 return NULL; 697 } 698 699 static void 700 nv50_msto_cleanup(struct nv50_msto *msto) 701 { 702 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 703 struct nv50_mstc *mstc = msto->mstc; 704 struct nv50_mstm *mstm = mstc->mstm; 705 706 if (!msto->disabled) 707 return; 708 709 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 710 711 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 712 713 msto->mstc = NULL; 714 msto->head = NULL; 715 msto->disabled = false; 716 } 717 718 static void 719 nv50_msto_prepare(struct nv50_msto *msto) 720 { 721 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 722 struct nv50_mstc *mstc = msto->mstc; 723 struct nv50_mstm *mstm = mstc->mstm; 724 struct { 725 struct nv50_disp_mthd_v1 base; 726 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 727 } args = { 728 .base.version = 1, 729 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 730 .base.hasht = mstm->outp->dcb->hasht, 731 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 732 (0x0100 << msto->head->base.index), 733 }; 734 735 mutex_lock(&mstm->mgr.payload_lock); 736 737 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 738 if (mstc->port->vcpi.vcpi > 0) { 739 struct drm_dp_payload *payload = nv50_msto_payload(msto); 740 if (payload) { 741 args.vcpi.start_slot = payload->start_slot; 742 args.vcpi.num_slots = payload->num_slots; 743 args.vcpi.pbn = mstc->port->vcpi.pbn; 744 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 745 } 746 } 747 748 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 749 msto->encoder.name, msto->head->base.base.name, 750 args.vcpi.start_slot, args.vcpi.num_slots, 751 args.vcpi.pbn, args.vcpi.aligned_pbn); 752 753 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 754 mutex_unlock(&mstm->mgr.payload_lock); 755 } 756 757 static int 758 nv50_msto_atomic_check(struct drm_encoder *encoder, 759 struct drm_crtc_state *crtc_state, 760 struct drm_connector_state *conn_state) 761 { 762 struct drm_atomic_state *state = crtc_state->state; 763 struct drm_connector *connector = conn_state->connector; 764 struct nv50_mstc *mstc = nv50_mstc(connector); 765 struct nv50_mstm *mstm = mstc->mstm; 766 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 767 int slots; 768 769 /* When restoring duplicated states, we need to make sure that the 770 * bw remains the same and avoid recalculating it, as the connector's 771 * bpc may have changed after the state was duplicated 772 */ 773 if (!state->duplicated) 774 asyh->dp.pbn = 775 drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, 776 connector->display_info.bpc * 3); 777 778 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 779 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, 780 mstc->port, 781 asyh->dp.pbn); 782 if (slots < 0) 783 return slots; 784 785 asyh->dp.tu = slots; 786 } 787 788 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 789 mstc->native); 790 } 791 792 static void 793 nv50_msto_enable(struct drm_encoder *encoder) 794 { 795 struct nv50_head *head = nv50_head(encoder->crtc); 796 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 797 struct nv50_msto *msto = nv50_msto(encoder); 798 struct nv50_mstc *mstc = NULL; 799 struct nv50_mstm *mstm = NULL; 800 struct drm_connector *connector; 801 struct drm_connector_list_iter conn_iter; 802 u8 proto, depth; 803 bool r; 804 805 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 806 drm_for_each_connector_iter(connector, &conn_iter) { 807 if (connector->state->best_encoder == &msto->encoder) { 808 mstc = nv50_mstc(connector); 809 mstm = mstc->mstm; 810 break; 811 } 812 } 813 drm_connector_list_iter_end(&conn_iter); 814 815 if (WARN_ON(!mstc)) 816 return; 817 818 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 819 armh->dp.tu); 820 if (!r) 821 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 822 823 if (!mstm->links++) 824 nv50_outp_acquire(mstm->outp); 825 826 if (mstm->outp->link & 1) 827 proto = 0x8; 828 else 829 proto = 0x9; 830 831 switch (mstc->connector.display_info.bpc) { 832 case 6: depth = 0x2; break; 833 case 8: depth = 0x5; break; 834 case 10: 835 default: depth = 0x6; break; 836 } 837 838 mstm->outp->update(mstm->outp, head->base.index, armh, proto, depth); 839 840 msto->head = head; 841 msto->mstc = mstc; 842 mstm->modified = true; 843 } 844 845 static void 846 nv50_msto_disable(struct drm_encoder *encoder) 847 { 848 struct nv50_msto *msto = nv50_msto(encoder); 849 struct nv50_mstc *mstc = msto->mstc; 850 struct nv50_mstm *mstm = mstc->mstm; 851 852 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 853 854 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 855 mstm->modified = true; 856 if (!--mstm->links) 857 mstm->disabled = true; 858 msto->disabled = true; 859 } 860 861 static const struct drm_encoder_helper_funcs 862 nv50_msto_help = { 863 .disable = nv50_msto_disable, 864 .enable = nv50_msto_enable, 865 .atomic_check = nv50_msto_atomic_check, 866 }; 867 868 static void 869 nv50_msto_destroy(struct drm_encoder *encoder) 870 { 871 struct nv50_msto *msto = nv50_msto(encoder); 872 drm_encoder_cleanup(&msto->encoder); 873 kfree(msto); 874 } 875 876 static const struct drm_encoder_funcs 877 nv50_msto = { 878 .destroy = nv50_msto_destroy, 879 }; 880 881 static int 882 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, 883 struct nv50_msto **pmsto) 884 { 885 struct nv50_msto *msto; 886 int ret; 887 888 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) 889 return -ENOMEM; 890 891 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 892 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); 893 if (ret) { 894 kfree(*pmsto); 895 *pmsto = NULL; 896 return ret; 897 } 898 899 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 900 msto->encoder.possible_crtcs = heads; 901 return 0; 902 } 903 904 static struct drm_encoder * 905 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 906 struct drm_connector_state *connector_state) 907 { 908 struct nv50_head *head = nv50_head(connector_state->crtc); 909 struct nv50_mstc *mstc = nv50_mstc(connector); 910 911 return &mstc->mstm->msto[head->base.index]->encoder; 912 } 913 914 static struct drm_encoder * 915 nv50_mstc_best_encoder(struct drm_connector *connector) 916 { 917 struct nv50_mstc *mstc = nv50_mstc(connector); 918 919 return &mstc->mstm->msto[0]->encoder; 920 } 921 922 static enum drm_mode_status 923 nv50_mstc_mode_valid(struct drm_connector *connector, 924 struct drm_display_mode *mode) 925 { 926 return MODE_OK; 927 } 928 929 static int 930 nv50_mstc_get_modes(struct drm_connector *connector) 931 { 932 struct nv50_mstc *mstc = nv50_mstc(connector); 933 int ret = 0; 934 935 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 936 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 937 if (mstc->edid) 938 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 939 940 if (!mstc->connector.display_info.bpc) 941 mstc->connector.display_info.bpc = 8; 942 943 if (mstc->native) 944 drm_mode_destroy(mstc->connector.dev, mstc->native); 945 mstc->native = nouveau_conn_native_mode(&mstc->connector); 946 return ret; 947 } 948 949 static int 950 nv50_mstc_atomic_check(struct drm_connector *connector, 951 struct drm_atomic_state *state) 952 { 953 struct nv50_mstc *mstc = nv50_mstc(connector); 954 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 955 struct drm_connector_state *new_conn_state = 956 drm_atomic_get_new_connector_state(state, connector); 957 struct drm_connector_state *old_conn_state = 958 drm_atomic_get_old_connector_state(state, connector); 959 struct drm_crtc_state *crtc_state; 960 struct drm_crtc *new_crtc = new_conn_state->crtc; 961 962 if (!old_conn_state->crtc) 963 return 0; 964 965 /* We only want to free VCPI if this state disables the CRTC on this 966 * connector 967 */ 968 if (new_crtc) { 969 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 970 971 if (!crtc_state || 972 !drm_atomic_crtc_needs_modeset(crtc_state) || 973 crtc_state->enable) 974 return 0; 975 } 976 977 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 978 } 979 980 static const struct drm_connector_helper_funcs 981 nv50_mstc_help = { 982 .get_modes = nv50_mstc_get_modes, 983 .mode_valid = nv50_mstc_mode_valid, 984 .best_encoder = nv50_mstc_best_encoder, 985 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 986 .atomic_check = nv50_mstc_atomic_check, 987 }; 988 989 static enum drm_connector_status 990 nv50_mstc_detect(struct drm_connector *connector, bool force) 991 { 992 struct nv50_mstc *mstc = nv50_mstc(connector); 993 enum drm_connector_status conn_status; 994 int ret; 995 996 if (drm_connector_is_unregistered(connector)) 997 return connector_status_disconnected; 998 999 ret = pm_runtime_get_sync(connector->dev->dev); 1000 if (ret < 0 && ret != -EACCES) 1001 return connector_status_disconnected; 1002 1003 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr, 1004 mstc->port); 1005 1006 pm_runtime_mark_last_busy(connector->dev->dev); 1007 pm_runtime_put_autosuspend(connector->dev->dev); 1008 return conn_status; 1009 } 1010 1011 static void 1012 nv50_mstc_destroy(struct drm_connector *connector) 1013 { 1014 struct nv50_mstc *mstc = nv50_mstc(connector); 1015 1016 drm_connector_cleanup(&mstc->connector); 1017 drm_dp_mst_put_port_malloc(mstc->port); 1018 1019 kfree(mstc); 1020 } 1021 1022 static const struct drm_connector_funcs 1023 nv50_mstc = { 1024 .reset = nouveau_conn_reset, 1025 .detect = nv50_mstc_detect, 1026 .fill_modes = drm_helper_probe_single_connector_modes, 1027 .destroy = nv50_mstc_destroy, 1028 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1029 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1030 .atomic_set_property = nouveau_conn_atomic_set_property, 1031 .atomic_get_property = nouveau_conn_atomic_get_property, 1032 }; 1033 1034 static int 1035 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1036 const char *path, struct nv50_mstc **pmstc) 1037 { 1038 struct drm_device *dev = mstm->outp->base.base.dev; 1039 struct nv50_mstc *mstc; 1040 int ret, i; 1041 1042 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1043 return -ENOMEM; 1044 mstc->mstm = mstm; 1045 mstc->port = port; 1046 1047 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1048 DRM_MODE_CONNECTOR_DisplayPort); 1049 if (ret) { 1050 kfree(*pmstc); 1051 *pmstc = NULL; 1052 return ret; 1053 } 1054 1055 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1056 1057 mstc->connector.funcs->reset(&mstc->connector); 1058 nouveau_conn_attach_properties(&mstc->connector); 1059 1060 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) 1061 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); 1062 1063 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1064 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1065 drm_connector_set_path_property(&mstc->connector, path); 1066 drm_dp_mst_get_port_malloc(port); 1067 return 0; 1068 } 1069 1070 static void 1071 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1072 { 1073 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1074 struct drm_encoder *encoder; 1075 int ret; 1076 1077 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1078 ret = drm_dp_check_act_status(&mstm->mgr); 1079 1080 ret = drm_dp_update_payload_part2(&mstm->mgr); 1081 1082 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1083 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1084 struct nv50_msto *msto = nv50_msto(encoder); 1085 struct nv50_mstc *mstc = msto->mstc; 1086 if (mstc && mstc->mstm == mstm) 1087 nv50_msto_cleanup(msto); 1088 } 1089 } 1090 1091 mstm->modified = false; 1092 } 1093 1094 static void 1095 nv50_mstm_prepare(struct nv50_mstm *mstm) 1096 { 1097 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1098 struct drm_encoder *encoder; 1099 int ret; 1100 1101 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1102 ret = drm_dp_update_payload_part1(&mstm->mgr); 1103 1104 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1105 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1106 struct nv50_msto *msto = nv50_msto(encoder); 1107 struct nv50_mstc *mstc = msto->mstc; 1108 if (mstc && mstc->mstm == mstm) 1109 nv50_msto_prepare(msto); 1110 } 1111 } 1112 1113 if (mstm->disabled) { 1114 if (!mstm->links) 1115 nv50_outp_release(mstm->outp); 1116 mstm->disabled = false; 1117 } 1118 } 1119 1120 static void 1121 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 1122 struct drm_connector *connector) 1123 { 1124 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1125 struct nv50_mstc *mstc = nv50_mstc(connector); 1126 1127 drm_connector_unregister(&mstc->connector); 1128 1129 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 1130 1131 drm_connector_put(&mstc->connector); 1132 } 1133 1134 static void 1135 nv50_mstm_register_connector(struct drm_connector *connector) 1136 { 1137 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1138 1139 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 1140 1141 drm_connector_register(connector); 1142 } 1143 1144 static struct drm_connector * 1145 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1146 struct drm_dp_mst_port *port, const char *path) 1147 { 1148 struct nv50_mstm *mstm = nv50_mstm(mgr); 1149 struct nv50_mstc *mstc; 1150 int ret; 1151 1152 ret = nv50_mstc_new(mstm, port, path, &mstc); 1153 if (ret) 1154 return NULL; 1155 1156 return &mstc->connector; 1157 } 1158 1159 static const struct drm_dp_mst_topology_cbs 1160 nv50_mstm = { 1161 .add_connector = nv50_mstm_add_connector, 1162 .register_connector = nv50_mstm_register_connector, 1163 .destroy_connector = nv50_mstm_destroy_connector, 1164 }; 1165 1166 void 1167 nv50_mstm_service(struct nv50_mstm *mstm) 1168 { 1169 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1170 bool handled = true; 1171 int ret; 1172 u8 esi[8] = {}; 1173 1174 if (!aux) 1175 return; 1176 1177 while (handled) { 1178 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1179 if (ret != 8) { 1180 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1181 return; 1182 } 1183 1184 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1185 if (!handled) 1186 break; 1187 1188 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1189 } 1190 } 1191 1192 void 1193 nv50_mstm_remove(struct nv50_mstm *mstm) 1194 { 1195 if (mstm) 1196 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1197 } 1198 1199 static int 1200 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1201 { 1202 struct nouveau_encoder *outp = mstm->outp; 1203 struct { 1204 struct nv50_disp_mthd_v1 base; 1205 struct nv50_disp_sor_dp_mst_link_v0 mst; 1206 } args = { 1207 .base.version = 1, 1208 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1209 .base.hasht = outp->dcb->hasht, 1210 .base.hashm = outp->dcb->hashm, 1211 .mst.state = state, 1212 }; 1213 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1214 struct nvif_object *disp = &drm->display->disp.object; 1215 int ret; 1216 1217 if (dpcd >= 0x12) { 1218 /* Even if we're enabling MST, start with disabling the 1219 * branching unit to clear any sink-side MST topology state 1220 * that wasn't set by us 1221 */ 1222 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1223 if (ret < 0) 1224 return ret; 1225 1226 if (state) { 1227 /* Now, start initializing */ 1228 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1229 DP_MST_EN); 1230 if (ret < 0) 1231 return ret; 1232 } 1233 } 1234 1235 return nvif_mthd(disp, 0, &args, sizeof(args)); 1236 } 1237 1238 int 1239 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1240 { 1241 struct drm_dp_aux *aux; 1242 int ret; 1243 bool old_state, new_state; 1244 u8 mstm_ctrl; 1245 1246 if (!mstm) 1247 return 0; 1248 1249 mutex_lock(&mstm->mgr.lock); 1250 1251 old_state = mstm->mgr.mst_state; 1252 new_state = old_state; 1253 aux = mstm->mgr.aux; 1254 1255 if (old_state) { 1256 /* Just check that the MST hub is still as we expect it */ 1257 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1258 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1259 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1260 new_state = false; 1261 } 1262 } else if (dpcd[0] >= 0x12) { 1263 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1264 if (ret < 0) 1265 goto probe_error; 1266 1267 if (!(dpcd[1] & DP_MST_CAP)) 1268 dpcd[0] = 0x11; 1269 else 1270 new_state = allow; 1271 } 1272 1273 if (new_state == old_state) { 1274 mutex_unlock(&mstm->mgr.lock); 1275 return new_state; 1276 } 1277 1278 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1279 if (ret) 1280 goto probe_error; 1281 1282 mutex_unlock(&mstm->mgr.lock); 1283 1284 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1285 if (ret) 1286 return nv50_mstm_enable(mstm, dpcd[0], 0); 1287 1288 return new_state; 1289 1290 probe_error: 1291 mutex_unlock(&mstm->mgr.lock); 1292 return ret; 1293 } 1294 1295 static void 1296 nv50_mstm_fini(struct nv50_mstm *mstm) 1297 { 1298 if (mstm && mstm->mgr.mst_state) 1299 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1300 } 1301 1302 static void 1303 nv50_mstm_init(struct nv50_mstm *mstm) 1304 { 1305 int ret; 1306 1307 if (!mstm || !mstm->mgr.mst_state) 1308 return; 1309 1310 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr); 1311 if (ret == -1) { 1312 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1313 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1314 } 1315 } 1316 1317 static void 1318 nv50_mstm_del(struct nv50_mstm **pmstm) 1319 { 1320 struct nv50_mstm *mstm = *pmstm; 1321 if (mstm) { 1322 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1323 kfree(*pmstm); 1324 *pmstm = NULL; 1325 } 1326 } 1327 1328 static int 1329 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1330 int conn_base_id, struct nv50_mstm **pmstm) 1331 { 1332 const int max_payloads = hweight8(outp->dcb->heads); 1333 struct drm_device *dev = outp->base.base.dev; 1334 struct nv50_mstm *mstm; 1335 int ret, i; 1336 u8 dpcd; 1337 1338 /* This is a workaround for some monitors not functioning 1339 * correctly in MST mode on initial module load. I think 1340 * some bad interaction with the VBIOS may be responsible. 1341 * 1342 * A good ol' off and on again seems to work here ;) 1343 */ 1344 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1345 if (ret >= 0 && dpcd >= 0x12) 1346 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1347 1348 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1349 return -ENOMEM; 1350 mstm->outp = outp; 1351 mstm->mgr.cbs = &nv50_mstm; 1352 1353 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1354 max_payloads, conn_base_id); 1355 if (ret) 1356 return ret; 1357 1358 for (i = 0; i < max_payloads; i++) { 1359 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, 1360 i, &mstm->msto[i]); 1361 if (ret) 1362 return ret; 1363 } 1364 1365 return 0; 1366 } 1367 1368 /****************************************************************************** 1369 * SOR 1370 *****************************************************************************/ 1371 static void 1372 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1373 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1374 { 1375 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1376 struct nv50_core *core = disp->core; 1377 1378 if (!asyh) { 1379 nv_encoder->ctrl &= ~BIT(head); 1380 if (!(nv_encoder->ctrl & 0x0000000f)) 1381 nv_encoder->ctrl = 0; 1382 } else { 1383 nv_encoder->ctrl |= proto << 8; 1384 nv_encoder->ctrl |= BIT(head); 1385 asyh->or.depth = depth; 1386 } 1387 1388 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1389 } 1390 1391 static void 1392 nv50_sor_disable(struct drm_encoder *encoder) 1393 { 1394 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1395 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1396 1397 nv_encoder->crtc = NULL; 1398 1399 if (nv_crtc) { 1400 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1401 u8 pwr; 1402 1403 if (aux) { 1404 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1405 if (ret == 0) { 1406 pwr &= ~DP_SET_POWER_MASK; 1407 pwr |= DP_SET_POWER_D3; 1408 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1409 } 1410 } 1411 1412 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1413 nv50_audio_disable(encoder, nv_crtc); 1414 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1415 nv50_outp_release(nv_encoder); 1416 } 1417 } 1418 1419 static void 1420 nv50_sor_enable(struct drm_encoder *encoder) 1421 { 1422 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1423 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1424 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1425 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1426 struct { 1427 struct nv50_disp_mthd_v1 base; 1428 struct nv50_disp_sor_lvds_script_v0 lvds; 1429 } lvds = { 1430 .base.version = 1, 1431 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1432 .base.hasht = nv_encoder->dcb->hasht, 1433 .base.hashm = nv_encoder->dcb->hashm, 1434 }; 1435 struct nv50_disp *disp = nv50_disp(encoder->dev); 1436 struct drm_device *dev = encoder->dev; 1437 struct nouveau_drm *drm = nouveau_drm(dev); 1438 struct nouveau_connector *nv_connector; 1439 struct nvbios *bios = &drm->vbios; 1440 u8 proto = 0xf; 1441 u8 depth = 0x0; 1442 1443 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1444 nv_encoder->crtc = encoder->crtc; 1445 nv50_outp_acquire(nv_encoder); 1446 1447 switch (nv_encoder->dcb->type) { 1448 case DCB_OUTPUT_TMDS: 1449 if (nv_encoder->link & 1) { 1450 proto = 0x1; 1451 /* Only enable dual-link if: 1452 * - Need to (i.e. rate > 165MHz) 1453 * - DCB says we can 1454 * - Not an HDMI monitor, since there's no dual-link 1455 * on HDMI. 1456 */ 1457 if (mode->clock >= 165000 && 1458 nv_encoder->dcb->duallink_possible && 1459 !drm_detect_hdmi_monitor(nv_connector->edid)) 1460 proto |= 0x4; 1461 } else { 1462 proto = 0x2; 1463 } 1464 1465 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1466 break; 1467 case DCB_OUTPUT_LVDS: 1468 proto = 0x0; 1469 1470 if (bios->fp_no_ddc) { 1471 if (bios->fp.dual_link) 1472 lvds.lvds.script |= 0x0100; 1473 if (bios->fp.if_is_24bit) 1474 lvds.lvds.script |= 0x0200; 1475 } else { 1476 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1477 if (((u8 *)nv_connector->edid)[121] == 2) 1478 lvds.lvds.script |= 0x0100; 1479 } else 1480 if (mode->clock >= bios->fp.duallink_transition_clk) { 1481 lvds.lvds.script |= 0x0100; 1482 } 1483 1484 if (lvds.lvds.script & 0x0100) { 1485 if (bios->fp.strapless_is_24bit & 2) 1486 lvds.lvds.script |= 0x0200; 1487 } else { 1488 if (bios->fp.strapless_is_24bit & 1) 1489 lvds.lvds.script |= 0x0200; 1490 } 1491 1492 if (nv_connector->base.display_info.bpc == 8) 1493 lvds.lvds.script |= 0x0200; 1494 } 1495 1496 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1497 break; 1498 case DCB_OUTPUT_DP: 1499 if (nv_connector->base.display_info.bpc == 6) 1500 depth = 0x2; 1501 else 1502 if (nv_connector->base.display_info.bpc == 8) 1503 depth = 0x5; 1504 else 1505 depth = 0x6; 1506 1507 if (nv_encoder->link & 1) 1508 proto = 0x8; 1509 else 1510 proto = 0x9; 1511 1512 nv50_audio_enable(encoder, mode); 1513 break; 1514 default: 1515 BUG(); 1516 break; 1517 } 1518 1519 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1520 } 1521 1522 static const struct drm_encoder_helper_funcs 1523 nv50_sor_help = { 1524 .atomic_check = nv50_outp_atomic_check, 1525 .enable = nv50_sor_enable, 1526 .disable = nv50_sor_disable, 1527 }; 1528 1529 static void 1530 nv50_sor_destroy(struct drm_encoder *encoder) 1531 { 1532 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1533 nv50_mstm_del(&nv_encoder->dp.mstm); 1534 drm_encoder_cleanup(encoder); 1535 kfree(encoder); 1536 } 1537 1538 static const struct drm_encoder_funcs 1539 nv50_sor_func = { 1540 .destroy = nv50_sor_destroy, 1541 }; 1542 1543 static int 1544 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1545 { 1546 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1547 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1548 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1549 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1550 struct nouveau_encoder *nv_encoder; 1551 struct drm_encoder *encoder; 1552 u8 ver, hdr, cnt, len; 1553 u32 data; 1554 int type, ret; 1555 1556 switch (dcbe->type) { 1557 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1558 case DCB_OUTPUT_TMDS: 1559 case DCB_OUTPUT_DP: 1560 default: 1561 type = DRM_MODE_ENCODER_TMDS; 1562 break; 1563 } 1564 1565 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1566 if (!nv_encoder) 1567 return -ENOMEM; 1568 nv_encoder->dcb = dcbe; 1569 nv_encoder->update = nv50_sor_update; 1570 1571 encoder = to_drm_encoder(nv_encoder); 1572 encoder->possible_crtcs = dcbe->heads; 1573 encoder->possible_clones = 0; 1574 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1575 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1576 drm_encoder_helper_add(encoder, &nv50_sor_help); 1577 1578 drm_connector_attach_encoder(connector, encoder); 1579 1580 if (dcbe->type == DCB_OUTPUT_DP) { 1581 struct nv50_disp *disp = nv50_disp(encoder->dev); 1582 struct nvkm_i2c_aux *aux = 1583 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1584 if (aux) { 1585 if (disp->disp->object.oclass < GF110_DISP) { 1586 /* HW has no support for address-only 1587 * transactions, so we're required to 1588 * use custom I2C-over-AUX code. 1589 */ 1590 nv_encoder->i2c = &aux->i2c; 1591 } else { 1592 nv_encoder->i2c = &nv_connector->aux.ddc; 1593 } 1594 nv_encoder->aux = aux; 1595 } 1596 1597 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && 1598 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) { 1599 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, 1600 nv_connector->base.base.id, 1601 &nv_encoder->dp.mstm); 1602 if (ret) 1603 return ret; 1604 } 1605 } else { 1606 struct nvkm_i2c_bus *bus = 1607 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1608 if (bus) 1609 nv_encoder->i2c = &bus->i2c; 1610 } 1611 1612 return 0; 1613 } 1614 1615 /****************************************************************************** 1616 * PIOR 1617 *****************************************************************************/ 1618 static int 1619 nv50_pior_atomic_check(struct drm_encoder *encoder, 1620 struct drm_crtc_state *crtc_state, 1621 struct drm_connector_state *conn_state) 1622 { 1623 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1624 if (ret) 1625 return ret; 1626 crtc_state->adjusted_mode.clock *= 2; 1627 return 0; 1628 } 1629 1630 static void 1631 nv50_pior_disable(struct drm_encoder *encoder) 1632 { 1633 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1634 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1635 if (nv_encoder->crtc) 1636 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1637 nv_encoder->crtc = NULL; 1638 nv50_outp_release(nv_encoder); 1639 } 1640 1641 static void 1642 nv50_pior_enable(struct drm_encoder *encoder) 1643 { 1644 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1645 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1646 struct nouveau_connector *nv_connector; 1647 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1648 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1649 u8 owner = 1 << nv_crtc->index; 1650 u8 proto; 1651 1652 nv50_outp_acquire(nv_encoder); 1653 1654 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1655 switch (nv_connector->base.display_info.bpc) { 1656 case 10: asyh->or.depth = 0x6; break; 1657 case 8: asyh->or.depth = 0x5; break; 1658 case 6: asyh->or.depth = 0x2; break; 1659 default: asyh->or.depth = 0x0; break; 1660 } 1661 1662 switch (nv_encoder->dcb->type) { 1663 case DCB_OUTPUT_TMDS: 1664 case DCB_OUTPUT_DP: 1665 proto = 0x0; 1666 break; 1667 default: 1668 BUG(); 1669 break; 1670 } 1671 1672 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1673 nv_encoder->crtc = encoder->crtc; 1674 } 1675 1676 static const struct drm_encoder_helper_funcs 1677 nv50_pior_help = { 1678 .atomic_check = nv50_pior_atomic_check, 1679 .enable = nv50_pior_enable, 1680 .disable = nv50_pior_disable, 1681 }; 1682 1683 static void 1684 nv50_pior_destroy(struct drm_encoder *encoder) 1685 { 1686 drm_encoder_cleanup(encoder); 1687 kfree(encoder); 1688 } 1689 1690 static const struct drm_encoder_funcs 1691 nv50_pior_func = { 1692 .destroy = nv50_pior_destroy, 1693 }; 1694 1695 static int 1696 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1697 { 1698 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1699 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1700 struct nvkm_i2c_bus *bus = NULL; 1701 struct nvkm_i2c_aux *aux = NULL; 1702 struct i2c_adapter *ddc; 1703 struct nouveau_encoder *nv_encoder; 1704 struct drm_encoder *encoder; 1705 int type; 1706 1707 switch (dcbe->type) { 1708 case DCB_OUTPUT_TMDS: 1709 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1710 ddc = bus ? &bus->i2c : NULL; 1711 type = DRM_MODE_ENCODER_TMDS; 1712 break; 1713 case DCB_OUTPUT_DP: 1714 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1715 ddc = aux ? &aux->i2c : NULL; 1716 type = DRM_MODE_ENCODER_TMDS; 1717 break; 1718 default: 1719 return -ENODEV; 1720 } 1721 1722 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1723 if (!nv_encoder) 1724 return -ENOMEM; 1725 nv_encoder->dcb = dcbe; 1726 nv_encoder->i2c = ddc; 1727 nv_encoder->aux = aux; 1728 1729 encoder = to_drm_encoder(nv_encoder); 1730 encoder->possible_crtcs = dcbe->heads; 1731 encoder->possible_clones = 0; 1732 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1733 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1734 drm_encoder_helper_add(encoder, &nv50_pior_help); 1735 1736 drm_connector_attach_encoder(connector, encoder); 1737 return 0; 1738 } 1739 1740 /****************************************************************************** 1741 * Atomic 1742 *****************************************************************************/ 1743 1744 static void 1745 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1746 { 1747 struct nouveau_drm *drm = nouveau_drm(state->dev); 1748 struct nv50_disp *disp = nv50_disp(drm->dev); 1749 struct nv50_core *core = disp->core; 1750 struct nv50_mstm *mstm; 1751 struct drm_encoder *encoder; 1752 1753 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1754 1755 drm_for_each_encoder(encoder, drm->dev) { 1756 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1757 mstm = nouveau_encoder(encoder)->dp.mstm; 1758 if (mstm && mstm->modified) 1759 nv50_mstm_prepare(mstm); 1760 } 1761 } 1762 1763 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1764 core->func->update(core, interlock, true); 1765 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1766 disp->core->chan.base.device)) 1767 NV_ERROR(drm, "core notifier timeout\n"); 1768 1769 drm_for_each_encoder(encoder, drm->dev) { 1770 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1771 mstm = nouveau_encoder(encoder)->dp.mstm; 1772 if (mstm && mstm->modified) 1773 nv50_mstm_cleanup(mstm); 1774 } 1775 } 1776 } 1777 1778 static void 1779 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1780 { 1781 struct drm_plane_state *new_plane_state; 1782 struct drm_plane *plane; 1783 int i; 1784 1785 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1786 struct nv50_wndw *wndw = nv50_wndw(plane); 1787 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1788 if (wndw->func->update) 1789 wndw->func->update(wndw, interlock); 1790 } 1791 } 1792 } 1793 1794 static void 1795 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1796 { 1797 struct drm_device *dev = state->dev; 1798 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1799 struct drm_crtc *crtc; 1800 struct drm_plane_state *new_plane_state; 1801 struct drm_plane *plane; 1802 struct nouveau_drm *drm = nouveau_drm(dev); 1803 struct nv50_disp *disp = nv50_disp(dev); 1804 struct nv50_atom *atom = nv50_atom(state); 1805 struct nv50_outp_atom *outp, *outt; 1806 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1807 int i; 1808 1809 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1810 drm_atomic_helper_wait_for_fences(dev, state, false); 1811 drm_atomic_helper_wait_for_dependencies(state); 1812 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1813 1814 if (atom->lock_core) 1815 mutex_lock(&disp->mutex); 1816 1817 /* Disable head(s). */ 1818 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1819 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1820 struct nv50_head *head = nv50_head(crtc); 1821 1822 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1823 asyh->clr.mask, asyh->set.mask); 1824 if (old_crtc_state->active && !new_crtc_state->active) 1825 drm_crtc_vblank_off(crtc); 1826 1827 if (asyh->clr.mask) { 1828 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1829 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1830 } 1831 } 1832 1833 /* Disable plane(s). */ 1834 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1835 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1836 struct nv50_wndw *wndw = nv50_wndw(plane); 1837 1838 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1839 asyw->clr.mask, asyw->set.mask); 1840 if (!asyw->clr.mask) 1841 continue; 1842 1843 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1844 } 1845 1846 /* Disable output path(s). */ 1847 list_for_each_entry(outp, &atom->outp, head) { 1848 const struct drm_encoder_helper_funcs *help; 1849 struct drm_encoder *encoder; 1850 1851 encoder = outp->encoder; 1852 help = encoder->helper_private; 1853 1854 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1855 outp->clr.mask, outp->set.mask); 1856 1857 if (outp->clr.mask) { 1858 help->disable(encoder); 1859 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1860 if (outp->flush_disable) { 1861 nv50_disp_atomic_commit_wndw(state, interlock); 1862 nv50_disp_atomic_commit_core(state, interlock); 1863 memset(interlock, 0x00, sizeof(interlock)); 1864 } 1865 } 1866 } 1867 1868 /* Flush disable. */ 1869 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1870 if (atom->flush_disable) { 1871 nv50_disp_atomic_commit_wndw(state, interlock); 1872 nv50_disp_atomic_commit_core(state, interlock); 1873 memset(interlock, 0x00, sizeof(interlock)); 1874 } 1875 } 1876 1877 /* Update output path(s). */ 1878 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1879 const struct drm_encoder_helper_funcs *help; 1880 struct drm_encoder *encoder; 1881 1882 encoder = outp->encoder; 1883 help = encoder->helper_private; 1884 1885 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 1886 outp->set.mask, outp->clr.mask); 1887 1888 if (outp->set.mask) { 1889 help->enable(encoder); 1890 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1891 } 1892 1893 list_del(&outp->head); 1894 kfree(outp); 1895 } 1896 1897 /* Update head(s). */ 1898 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1899 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1900 struct nv50_head *head = nv50_head(crtc); 1901 1902 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 1903 asyh->set.mask, asyh->clr.mask); 1904 1905 if (asyh->set.mask) { 1906 nv50_head_flush_set(head, asyh); 1907 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1908 } 1909 1910 if (new_crtc_state->active) { 1911 if (!old_crtc_state->active) 1912 drm_crtc_vblank_on(crtc); 1913 if (new_crtc_state->event) 1914 drm_crtc_vblank_get(crtc); 1915 } 1916 } 1917 1918 /* Update plane(s). */ 1919 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1920 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1921 struct nv50_wndw *wndw = nv50_wndw(plane); 1922 1923 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 1924 asyw->set.mask, asyw->clr.mask); 1925 if ( !asyw->set.mask && 1926 (!asyw->clr.mask || atom->flush_disable)) 1927 continue; 1928 1929 nv50_wndw_flush_set(wndw, interlock, asyw); 1930 } 1931 1932 /* Flush update. */ 1933 nv50_disp_atomic_commit_wndw(state, interlock); 1934 1935 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1936 if (interlock[NV50_DISP_INTERLOCK_BASE] || 1937 interlock[NV50_DISP_INTERLOCK_OVLY] || 1938 interlock[NV50_DISP_INTERLOCK_WNDW] || 1939 !atom->state.legacy_cursor_update) 1940 nv50_disp_atomic_commit_core(state, interlock); 1941 else 1942 disp->core->func->update(disp->core, interlock, false); 1943 } 1944 1945 if (atom->lock_core) 1946 mutex_unlock(&disp->mutex); 1947 1948 /* Wait for HW to signal completion. */ 1949 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1950 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1951 struct nv50_wndw *wndw = nv50_wndw(plane); 1952 int ret = nv50_wndw_wait_armed(wndw, asyw); 1953 if (ret) 1954 NV_ERROR(drm, "%s: timeout\n", plane->name); 1955 } 1956 1957 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 1958 if (new_crtc_state->event) { 1959 unsigned long flags; 1960 /* Get correct count/ts if racing with vblank irq */ 1961 if (new_crtc_state->active) 1962 drm_crtc_accurate_vblank_count(crtc); 1963 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1964 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 1965 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1966 1967 new_crtc_state->event = NULL; 1968 if (new_crtc_state->active) 1969 drm_crtc_vblank_put(crtc); 1970 } 1971 } 1972 1973 drm_atomic_helper_commit_hw_done(state); 1974 drm_atomic_helper_cleanup_planes(dev, state); 1975 drm_atomic_helper_commit_cleanup_done(state); 1976 drm_atomic_state_put(state); 1977 } 1978 1979 static void 1980 nv50_disp_atomic_commit_work(struct work_struct *work) 1981 { 1982 struct drm_atomic_state *state = 1983 container_of(work, typeof(*state), commit_work); 1984 nv50_disp_atomic_commit_tail(state); 1985 } 1986 1987 static int 1988 nv50_disp_atomic_commit(struct drm_device *dev, 1989 struct drm_atomic_state *state, bool nonblock) 1990 { 1991 struct nouveau_drm *drm = nouveau_drm(dev); 1992 struct drm_plane_state *new_plane_state; 1993 struct drm_plane *plane; 1994 struct drm_crtc *crtc; 1995 bool active = false; 1996 int ret, i; 1997 1998 ret = pm_runtime_get_sync(dev->dev); 1999 if (ret < 0 && ret != -EACCES) 2000 return ret; 2001 2002 ret = drm_atomic_helper_setup_commit(state, nonblock); 2003 if (ret) 2004 goto done; 2005 2006 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2007 2008 ret = drm_atomic_helper_prepare_planes(dev, state); 2009 if (ret) 2010 goto done; 2011 2012 if (!nonblock) { 2013 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2014 if (ret) 2015 goto err_cleanup; 2016 } 2017 2018 ret = drm_atomic_helper_swap_state(state, true); 2019 if (ret) 2020 goto err_cleanup; 2021 2022 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2023 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2024 struct nv50_wndw *wndw = nv50_wndw(plane); 2025 2026 if (asyw->set.image) 2027 nv50_wndw_ntfy_enable(wndw, asyw); 2028 } 2029 2030 drm_atomic_state_get(state); 2031 2032 if (nonblock) 2033 queue_work(system_unbound_wq, &state->commit_work); 2034 else 2035 nv50_disp_atomic_commit_tail(state); 2036 2037 drm_for_each_crtc(crtc, dev) { 2038 if (crtc->state->active) { 2039 if (!drm->have_disp_power_ref) { 2040 drm->have_disp_power_ref = true; 2041 return 0; 2042 } 2043 active = true; 2044 break; 2045 } 2046 } 2047 2048 if (!active && drm->have_disp_power_ref) { 2049 pm_runtime_put_autosuspend(dev->dev); 2050 drm->have_disp_power_ref = false; 2051 } 2052 2053 err_cleanup: 2054 if (ret) 2055 drm_atomic_helper_cleanup_planes(dev, state); 2056 done: 2057 pm_runtime_put_autosuspend(dev->dev); 2058 return ret; 2059 } 2060 2061 static struct nv50_outp_atom * 2062 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2063 { 2064 struct nv50_outp_atom *outp; 2065 2066 list_for_each_entry(outp, &atom->outp, head) { 2067 if (outp->encoder == encoder) 2068 return outp; 2069 } 2070 2071 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2072 if (!outp) 2073 return ERR_PTR(-ENOMEM); 2074 2075 list_add(&outp->head, &atom->outp); 2076 outp->encoder = encoder; 2077 return outp; 2078 } 2079 2080 static int 2081 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2082 struct drm_connector_state *old_connector_state) 2083 { 2084 struct drm_encoder *encoder = old_connector_state->best_encoder; 2085 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2086 struct drm_crtc *crtc; 2087 struct nv50_outp_atom *outp; 2088 2089 if (!(crtc = old_connector_state->crtc)) 2090 return 0; 2091 2092 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2093 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2094 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2095 outp = nv50_disp_outp_atomic_add(atom, encoder); 2096 if (IS_ERR(outp)) 2097 return PTR_ERR(outp); 2098 2099 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2100 outp->flush_disable = true; 2101 atom->flush_disable = true; 2102 } 2103 outp->clr.ctrl = true; 2104 atom->lock_core = true; 2105 } 2106 2107 return 0; 2108 } 2109 2110 static int 2111 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2112 struct drm_connector_state *connector_state) 2113 { 2114 struct drm_encoder *encoder = connector_state->best_encoder; 2115 struct drm_crtc_state *new_crtc_state; 2116 struct drm_crtc *crtc; 2117 struct nv50_outp_atom *outp; 2118 2119 if (!(crtc = connector_state->crtc)) 2120 return 0; 2121 2122 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2123 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2124 outp = nv50_disp_outp_atomic_add(atom, encoder); 2125 if (IS_ERR(outp)) 2126 return PTR_ERR(outp); 2127 2128 outp->set.ctrl = true; 2129 atom->lock_core = true; 2130 } 2131 2132 return 0; 2133 } 2134 2135 static int 2136 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2137 { 2138 struct nv50_atom *atom = nv50_atom(state); 2139 struct drm_connector_state *old_connector_state, *new_connector_state; 2140 struct drm_connector *connector; 2141 struct drm_crtc_state *new_crtc_state; 2142 struct drm_crtc *crtc; 2143 int ret, i; 2144 2145 /* We need to handle colour management on a per-plane basis. */ 2146 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2147 if (new_crtc_state->color_mgmt_changed) { 2148 ret = drm_atomic_add_affected_planes(state, crtc); 2149 if (ret) 2150 return ret; 2151 } 2152 } 2153 2154 ret = drm_atomic_helper_check(dev, state); 2155 if (ret) 2156 return ret; 2157 2158 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2159 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2160 if (ret) 2161 return ret; 2162 2163 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2164 if (ret) 2165 return ret; 2166 } 2167 2168 ret = drm_dp_mst_atomic_check(state); 2169 if (ret) 2170 return ret; 2171 2172 return 0; 2173 } 2174 2175 static void 2176 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2177 { 2178 struct nv50_atom *atom = nv50_atom(state); 2179 struct nv50_outp_atom *outp, *outt; 2180 2181 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2182 list_del(&outp->head); 2183 kfree(outp); 2184 } 2185 2186 drm_atomic_state_default_clear(state); 2187 } 2188 2189 static void 2190 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2191 { 2192 struct nv50_atom *atom = nv50_atom(state); 2193 drm_atomic_state_default_release(&atom->state); 2194 kfree(atom); 2195 } 2196 2197 static struct drm_atomic_state * 2198 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2199 { 2200 struct nv50_atom *atom; 2201 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2202 drm_atomic_state_init(dev, &atom->state) < 0) { 2203 kfree(atom); 2204 return NULL; 2205 } 2206 INIT_LIST_HEAD(&atom->outp); 2207 return &atom->state; 2208 } 2209 2210 static const struct drm_mode_config_funcs 2211 nv50_disp_func = { 2212 .fb_create = nouveau_user_framebuffer_create, 2213 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2214 .atomic_check = nv50_disp_atomic_check, 2215 .atomic_commit = nv50_disp_atomic_commit, 2216 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2217 .atomic_state_clear = nv50_disp_atomic_state_clear, 2218 .atomic_state_free = nv50_disp_atomic_state_free, 2219 }; 2220 2221 /****************************************************************************** 2222 * Init 2223 *****************************************************************************/ 2224 2225 static void 2226 nv50_display_fini(struct drm_device *dev, bool suspend) 2227 { 2228 struct nouveau_encoder *nv_encoder; 2229 struct drm_encoder *encoder; 2230 struct drm_plane *plane; 2231 2232 drm_for_each_plane(plane, dev) { 2233 struct nv50_wndw *wndw = nv50_wndw(plane); 2234 if (plane->funcs != &nv50_wndw) 2235 continue; 2236 nv50_wndw_fini(wndw); 2237 } 2238 2239 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2240 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2241 nv_encoder = nouveau_encoder(encoder); 2242 nv50_mstm_fini(nv_encoder->dp.mstm); 2243 } 2244 } 2245 } 2246 2247 static int 2248 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2249 { 2250 struct nv50_core *core = nv50_disp(dev)->core; 2251 struct drm_encoder *encoder; 2252 struct drm_plane *plane; 2253 2254 core->func->init(core); 2255 2256 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2257 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2258 struct nouveau_encoder *nv_encoder = 2259 nouveau_encoder(encoder); 2260 nv50_mstm_init(nv_encoder->dp.mstm); 2261 } 2262 } 2263 2264 drm_for_each_plane(plane, dev) { 2265 struct nv50_wndw *wndw = nv50_wndw(plane); 2266 if (plane->funcs != &nv50_wndw) 2267 continue; 2268 nv50_wndw_init(wndw); 2269 } 2270 2271 return 0; 2272 } 2273 2274 static void 2275 nv50_display_destroy(struct drm_device *dev) 2276 { 2277 struct nv50_disp *disp = nv50_disp(dev); 2278 2279 nv50_core_del(&disp->core); 2280 2281 nouveau_bo_unmap(disp->sync); 2282 if (disp->sync) 2283 nouveau_bo_unpin(disp->sync); 2284 nouveau_bo_ref(NULL, &disp->sync); 2285 2286 nouveau_display(dev)->priv = NULL; 2287 kfree(disp); 2288 } 2289 2290 int 2291 nv50_display_create(struct drm_device *dev) 2292 { 2293 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2294 struct nouveau_drm *drm = nouveau_drm(dev); 2295 struct dcb_table *dcb = &drm->vbios.dcb; 2296 struct drm_connector *connector, *tmp; 2297 struct nv50_disp *disp; 2298 struct dcb_output *dcbe; 2299 int crtcs, ret, i; 2300 2301 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2302 if (!disp) 2303 return -ENOMEM; 2304 2305 mutex_init(&disp->mutex); 2306 2307 nouveau_display(dev)->priv = disp; 2308 nouveau_display(dev)->dtor = nv50_display_destroy; 2309 nouveau_display(dev)->init = nv50_display_init; 2310 nouveau_display(dev)->fini = nv50_display_fini; 2311 disp->disp = &nouveau_display(dev)->disp; 2312 dev->mode_config.funcs = &nv50_disp_func; 2313 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2314 2315 /* small shared memory area we use for notifiers and semaphores */ 2316 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2317 0, 0x0000, NULL, NULL, &disp->sync); 2318 if (!ret) { 2319 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2320 if (!ret) { 2321 ret = nouveau_bo_map(disp->sync); 2322 if (ret) 2323 nouveau_bo_unpin(disp->sync); 2324 } 2325 if (ret) 2326 nouveau_bo_ref(NULL, &disp->sync); 2327 } 2328 2329 if (ret) 2330 goto out; 2331 2332 /* allocate master evo channel */ 2333 ret = nv50_core_new(drm, &disp->core); 2334 if (ret) 2335 goto out; 2336 2337 /* create crtc objects to represent the hw heads */ 2338 if (disp->disp->object.oclass >= GV100_DISP) 2339 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2340 else 2341 if (disp->disp->object.oclass >= GF110_DISP) 2342 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2343 else 2344 crtcs = 0x3; 2345 2346 for (i = 0; i < fls(crtcs); i++) { 2347 if (!(crtcs & (1 << i))) 2348 continue; 2349 ret = nv50_head_create(dev, i); 2350 if (ret) 2351 goto out; 2352 } 2353 2354 /* create encoder/connector objects based on VBIOS DCB table */ 2355 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2356 connector = nouveau_connector_create(dev, dcbe); 2357 if (IS_ERR(connector)) 2358 continue; 2359 2360 if (dcbe->location == DCB_LOC_ON_CHIP) { 2361 switch (dcbe->type) { 2362 case DCB_OUTPUT_TMDS: 2363 case DCB_OUTPUT_LVDS: 2364 case DCB_OUTPUT_DP: 2365 ret = nv50_sor_create(connector, dcbe); 2366 break; 2367 case DCB_OUTPUT_ANALOG: 2368 ret = nv50_dac_create(connector, dcbe); 2369 break; 2370 default: 2371 ret = -ENODEV; 2372 break; 2373 } 2374 } else { 2375 ret = nv50_pior_create(connector, dcbe); 2376 } 2377 2378 if (ret) { 2379 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2380 dcbe->location, dcbe->type, 2381 ffs(dcbe->or) - 1, ret); 2382 ret = 0; 2383 } 2384 } 2385 2386 /* cull any connectors we created that don't have an encoder */ 2387 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2388 if (connector->encoder_ids[0]) 2389 continue; 2390 2391 NV_WARN(drm, "%s has no encoders, removing\n", 2392 connector->name); 2393 connector->funcs->destroy(connector); 2394 } 2395 2396 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2397 dev->vblank_disable_immediate = true; 2398 2399 out: 2400 if (ret) 2401 nv50_display_destroy(dev); 2402 return ret; 2403 } 2404