1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 #include <linux/iopoll.h> 35 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_dp_helper.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_scdc_helper.h> 44 #include <drm/drm_vblank.h> 45 46 #include <nvif/push507c.h> 47 48 #include <nvif/class.h> 49 #include <nvif/cl0002.h> 50 #include <nvif/cl5070.h> 51 #include <nvif/cl507d.h> 52 #include <nvif/event.h> 53 #include <nvif/timer.h> 54 55 #include <nvhw/class/cl507c.h> 56 #include <nvhw/class/cl507d.h> 57 #include <nvhw/class/cl837d.h> 58 #include <nvhw/class/cl887d.h> 59 #include <nvhw/class/cl907d.h> 60 #include <nvhw/class/cl917d.h> 61 62 #include "nouveau_drv.h" 63 #include "nouveau_dma.h" 64 #include "nouveau_gem.h" 65 #include "nouveau_connector.h" 66 #include "nouveau_encoder.h" 67 #include "nouveau_fence.h" 68 #include "nouveau_fbcon.h" 69 70 #include <subdev/bios/dp.h> 71 72 /****************************************************************************** 73 * EVO channel 74 *****************************************************************************/ 75 76 static int 77 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 78 const s32 *oclass, u8 head, void *data, u32 size, 79 struct nv50_chan *chan) 80 { 81 struct nvif_sclass *sclass; 82 int ret, i, n; 83 84 chan->device = device; 85 86 ret = n = nvif_object_sclass_get(disp, &sclass); 87 if (ret < 0) 88 return ret; 89 90 while (oclass[0]) { 91 for (i = 0; i < n; i++) { 92 if (sclass[i].oclass == oclass[0]) { 93 ret = nvif_object_ctor(disp, "kmsChan", 0, 94 oclass[0], data, size, 95 &chan->user); 96 if (ret == 0) 97 nvif_object_map(&chan->user, NULL, 0); 98 nvif_object_sclass_put(&sclass); 99 return ret; 100 } 101 } 102 oclass++; 103 } 104 105 nvif_object_sclass_put(&sclass); 106 return -ENOSYS; 107 } 108 109 static void 110 nv50_chan_destroy(struct nv50_chan *chan) 111 { 112 nvif_object_dtor(&chan->user); 113 } 114 115 /****************************************************************************** 116 * DMA EVO channel 117 *****************************************************************************/ 118 119 void 120 nv50_dmac_destroy(struct nv50_dmac *dmac) 121 { 122 nvif_object_dtor(&dmac->vram); 123 nvif_object_dtor(&dmac->sync); 124 125 nv50_chan_destroy(&dmac->base); 126 127 nvif_mem_dtor(&dmac->_push.mem); 128 } 129 130 static void 131 nv50_dmac_kick(struct nvif_push *push) 132 { 133 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 134 135 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 136 if (dmac->put != dmac->cur) { 137 /* Push buffer fetches are not coherent with BAR1, we need to ensure 138 * writes have been flushed right through to VRAM before writing PUT. 139 */ 140 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 141 struct nvif_device *device = dmac->base.device; 142 nvif_wr32(&device->object, 0x070000, 0x00000001); 143 nvif_msec(device, 2000, 144 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 145 break; 146 ); 147 } 148 149 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 150 dmac->put = dmac->cur; 151 } 152 153 push->bgn = push->cur; 154 } 155 156 static int 157 nv50_dmac_free(struct nv50_dmac *dmac) 158 { 159 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 160 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 161 return get - dmac->cur - 5; 162 return dmac->max - dmac->cur; 163 } 164 165 static int 166 nv50_dmac_wind(struct nv50_dmac *dmac) 167 { 168 /* Wait for GET to depart from the beginning of the push buffer to 169 * prevent writing PUT == GET, which would be ignored by HW. 170 */ 171 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 172 if (get == 0) { 173 /* Corner-case, HW idle, but non-committed work pending. */ 174 if (dmac->put == 0) 175 nv50_dmac_kick(dmac->push); 176 177 if (nvif_msec(dmac->base.device, 2000, 178 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 179 break; 180 ) < 0) 181 return -ETIMEDOUT; 182 } 183 184 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 185 dmac->cur = 0; 186 return 0; 187 } 188 189 static int 190 nv50_dmac_wait(struct nvif_push *push, u32 size) 191 { 192 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 193 int free; 194 195 if (WARN_ON(size > dmac->max)) 196 return -EINVAL; 197 198 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 199 if (dmac->cur + size >= dmac->max) { 200 int ret = nv50_dmac_wind(dmac); 201 if (ret) 202 return ret; 203 204 push->cur = dmac->_push.mem.object.map.ptr; 205 push->cur = push->cur + dmac->cur; 206 nv50_dmac_kick(push); 207 } 208 209 if (nvif_msec(dmac->base.device, 2000, 210 if ((free = nv50_dmac_free(dmac)) >= size) 211 break; 212 ) < 0) { 213 WARN_ON(1); 214 return -ETIMEDOUT; 215 } 216 217 push->bgn = dmac->_push.mem.object.map.ptr; 218 push->bgn = push->bgn + dmac->cur; 219 push->cur = push->bgn; 220 push->end = push->cur + free; 221 return 0; 222 } 223 224 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)"); 225 static int nv50_dmac_vram_pushbuf = -1; 226 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400); 227 228 int 229 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 230 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf, 231 struct nv50_dmac *dmac) 232 { 233 struct nouveau_cli *cli = (void *)device->object.client; 234 struct nv50_disp_core_channel_dma_v0 *args = data; 235 u8 type = NVIF_MEM_COHERENT; 236 int ret; 237 238 mutex_init(&dmac->lock); 239 240 /* Pascal added support for 47-bit physical addresses, but some 241 * parts of EVO still only accept 40-bit PAs. 242 * 243 * To avoid issues on systems with large amounts of RAM, and on 244 * systems where an IOMMU maps pages at a high address, we need 245 * to allocate push buffers in VRAM instead. 246 * 247 * This appears to match NVIDIA's behaviour on Pascal. 248 */ 249 if ((nv50_dmac_vram_pushbuf > 0) || 250 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) 251 type |= NVIF_MEM_VRAM; 252 253 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 254 &dmac->_push.mem); 255 if (ret) 256 return ret; 257 258 dmac->ptr = dmac->_push.mem.object.map.ptr; 259 dmac->_push.wait = nv50_dmac_wait; 260 dmac->_push.kick = nv50_dmac_kick; 261 dmac->push = &dmac->_push; 262 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 263 dmac->push->cur = dmac->push->bgn; 264 dmac->push->end = dmac->push->bgn; 265 dmac->max = 0x1000/4 - 1; 266 267 /* EVO channels are affected by a HW bug where the last 12 DWORDs 268 * of the push buffer aren't able to be used safely. 269 */ 270 if (disp->oclass < GV100_DISP) 271 dmac->max -= 12; 272 273 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 274 275 ret = nv50_chan_create(device, disp, oclass, head, data, size, 276 &dmac->base); 277 if (ret) 278 return ret; 279 280 if (syncbuf < 0) 281 return 0; 282 283 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 284 NV_DMA_IN_MEMORY, 285 &(struct nv_dma_v0) { 286 .target = NV_DMA_V0_TARGET_VRAM, 287 .access = NV_DMA_V0_ACCESS_RDWR, 288 .start = syncbuf + 0x0000, 289 .limit = syncbuf + 0x0fff, 290 }, sizeof(struct nv_dma_v0), 291 &dmac->sync); 292 if (ret) 293 return ret; 294 295 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 296 NV_DMA_IN_MEMORY, 297 &(struct nv_dma_v0) { 298 .target = NV_DMA_V0_TARGET_VRAM, 299 .access = NV_DMA_V0_ACCESS_RDWR, 300 .start = 0, 301 .limit = device->info.ram_user - 1, 302 }, sizeof(struct nv_dma_v0), 303 &dmac->vram); 304 if (ret) 305 return ret; 306 307 return ret; 308 } 309 310 /****************************************************************************** 311 * Output path helpers 312 *****************************************************************************/ 313 static void 314 nv50_outp_dump_caps(struct nouveau_drm *drm, 315 struct nouveau_encoder *outp) 316 { 317 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n", 318 outp->base.base.name, outp->caps.dp_interlace); 319 } 320 321 static void 322 nv50_outp_release(struct nouveau_encoder *nv_encoder) 323 { 324 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 325 struct { 326 struct nv50_disp_mthd_v1 base; 327 } args = { 328 .base.version = 1, 329 .base.method = NV50_DISP_MTHD_V1_RELEASE, 330 .base.hasht = nv_encoder->dcb->hasht, 331 .base.hashm = nv_encoder->dcb->hashm, 332 }; 333 334 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 335 nv_encoder->or = -1; 336 nv_encoder->link = 0; 337 } 338 339 static int 340 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 341 { 342 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 343 struct nv50_disp *disp = nv50_disp(drm->dev); 344 struct { 345 struct nv50_disp_mthd_v1 base; 346 struct nv50_disp_acquire_v0 info; 347 } args = { 348 .base.version = 1, 349 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 350 .base.hasht = nv_encoder->dcb->hasht, 351 .base.hashm = nv_encoder->dcb->hashm, 352 .info.hda = hda, 353 }; 354 int ret; 355 356 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 357 if (ret) { 358 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 359 return ret; 360 } 361 362 nv_encoder->or = args.info.or; 363 nv_encoder->link = args.info.link; 364 return 0; 365 } 366 367 static int 368 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 369 struct drm_crtc_state *crtc_state, 370 struct drm_connector_state *conn_state, 371 struct drm_display_mode *native_mode) 372 { 373 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 374 struct drm_display_mode *mode = &crtc_state->mode; 375 struct drm_connector *connector = conn_state->connector; 376 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 377 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 378 379 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 380 asyc->scaler.full = false; 381 if (!native_mode) 382 return 0; 383 384 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 385 switch (connector->connector_type) { 386 case DRM_MODE_CONNECTOR_LVDS: 387 case DRM_MODE_CONNECTOR_eDP: 388 /* Don't force scaler for EDID modes with 389 * same size as the native one (e.g. different 390 * refresh rate) 391 */ 392 if (mode->hdisplay == native_mode->hdisplay && 393 mode->vdisplay == native_mode->vdisplay && 394 mode->type & DRM_MODE_TYPE_DRIVER) 395 break; 396 mode = native_mode; 397 asyc->scaler.full = true; 398 break; 399 default: 400 break; 401 } 402 } else { 403 mode = native_mode; 404 } 405 406 if (!drm_mode_equal(adjusted_mode, mode)) { 407 drm_mode_copy(adjusted_mode, mode); 408 crtc_state->mode_changed = true; 409 } 410 411 return 0; 412 } 413 414 static int 415 nv50_outp_atomic_check(struct drm_encoder *encoder, 416 struct drm_crtc_state *crtc_state, 417 struct drm_connector_state *conn_state) 418 { 419 struct drm_connector *connector = conn_state->connector; 420 struct nouveau_connector *nv_connector = nouveau_connector(connector); 421 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 422 int ret; 423 424 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 425 nv_connector->native_mode); 426 if (ret) 427 return ret; 428 429 if (crtc_state->mode_changed || crtc_state->connectors_changed) 430 asyh->or.bpc = connector->display_info.bpc; 431 432 return 0; 433 } 434 435 struct nouveau_connector * 436 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 437 { 438 struct drm_connector *connector; 439 struct drm_connector_state *connector_state; 440 struct drm_encoder *encoder = to_drm_encoder(outp); 441 int i; 442 443 for_each_new_connector_in_state(state, connector, connector_state, i) { 444 if (connector_state->best_encoder == encoder) 445 return nouveau_connector(connector); 446 } 447 448 return NULL; 449 } 450 451 struct nouveau_connector * 452 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 453 { 454 struct drm_connector *connector; 455 struct drm_connector_state *connector_state; 456 struct drm_encoder *encoder = to_drm_encoder(outp); 457 int i; 458 459 for_each_old_connector_in_state(state, connector, connector_state, i) { 460 if (connector_state->best_encoder == encoder) 461 return nouveau_connector(connector); 462 } 463 464 return NULL; 465 } 466 467 static struct nouveau_crtc * 468 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp) 469 { 470 struct drm_crtc *crtc; 471 struct drm_crtc_state *crtc_state; 472 const u32 mask = drm_encoder_mask(&outp->base.base); 473 int i; 474 475 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 476 if (crtc_state->encoder_mask & mask) 477 return nouveau_crtc(crtc); 478 } 479 480 return NULL; 481 } 482 483 /****************************************************************************** 484 * DAC 485 *****************************************************************************/ 486 static void 487 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 488 { 489 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 490 struct nv50_core *core = nv50_disp(encoder->dev)->core; 491 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 492 493 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); 494 nv_encoder->crtc = NULL; 495 nv50_outp_release(nv_encoder); 496 } 497 498 static void 499 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 500 { 501 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 502 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 503 struct nv50_head_atom *asyh = 504 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 505 struct nv50_core *core = nv50_disp(encoder->dev)->core; 506 u32 ctrl = 0; 507 508 switch (nv_crtc->index) { 509 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 510 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 511 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 512 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 513 default: 514 WARN_ON(1); 515 break; 516 } 517 518 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 519 520 nv50_outp_acquire(nv_encoder, false); 521 522 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); 523 asyh->or.depth = 0; 524 525 nv_encoder->crtc = &nv_crtc->base; 526 } 527 528 static enum drm_connector_status 529 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 530 { 531 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 532 struct nv50_disp *disp = nv50_disp(encoder->dev); 533 struct { 534 struct nv50_disp_mthd_v1 base; 535 struct nv50_disp_dac_load_v0 load; 536 } args = { 537 .base.version = 1, 538 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 539 .base.hasht = nv_encoder->dcb->hasht, 540 .base.hashm = nv_encoder->dcb->hashm, 541 }; 542 int ret; 543 544 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 545 if (args.load.data == 0) 546 args.load.data = 340; 547 548 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 549 if (ret || !args.load.load) 550 return connector_status_disconnected; 551 552 return connector_status_connected; 553 } 554 555 static const struct drm_encoder_helper_funcs 556 nv50_dac_help = { 557 .atomic_check = nv50_outp_atomic_check, 558 .atomic_enable = nv50_dac_atomic_enable, 559 .atomic_disable = nv50_dac_atomic_disable, 560 .detect = nv50_dac_detect 561 }; 562 563 static void 564 nv50_dac_destroy(struct drm_encoder *encoder) 565 { 566 drm_encoder_cleanup(encoder); 567 kfree(encoder); 568 } 569 570 static const struct drm_encoder_funcs 571 nv50_dac_func = { 572 .destroy = nv50_dac_destroy, 573 }; 574 575 static int 576 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 577 { 578 struct nouveau_drm *drm = nouveau_drm(connector->dev); 579 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 580 struct nvkm_i2c_bus *bus; 581 struct nouveau_encoder *nv_encoder; 582 struct drm_encoder *encoder; 583 int type = DRM_MODE_ENCODER_DAC; 584 585 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 586 if (!nv_encoder) 587 return -ENOMEM; 588 nv_encoder->dcb = dcbe; 589 590 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 591 if (bus) 592 nv_encoder->i2c = &bus->i2c; 593 594 encoder = to_drm_encoder(nv_encoder); 595 encoder->possible_crtcs = dcbe->heads; 596 encoder->possible_clones = 0; 597 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 598 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 599 drm_encoder_helper_add(encoder, &nv50_dac_help); 600 601 drm_connector_attach_encoder(connector, encoder); 602 return 0; 603 } 604 605 /* 606 * audio component binding for ELD notification 607 */ 608 static void 609 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 610 int dev_id) 611 { 612 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 613 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 614 port, dev_id); 615 } 616 617 static int 618 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 619 bool *enabled, unsigned char *buf, int max_bytes) 620 { 621 struct drm_device *drm_dev = dev_get_drvdata(kdev); 622 struct nouveau_drm *drm = nouveau_drm(drm_dev); 623 struct drm_encoder *encoder; 624 struct nouveau_encoder *nv_encoder; 625 struct nouveau_crtc *nv_crtc; 626 int ret = 0; 627 628 *enabled = false; 629 630 mutex_lock(&drm->audio.lock); 631 632 drm_for_each_encoder(encoder, drm->dev) { 633 struct nouveau_connector *nv_connector = NULL; 634 635 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) 636 continue; /* TODO */ 637 638 nv_encoder = nouveau_encoder(encoder); 639 nv_connector = nouveau_connector(nv_encoder->audio.connector); 640 nv_crtc = nouveau_crtc(nv_encoder->crtc); 641 642 if (!nv_crtc || nv_encoder->or != port || nv_crtc->index != dev_id) 643 continue; 644 645 *enabled = nv_encoder->audio.enabled; 646 if (*enabled) { 647 ret = drm_eld_size(nv_connector->base.eld); 648 memcpy(buf, nv_connector->base.eld, 649 min(max_bytes, ret)); 650 } 651 break; 652 } 653 654 mutex_unlock(&drm->audio.lock); 655 656 return ret; 657 } 658 659 static const struct drm_audio_component_ops nv50_audio_component_ops = { 660 .get_eld = nv50_audio_component_get_eld, 661 }; 662 663 static int 664 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 665 void *data) 666 { 667 struct drm_device *drm_dev = dev_get_drvdata(kdev); 668 struct nouveau_drm *drm = nouveau_drm(drm_dev); 669 struct drm_audio_component *acomp = data; 670 671 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 672 return -ENOMEM; 673 674 drm_modeset_lock_all(drm_dev); 675 acomp->ops = &nv50_audio_component_ops; 676 acomp->dev = kdev; 677 drm->audio.component = acomp; 678 drm_modeset_unlock_all(drm_dev); 679 return 0; 680 } 681 682 static void 683 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 684 void *data) 685 { 686 struct drm_device *drm_dev = dev_get_drvdata(kdev); 687 struct nouveau_drm *drm = nouveau_drm(drm_dev); 688 struct drm_audio_component *acomp = data; 689 690 drm_modeset_lock_all(drm_dev); 691 drm->audio.component = NULL; 692 acomp->ops = NULL; 693 acomp->dev = NULL; 694 drm_modeset_unlock_all(drm_dev); 695 } 696 697 static const struct component_ops nv50_audio_component_bind_ops = { 698 .bind = nv50_audio_component_bind, 699 .unbind = nv50_audio_component_unbind, 700 }; 701 702 static void 703 nv50_audio_component_init(struct nouveau_drm *drm) 704 { 705 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 706 return; 707 708 drm->audio.component_registered = true; 709 mutex_init(&drm->audio.lock); 710 } 711 712 static void 713 nv50_audio_component_fini(struct nouveau_drm *drm) 714 { 715 if (!drm->audio.component_registered) 716 return; 717 718 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 719 drm->audio.component_registered = false; 720 mutex_destroy(&drm->audio.lock); 721 } 722 723 /****************************************************************************** 724 * Audio 725 *****************************************************************************/ 726 static void 727 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 728 { 729 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 730 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 731 struct nv50_disp *disp = nv50_disp(encoder->dev); 732 struct { 733 struct nv50_disp_mthd_v1 base; 734 struct nv50_disp_sor_hda_eld_v0 eld; 735 } args = { 736 .base.version = 1, 737 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 738 .base.hasht = nv_encoder->dcb->hasht, 739 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 740 (0x0100 << nv_crtc->index), 741 }; 742 743 mutex_lock(&drm->audio.lock); 744 if (nv_encoder->audio.enabled) { 745 nv_encoder->audio.enabled = false; 746 nv_encoder->audio.connector = NULL; 747 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 748 } 749 mutex_unlock(&drm->audio.lock); 750 751 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 752 nv_crtc->index); 753 } 754 755 static void 756 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 757 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 758 struct drm_display_mode *mode) 759 { 760 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 761 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 762 struct nv50_disp *disp = nv50_disp(encoder->dev); 763 struct __packed { 764 struct { 765 struct nv50_disp_mthd_v1 mthd; 766 struct nv50_disp_sor_hda_eld_v0 eld; 767 } base; 768 u8 data[sizeof(nv_connector->base.eld)]; 769 } args = { 770 .base.mthd.version = 1, 771 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 772 .base.mthd.hasht = nv_encoder->dcb->hasht, 773 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 774 (0x0100 << nv_crtc->index), 775 }; 776 777 if (!drm_detect_monitor_audio(nv_connector->edid)) 778 return; 779 780 mutex_lock(&drm->audio.lock); 781 782 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 783 784 nvif_mthd(&disp->disp->object, 0, &args, 785 sizeof(args.base) + drm_eld_size(args.data)); 786 nv_encoder->audio.enabled = true; 787 nv_encoder->audio.connector = &nv_connector->base; 788 789 mutex_unlock(&drm->audio.lock); 790 791 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 792 nv_crtc->index); 793 } 794 795 /****************************************************************************** 796 * HDMI 797 *****************************************************************************/ 798 static void 799 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 800 { 801 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 802 struct nv50_disp *disp = nv50_disp(encoder->dev); 803 struct { 804 struct nv50_disp_mthd_v1 base; 805 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 806 } args = { 807 .base.version = 1, 808 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 809 .base.hasht = nv_encoder->dcb->hasht, 810 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 811 (0x0100 << nv_crtc->index), 812 }; 813 814 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 815 } 816 817 static void 818 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 819 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 820 struct drm_display_mode *mode) 821 { 822 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 823 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 824 struct nv50_disp *disp = nv50_disp(encoder->dev); 825 struct { 826 struct nv50_disp_mthd_v1 base; 827 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 828 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 829 } args = { 830 .base.version = 1, 831 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 832 .base.hasht = nv_encoder->dcb->hasht, 833 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 834 (0x0100 << nv_crtc->index), 835 .pwr.state = 1, 836 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 837 }; 838 struct drm_hdmi_info *hdmi; 839 u32 max_ac_packet; 840 union hdmi_infoframe avi_frame; 841 union hdmi_infoframe vendor_frame; 842 bool high_tmds_clock_ratio = false, scrambling = false; 843 u8 config; 844 int ret; 845 int size; 846 847 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 848 return; 849 850 hdmi = &nv_connector->base.display_info.hdmi; 851 852 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 853 &nv_connector->base, mode); 854 if (!ret) { 855 drm_hdmi_avi_infoframe_quant_range(&avi_frame.avi, 856 &nv_connector->base, mode, 857 HDMI_QUANTIZATION_RANGE_FULL); 858 /* We have an AVI InfoFrame, populate it to the display */ 859 args.pwr.avi_infoframe_length 860 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 861 } 862 863 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 864 &nv_connector->base, mode); 865 if (!ret) { 866 /* We have a Vendor InfoFrame, populate it to the display */ 867 args.pwr.vendor_infoframe_length 868 = hdmi_infoframe_pack(&vendor_frame, 869 args.infoframes 870 + args.pwr.avi_infoframe_length, 871 17); 872 } 873 874 max_ac_packet = mode->htotal - mode->hdisplay; 875 max_ac_packet -= args.pwr.rekey; 876 max_ac_packet -= 18; /* constant from tegra */ 877 args.pwr.max_ac_packet = max_ac_packet / 32; 878 879 if (hdmi->scdc.scrambling.supported) { 880 high_tmds_clock_ratio = mode->clock > 340000; 881 scrambling = high_tmds_clock_ratio || 882 hdmi->scdc.scrambling.low_rates; 883 } 884 885 args.pwr.scdc = 886 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 887 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 888 889 size = sizeof(args.base) 890 + sizeof(args.pwr) 891 + args.pwr.avi_infoframe_length 892 + args.pwr.vendor_infoframe_length; 893 nvif_mthd(&disp->disp->object, 0, &args, size); 894 895 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 896 897 /* If SCDC is supported by the downstream monitor, update 898 * divider / scrambling settings to what we programmed above. 899 */ 900 if (!hdmi->scdc.scrambling.supported) 901 return; 902 903 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 904 if (ret < 0) { 905 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 906 return; 907 } 908 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 909 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 910 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 911 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 912 if (ret < 0) 913 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 914 config, ret); 915 } 916 917 /****************************************************************************** 918 * MST 919 *****************************************************************************/ 920 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 921 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 922 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 923 924 struct nv50_mstc { 925 struct nv50_mstm *mstm; 926 struct drm_dp_mst_port *port; 927 struct drm_connector connector; 928 929 struct drm_display_mode *native; 930 struct edid *edid; 931 }; 932 933 struct nv50_msto { 934 struct drm_encoder encoder; 935 936 /* head is statically assigned on msto creation */ 937 struct nv50_head *head; 938 struct nv50_mstc *mstc; 939 bool disabled; 940 }; 941 942 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 943 { 944 struct nv50_msto *msto; 945 946 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 947 return nouveau_encoder(encoder); 948 949 msto = nv50_msto(encoder); 950 if (!msto->mstc) 951 return NULL; 952 return msto->mstc->mstm->outp; 953 } 954 955 static struct drm_dp_payload * 956 nv50_msto_payload(struct nv50_msto *msto) 957 { 958 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 959 struct nv50_mstc *mstc = msto->mstc; 960 struct nv50_mstm *mstm = mstc->mstm; 961 int vcpi = mstc->port->vcpi.vcpi, i; 962 963 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 964 965 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 966 for (i = 0; i < mstm->mgr.max_payloads; i++) { 967 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 968 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 969 mstm->outp->base.base.name, i, payload->vcpi, 970 payload->start_slot, payload->num_slots); 971 } 972 973 for (i = 0; i < mstm->mgr.max_payloads; i++) { 974 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 975 if (payload->vcpi == vcpi) 976 return payload; 977 } 978 979 return NULL; 980 } 981 982 static void 983 nv50_msto_cleanup(struct nv50_msto *msto) 984 { 985 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 986 struct nv50_mstc *mstc = msto->mstc; 987 struct nv50_mstm *mstm = mstc->mstm; 988 989 if (!msto->disabled) 990 return; 991 992 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 993 994 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 995 996 msto->mstc = NULL; 997 msto->disabled = false; 998 } 999 1000 static void 1001 nv50_msto_prepare(struct nv50_msto *msto) 1002 { 1003 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 1004 struct nv50_mstc *mstc = msto->mstc; 1005 struct nv50_mstm *mstm = mstc->mstm; 1006 struct { 1007 struct nv50_disp_mthd_v1 base; 1008 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 1009 } args = { 1010 .base.version = 1, 1011 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 1012 .base.hasht = mstm->outp->dcb->hasht, 1013 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 1014 (0x0100 << msto->head->base.index), 1015 }; 1016 1017 mutex_lock(&mstm->mgr.payload_lock); 1018 1019 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 1020 if (mstc->port->vcpi.vcpi > 0) { 1021 struct drm_dp_payload *payload = nv50_msto_payload(msto); 1022 if (payload) { 1023 args.vcpi.start_slot = payload->start_slot; 1024 args.vcpi.num_slots = payload->num_slots; 1025 args.vcpi.pbn = mstc->port->vcpi.pbn; 1026 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 1027 } 1028 } 1029 1030 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 1031 msto->encoder.name, msto->head->base.base.name, 1032 args.vcpi.start_slot, args.vcpi.num_slots, 1033 args.vcpi.pbn, args.vcpi.aligned_pbn); 1034 1035 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 1036 mutex_unlock(&mstm->mgr.payload_lock); 1037 } 1038 1039 static int 1040 nv50_msto_atomic_check(struct drm_encoder *encoder, 1041 struct drm_crtc_state *crtc_state, 1042 struct drm_connector_state *conn_state) 1043 { 1044 struct drm_atomic_state *state = crtc_state->state; 1045 struct drm_connector *connector = conn_state->connector; 1046 struct nv50_mstc *mstc = nv50_mstc(connector); 1047 struct nv50_mstm *mstm = mstc->mstm; 1048 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 1049 int slots; 1050 int ret; 1051 1052 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 1053 mstc->native); 1054 if (ret) 1055 return ret; 1056 1057 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 1058 return 0; 1059 1060 /* 1061 * When restoring duplicated states, we need to make sure that the bw 1062 * remains the same and avoid recalculating it, as the connector's bpc 1063 * may have changed after the state was duplicated 1064 */ 1065 if (!state->duplicated) { 1066 const int clock = crtc_state->adjusted_mode.clock; 1067 1068 asyh->or.bpc = connector->display_info.bpc; 1069 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 1070 false); 1071 } 1072 1073 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 1074 asyh->dp.pbn, 0); 1075 if (slots < 0) 1076 return slots; 1077 1078 asyh->dp.tu = slots; 1079 1080 return 0; 1081 } 1082 1083 static u8 1084 nv50_dp_bpc_to_depth(unsigned int bpc) 1085 { 1086 switch (bpc) { 1087 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1088 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1089 case 10: 1090 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1091 } 1092 } 1093 1094 static void 1095 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1096 { 1097 struct nv50_msto *msto = nv50_msto(encoder); 1098 struct nv50_head *head = msto->head; 1099 struct nv50_head_atom *asyh = 1100 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base)); 1101 struct nv50_mstc *mstc = NULL; 1102 struct nv50_mstm *mstm = NULL; 1103 struct drm_connector *connector; 1104 struct drm_connector_list_iter conn_iter; 1105 u8 proto; 1106 bool r; 1107 1108 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1109 drm_for_each_connector_iter(connector, &conn_iter) { 1110 if (connector->state->best_encoder == &msto->encoder) { 1111 mstc = nv50_mstc(connector); 1112 mstm = mstc->mstm; 1113 break; 1114 } 1115 } 1116 drm_connector_list_iter_end(&conn_iter); 1117 1118 if (WARN_ON(!mstc)) 1119 return; 1120 1121 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, asyh->dp.pbn, asyh->dp.tu); 1122 if (!r) 1123 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 1124 1125 if (!mstm->links++) 1126 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 1127 1128 if (mstm->outp->link & 1) 1129 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1130 else 1131 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1132 1133 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, 1134 nv50_dp_bpc_to_depth(asyh->or.bpc)); 1135 1136 msto->mstc = mstc; 1137 mstm->modified = true; 1138 } 1139 1140 static void 1141 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1142 { 1143 struct nv50_msto *msto = nv50_msto(encoder); 1144 struct nv50_mstc *mstc = msto->mstc; 1145 struct nv50_mstm *mstm = mstc->mstm; 1146 1147 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 1148 1149 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1150 mstm->modified = true; 1151 if (!--mstm->links) 1152 mstm->disabled = true; 1153 msto->disabled = true; 1154 } 1155 1156 static const struct drm_encoder_helper_funcs 1157 nv50_msto_help = { 1158 .atomic_disable = nv50_msto_atomic_disable, 1159 .atomic_enable = nv50_msto_atomic_enable, 1160 .atomic_check = nv50_msto_atomic_check, 1161 }; 1162 1163 static void 1164 nv50_msto_destroy(struct drm_encoder *encoder) 1165 { 1166 struct nv50_msto *msto = nv50_msto(encoder); 1167 drm_encoder_cleanup(&msto->encoder); 1168 kfree(msto); 1169 } 1170 1171 static const struct drm_encoder_funcs 1172 nv50_msto = { 1173 .destroy = nv50_msto_destroy, 1174 }; 1175 1176 static struct nv50_msto * 1177 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1178 { 1179 struct nv50_msto *msto; 1180 int ret; 1181 1182 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1183 if (!msto) 1184 return ERR_PTR(-ENOMEM); 1185 1186 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1187 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1188 if (ret) { 1189 kfree(msto); 1190 return ERR_PTR(ret); 1191 } 1192 1193 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1194 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1195 msto->head = head; 1196 return msto; 1197 } 1198 1199 static struct drm_encoder * 1200 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1201 struct drm_atomic_state *state) 1202 { 1203 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1204 connector); 1205 struct nv50_mstc *mstc = nv50_mstc(connector); 1206 struct drm_crtc *crtc = connector_state->crtc; 1207 1208 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1209 return NULL; 1210 1211 return &nv50_head(crtc)->msto->encoder; 1212 } 1213 1214 static enum drm_mode_status 1215 nv50_mstc_mode_valid(struct drm_connector *connector, 1216 struct drm_display_mode *mode) 1217 { 1218 struct nv50_mstc *mstc = nv50_mstc(connector); 1219 struct nouveau_encoder *outp = mstc->mstm->outp; 1220 1221 /* TODO: calculate the PBN from the dotclock and validate against the 1222 * MSTB's max possible PBN 1223 */ 1224 1225 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1226 } 1227 1228 static int 1229 nv50_mstc_get_modes(struct drm_connector *connector) 1230 { 1231 struct nv50_mstc *mstc = nv50_mstc(connector); 1232 int ret = 0; 1233 1234 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1235 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1236 if (mstc->edid) 1237 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1238 1239 /* 1240 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1241 * to 8 to save bandwidth on the topology. In the future, we'll want 1242 * to properly fix this by dynamically selecting the highest possible 1243 * bpc that would fit in the topology 1244 */ 1245 if (connector->display_info.bpc) 1246 connector->display_info.bpc = 1247 clamp(connector->display_info.bpc, 6U, 8U); 1248 else 1249 connector->display_info.bpc = 8; 1250 1251 if (mstc->native) 1252 drm_mode_destroy(mstc->connector.dev, mstc->native); 1253 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1254 return ret; 1255 } 1256 1257 static int 1258 nv50_mstc_atomic_check(struct drm_connector *connector, 1259 struct drm_atomic_state *state) 1260 { 1261 struct nv50_mstc *mstc = nv50_mstc(connector); 1262 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1263 struct drm_connector_state *new_conn_state = 1264 drm_atomic_get_new_connector_state(state, connector); 1265 struct drm_connector_state *old_conn_state = 1266 drm_atomic_get_old_connector_state(state, connector); 1267 struct drm_crtc_state *crtc_state; 1268 struct drm_crtc *new_crtc = new_conn_state->crtc; 1269 1270 if (!old_conn_state->crtc) 1271 return 0; 1272 1273 /* We only want to free VCPI if this state disables the CRTC on this 1274 * connector 1275 */ 1276 if (new_crtc) { 1277 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1278 1279 if (!crtc_state || 1280 !drm_atomic_crtc_needs_modeset(crtc_state) || 1281 crtc_state->enable) 1282 return 0; 1283 } 1284 1285 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1286 } 1287 1288 static int 1289 nv50_mstc_detect(struct drm_connector *connector, 1290 struct drm_modeset_acquire_ctx *ctx, bool force) 1291 { 1292 struct nv50_mstc *mstc = nv50_mstc(connector); 1293 int ret; 1294 1295 if (drm_connector_is_unregistered(connector)) 1296 return connector_status_disconnected; 1297 1298 ret = pm_runtime_get_sync(connector->dev->dev); 1299 if (ret < 0 && ret != -EACCES) { 1300 pm_runtime_put_autosuspend(connector->dev->dev); 1301 return connector_status_disconnected; 1302 } 1303 1304 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1305 mstc->port); 1306 if (ret != connector_status_connected) 1307 goto out; 1308 1309 out: 1310 pm_runtime_mark_last_busy(connector->dev->dev); 1311 pm_runtime_put_autosuspend(connector->dev->dev); 1312 return ret; 1313 } 1314 1315 static const struct drm_connector_helper_funcs 1316 nv50_mstc_help = { 1317 .get_modes = nv50_mstc_get_modes, 1318 .mode_valid = nv50_mstc_mode_valid, 1319 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1320 .atomic_check = nv50_mstc_atomic_check, 1321 .detect_ctx = nv50_mstc_detect, 1322 }; 1323 1324 static void 1325 nv50_mstc_destroy(struct drm_connector *connector) 1326 { 1327 struct nv50_mstc *mstc = nv50_mstc(connector); 1328 1329 drm_connector_cleanup(&mstc->connector); 1330 drm_dp_mst_put_port_malloc(mstc->port); 1331 1332 kfree(mstc); 1333 } 1334 1335 static const struct drm_connector_funcs 1336 nv50_mstc = { 1337 .reset = nouveau_conn_reset, 1338 .fill_modes = drm_helper_probe_single_connector_modes, 1339 .destroy = nv50_mstc_destroy, 1340 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1341 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1342 .atomic_set_property = nouveau_conn_atomic_set_property, 1343 .atomic_get_property = nouveau_conn_atomic_get_property, 1344 }; 1345 1346 static int 1347 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1348 const char *path, struct nv50_mstc **pmstc) 1349 { 1350 struct drm_device *dev = mstm->outp->base.base.dev; 1351 struct drm_crtc *crtc; 1352 struct nv50_mstc *mstc; 1353 int ret; 1354 1355 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1356 return -ENOMEM; 1357 mstc->mstm = mstm; 1358 mstc->port = port; 1359 1360 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1361 DRM_MODE_CONNECTOR_DisplayPort); 1362 if (ret) { 1363 kfree(*pmstc); 1364 *pmstc = NULL; 1365 return ret; 1366 } 1367 1368 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1369 1370 mstc->connector.funcs->reset(&mstc->connector); 1371 nouveau_conn_attach_properties(&mstc->connector); 1372 1373 drm_for_each_crtc(crtc, dev) { 1374 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1375 continue; 1376 1377 drm_connector_attach_encoder(&mstc->connector, 1378 &nv50_head(crtc)->msto->encoder); 1379 } 1380 1381 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1382 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1383 drm_connector_set_path_property(&mstc->connector, path); 1384 drm_dp_mst_get_port_malloc(port); 1385 return 0; 1386 } 1387 1388 static void 1389 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1390 { 1391 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1392 struct drm_encoder *encoder; 1393 1394 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1395 drm_dp_check_act_status(&mstm->mgr); 1396 1397 drm_dp_update_payload_part2(&mstm->mgr); 1398 1399 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1400 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1401 struct nv50_msto *msto = nv50_msto(encoder); 1402 struct nv50_mstc *mstc = msto->mstc; 1403 if (mstc && mstc->mstm == mstm) 1404 nv50_msto_cleanup(msto); 1405 } 1406 } 1407 1408 mstm->modified = false; 1409 } 1410 1411 static void 1412 nv50_mstm_prepare(struct nv50_mstm *mstm) 1413 { 1414 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1415 struct drm_encoder *encoder; 1416 1417 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1418 drm_dp_update_payload_part1(&mstm->mgr, 1); 1419 1420 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1421 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1422 struct nv50_msto *msto = nv50_msto(encoder); 1423 struct nv50_mstc *mstc = msto->mstc; 1424 if (mstc && mstc->mstm == mstm) 1425 nv50_msto_prepare(msto); 1426 } 1427 } 1428 1429 if (mstm->disabled) { 1430 if (!mstm->links) 1431 nv50_outp_release(mstm->outp); 1432 mstm->disabled = false; 1433 } 1434 } 1435 1436 static struct drm_connector * 1437 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1438 struct drm_dp_mst_port *port, const char *path) 1439 { 1440 struct nv50_mstm *mstm = nv50_mstm(mgr); 1441 struct nv50_mstc *mstc; 1442 int ret; 1443 1444 ret = nv50_mstc_new(mstm, port, path, &mstc); 1445 if (ret) 1446 return NULL; 1447 1448 return &mstc->connector; 1449 } 1450 1451 static const struct drm_dp_mst_topology_cbs 1452 nv50_mstm = { 1453 .add_connector = nv50_mstm_add_connector, 1454 }; 1455 1456 bool 1457 nv50_mstm_service(struct nouveau_drm *drm, 1458 struct nouveau_connector *nv_connector, 1459 struct nv50_mstm *mstm) 1460 { 1461 struct drm_dp_aux *aux = &nv_connector->aux; 1462 bool handled = true, ret = true; 1463 int rc; 1464 u8 esi[8] = {}; 1465 1466 while (handled) { 1467 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1468 if (rc != 8) { 1469 ret = false; 1470 break; 1471 } 1472 1473 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1474 if (!handled) 1475 break; 1476 1477 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 1478 3); 1479 if (rc != 3) { 1480 ret = false; 1481 break; 1482 } 1483 } 1484 1485 if (!ret) 1486 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1487 nv_connector->base.name, rc); 1488 1489 return ret; 1490 } 1491 1492 void 1493 nv50_mstm_remove(struct nv50_mstm *mstm) 1494 { 1495 mstm->is_mst = false; 1496 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1497 } 1498 1499 static int 1500 nv50_mstm_enable(struct nv50_mstm *mstm, int state) 1501 { 1502 struct nouveau_encoder *outp = mstm->outp; 1503 struct { 1504 struct nv50_disp_mthd_v1 base; 1505 struct nv50_disp_sor_dp_mst_link_v0 mst; 1506 } args = { 1507 .base.version = 1, 1508 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1509 .base.hasht = outp->dcb->hasht, 1510 .base.hashm = outp->dcb->hashm, 1511 .mst.state = state, 1512 }; 1513 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1514 struct nvif_object *disp = &drm->display->disp.object; 1515 1516 return nvif_mthd(disp, 0, &args, sizeof(args)); 1517 } 1518 1519 int 1520 nv50_mstm_detect(struct nouveau_encoder *outp) 1521 { 1522 struct nv50_mstm *mstm = outp->dp.mstm; 1523 struct drm_dp_aux *aux; 1524 int ret; 1525 1526 if (!mstm || !mstm->can_mst) 1527 return 0; 1528 1529 aux = mstm->mgr.aux; 1530 1531 /* Clear any leftover MST state we didn't set ourselves by first 1532 * disabling MST if it was already enabled 1533 */ 1534 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1535 if (ret < 0) 1536 return ret; 1537 1538 /* And start enabling */ 1539 ret = nv50_mstm_enable(mstm, true); 1540 if (ret) 1541 return ret; 1542 1543 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1544 if (ret) { 1545 nv50_mstm_enable(mstm, false); 1546 return ret; 1547 } 1548 1549 mstm->is_mst = true; 1550 return 1; 1551 } 1552 1553 static void 1554 nv50_mstm_fini(struct nouveau_encoder *outp) 1555 { 1556 struct nv50_mstm *mstm = outp->dp.mstm; 1557 1558 if (!mstm) 1559 return; 1560 1561 /* Don't change the MST state of this connector until we've finished 1562 * resuming, since we can't safely grab hpd_irq_lock in our resume 1563 * path to protect mstm->is_mst without potentially deadlocking 1564 */ 1565 mutex_lock(&outp->dp.hpd_irq_lock); 1566 mstm->suspended = true; 1567 mutex_unlock(&outp->dp.hpd_irq_lock); 1568 1569 if (mstm->is_mst) 1570 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1571 } 1572 1573 static void 1574 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1575 { 1576 struct nv50_mstm *mstm = outp->dp.mstm; 1577 int ret = 0; 1578 1579 if (!mstm) 1580 return; 1581 1582 if (mstm->is_mst) { 1583 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1584 if (ret == -1) 1585 nv50_mstm_remove(mstm); 1586 } 1587 1588 mutex_lock(&outp->dp.hpd_irq_lock); 1589 mstm->suspended = false; 1590 mutex_unlock(&outp->dp.hpd_irq_lock); 1591 1592 if (ret == -1) 1593 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1594 } 1595 1596 static void 1597 nv50_mstm_del(struct nv50_mstm **pmstm) 1598 { 1599 struct nv50_mstm *mstm = *pmstm; 1600 if (mstm) { 1601 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1602 kfree(*pmstm); 1603 *pmstm = NULL; 1604 } 1605 } 1606 1607 static int 1608 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1609 int conn_base_id, struct nv50_mstm **pmstm) 1610 { 1611 const int max_payloads = hweight8(outp->dcb->heads); 1612 struct drm_device *dev = outp->base.base.dev; 1613 struct nv50_mstm *mstm; 1614 int ret; 1615 1616 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1617 return -ENOMEM; 1618 mstm->outp = outp; 1619 mstm->mgr.cbs = &nv50_mstm; 1620 1621 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1622 max_payloads, outp->dcb->dpconf.link_nr, 1623 drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), 1624 conn_base_id); 1625 if (ret) 1626 return ret; 1627 1628 return 0; 1629 } 1630 1631 /****************************************************************************** 1632 * SOR 1633 *****************************************************************************/ 1634 static void 1635 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1636 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1637 { 1638 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1639 struct nv50_core *core = disp->core; 1640 1641 if (!asyh) { 1642 nv_encoder->ctrl &= ~BIT(head); 1643 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1644 nv_encoder->ctrl = 0; 1645 } else { 1646 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1647 nv_encoder->ctrl |= BIT(head); 1648 asyh->or.depth = depth; 1649 } 1650 1651 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1652 } 1653 1654 /* TODO: Should we extend this to PWM-only backlights? 1655 * As well, should we add a DRM helper for waiting for the backlight to acknowledge 1656 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a 1657 * fixed time delay from the vbios… 1658 */ 1659 static void 1660 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1661 { 1662 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1663 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1664 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder); 1665 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1666 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 1667 struct nouveau_backlight *backlight = nv_connector->backlight; 1668 #endif 1669 struct drm_dp_aux *aux = &nv_connector->aux; 1670 int ret; 1671 u8 pwr; 1672 1673 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1674 if (backlight && backlight->uses_dpcd) { 1675 ret = drm_edp_backlight_disable(aux, &backlight->edp_info); 1676 if (ret < 0) 1677 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n", 1678 nv_connector->base.base.id, nv_connector->base.name, ret); 1679 } 1680 #endif 1681 1682 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1683 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1684 1685 if (ret == 0) { 1686 pwr &= ~DP_SET_POWER_MASK; 1687 pwr |= DP_SET_POWER_D3; 1688 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1689 } 1690 } 1691 1692 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1693 nv50_audio_disable(encoder, nv_crtc); 1694 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1695 nv50_outp_release(nv_encoder); 1696 nv_encoder->crtc = NULL; 1697 } 1698 1699 static void 1700 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1701 { 1702 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1703 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1704 struct nv50_head_atom *asyh = 1705 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1706 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1707 struct { 1708 struct nv50_disp_mthd_v1 base; 1709 struct nv50_disp_sor_lvds_script_v0 lvds; 1710 } lvds = { 1711 .base.version = 1, 1712 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1713 .base.hasht = nv_encoder->dcb->hasht, 1714 .base.hashm = nv_encoder->dcb->hashm, 1715 }; 1716 struct nv50_disp *disp = nv50_disp(encoder->dev); 1717 struct drm_device *dev = encoder->dev; 1718 struct nouveau_drm *drm = nouveau_drm(dev); 1719 struct nouveau_connector *nv_connector; 1720 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1721 struct nouveau_backlight *backlight; 1722 #endif 1723 struct nvbios *bios = &drm->vbios; 1724 bool hda = false; 1725 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1726 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1727 1728 nv_connector = nv50_outp_get_new_connector(state, nv_encoder); 1729 nv_encoder->crtc = &nv_crtc->base; 1730 1731 if ((disp->disp->object.oclass == GT214_DISP || 1732 disp->disp->object.oclass >= GF110_DISP) && 1733 drm_detect_monitor_audio(nv_connector->edid)) 1734 hda = true; 1735 nv50_outp_acquire(nv_encoder, hda); 1736 1737 switch (nv_encoder->dcb->type) { 1738 case DCB_OUTPUT_TMDS: 1739 if (nv_encoder->link & 1) { 1740 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1741 /* Only enable dual-link if: 1742 * - Need to (i.e. rate > 165MHz) 1743 * - DCB says we can 1744 * - Not an HDMI monitor, since there's no dual-link 1745 * on HDMI. 1746 */ 1747 if (mode->clock >= 165000 && 1748 nv_encoder->dcb->duallink_possible && 1749 !drm_detect_hdmi_monitor(nv_connector->edid)) 1750 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1751 } else { 1752 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1753 } 1754 1755 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode); 1756 break; 1757 case DCB_OUTPUT_LVDS: 1758 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1759 1760 if (bios->fp_no_ddc) { 1761 if (bios->fp.dual_link) 1762 lvds.lvds.script |= 0x0100; 1763 if (bios->fp.if_is_24bit) 1764 lvds.lvds.script |= 0x0200; 1765 } else { 1766 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1767 if (((u8 *)nv_connector->edid)[121] == 2) 1768 lvds.lvds.script |= 0x0100; 1769 } else 1770 if (mode->clock >= bios->fp.duallink_transition_clk) { 1771 lvds.lvds.script |= 0x0100; 1772 } 1773 1774 if (lvds.lvds.script & 0x0100) { 1775 if (bios->fp.strapless_is_24bit & 2) 1776 lvds.lvds.script |= 0x0200; 1777 } else { 1778 if (bios->fp.strapless_is_24bit & 1) 1779 lvds.lvds.script |= 0x0200; 1780 } 1781 1782 if (asyh->or.bpc == 8) 1783 lvds.lvds.script |= 0x0200; 1784 } 1785 1786 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1787 break; 1788 case DCB_OUTPUT_DP: 1789 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1790 1791 if (nv_encoder->link & 1) 1792 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1793 else 1794 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1795 1796 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 1797 1798 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1799 backlight = nv_connector->backlight; 1800 if (backlight && backlight->uses_dpcd) 1801 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info, 1802 (u16)backlight->dev->props.brightness); 1803 #endif 1804 1805 break; 1806 default: 1807 BUG(); 1808 break; 1809 } 1810 1811 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1812 } 1813 1814 static const struct drm_encoder_helper_funcs 1815 nv50_sor_help = { 1816 .atomic_check = nv50_outp_atomic_check, 1817 .atomic_enable = nv50_sor_atomic_enable, 1818 .atomic_disable = nv50_sor_atomic_disable, 1819 }; 1820 1821 static void 1822 nv50_sor_destroy(struct drm_encoder *encoder) 1823 { 1824 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1825 nv50_mstm_del(&nv_encoder->dp.mstm); 1826 drm_encoder_cleanup(encoder); 1827 1828 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1829 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1830 1831 kfree(encoder); 1832 } 1833 1834 static const struct drm_encoder_funcs 1835 nv50_sor_func = { 1836 .destroy = nv50_sor_destroy, 1837 }; 1838 1839 static bool nv50_has_mst(struct nouveau_drm *drm) 1840 { 1841 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1842 u32 data; 1843 u8 ver, hdr, cnt, len; 1844 1845 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1846 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1847 } 1848 1849 static int 1850 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1851 { 1852 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1853 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1854 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1855 struct nouveau_encoder *nv_encoder; 1856 struct drm_encoder *encoder; 1857 struct nv50_disp *disp = nv50_disp(connector->dev); 1858 int type, ret; 1859 1860 switch (dcbe->type) { 1861 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1862 case DCB_OUTPUT_TMDS: 1863 case DCB_OUTPUT_DP: 1864 default: 1865 type = DRM_MODE_ENCODER_TMDS; 1866 break; 1867 } 1868 1869 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1870 if (!nv_encoder) 1871 return -ENOMEM; 1872 nv_encoder->dcb = dcbe; 1873 nv_encoder->update = nv50_sor_update; 1874 1875 encoder = to_drm_encoder(nv_encoder); 1876 encoder->possible_crtcs = dcbe->heads; 1877 encoder->possible_clones = 0; 1878 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1879 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1880 drm_encoder_helper_add(encoder, &nv50_sor_help); 1881 1882 drm_connector_attach_encoder(connector, encoder); 1883 1884 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1885 nv50_outp_dump_caps(drm, nv_encoder); 1886 1887 if (dcbe->type == DCB_OUTPUT_DP) { 1888 struct nvkm_i2c_aux *aux = 1889 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1890 1891 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1892 1893 if (aux) { 1894 if (disp->disp->object.oclass < GF110_DISP) { 1895 /* HW has no support for address-only 1896 * transactions, so we're required to 1897 * use custom I2C-over-AUX code. 1898 */ 1899 nv_encoder->i2c = &aux->i2c; 1900 } else { 1901 nv_encoder->i2c = &nv_connector->aux.ddc; 1902 } 1903 nv_encoder->aux = aux; 1904 } 1905 1906 if (nv_connector->type != DCB_CONNECTOR_eDP && 1907 nv50_has_mst(drm)) { 1908 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1909 16, nv_connector->base.base.id, 1910 &nv_encoder->dp.mstm); 1911 if (ret) 1912 return ret; 1913 } 1914 } else { 1915 struct nvkm_i2c_bus *bus = 1916 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1917 if (bus) 1918 nv_encoder->i2c = &bus->i2c; 1919 } 1920 1921 return 0; 1922 } 1923 1924 /****************************************************************************** 1925 * PIOR 1926 *****************************************************************************/ 1927 static int 1928 nv50_pior_atomic_check(struct drm_encoder *encoder, 1929 struct drm_crtc_state *crtc_state, 1930 struct drm_connector_state *conn_state) 1931 { 1932 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1933 if (ret) 1934 return ret; 1935 crtc_state->adjusted_mode.clock *= 2; 1936 return 0; 1937 } 1938 1939 static void 1940 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1941 { 1942 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1943 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1944 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1945 1946 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); 1947 nv_encoder->crtc = NULL; 1948 nv50_outp_release(nv_encoder); 1949 } 1950 1951 static void 1952 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1953 { 1954 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1955 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1956 struct nv50_head_atom *asyh = 1957 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1958 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1959 u32 ctrl = 0; 1960 1961 switch (nv_crtc->index) { 1962 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1963 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1964 default: 1965 WARN_ON(1); 1966 break; 1967 } 1968 1969 nv50_outp_acquire(nv_encoder, false); 1970 1971 switch (asyh->or.bpc) { 1972 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1973 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1974 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1975 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1976 } 1977 1978 switch (nv_encoder->dcb->type) { 1979 case DCB_OUTPUT_TMDS: 1980 case DCB_OUTPUT_DP: 1981 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1982 break; 1983 default: 1984 BUG(); 1985 break; 1986 } 1987 1988 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); 1989 nv_encoder->crtc = &nv_crtc->base; 1990 } 1991 1992 static const struct drm_encoder_helper_funcs 1993 nv50_pior_help = { 1994 .atomic_check = nv50_pior_atomic_check, 1995 .atomic_enable = nv50_pior_atomic_enable, 1996 .atomic_disable = nv50_pior_atomic_disable, 1997 }; 1998 1999 static void 2000 nv50_pior_destroy(struct drm_encoder *encoder) 2001 { 2002 drm_encoder_cleanup(encoder); 2003 kfree(encoder); 2004 } 2005 2006 static const struct drm_encoder_funcs 2007 nv50_pior_func = { 2008 .destroy = nv50_pior_destroy, 2009 }; 2010 2011 static int 2012 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 2013 { 2014 struct drm_device *dev = connector->dev; 2015 struct nouveau_drm *drm = nouveau_drm(dev); 2016 struct nv50_disp *disp = nv50_disp(dev); 2017 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 2018 struct nvkm_i2c_bus *bus = NULL; 2019 struct nvkm_i2c_aux *aux = NULL; 2020 struct i2c_adapter *ddc; 2021 struct nouveau_encoder *nv_encoder; 2022 struct drm_encoder *encoder; 2023 int type; 2024 2025 switch (dcbe->type) { 2026 case DCB_OUTPUT_TMDS: 2027 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 2028 ddc = bus ? &bus->i2c : NULL; 2029 type = DRM_MODE_ENCODER_TMDS; 2030 break; 2031 case DCB_OUTPUT_DP: 2032 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 2033 ddc = aux ? &aux->i2c : NULL; 2034 type = DRM_MODE_ENCODER_TMDS; 2035 break; 2036 default: 2037 return -ENODEV; 2038 } 2039 2040 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 2041 if (!nv_encoder) 2042 return -ENOMEM; 2043 nv_encoder->dcb = dcbe; 2044 nv_encoder->i2c = ddc; 2045 nv_encoder->aux = aux; 2046 2047 encoder = to_drm_encoder(nv_encoder); 2048 encoder->possible_crtcs = dcbe->heads; 2049 encoder->possible_clones = 0; 2050 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 2051 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 2052 drm_encoder_helper_add(encoder, &nv50_pior_help); 2053 2054 drm_connector_attach_encoder(connector, encoder); 2055 2056 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 2057 nv50_outp_dump_caps(drm, nv_encoder); 2058 2059 return 0; 2060 } 2061 2062 /****************************************************************************** 2063 * Atomic 2064 *****************************************************************************/ 2065 2066 static void 2067 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 2068 { 2069 struct nouveau_drm *drm = nouveau_drm(state->dev); 2070 struct nv50_disp *disp = nv50_disp(drm->dev); 2071 struct nv50_core *core = disp->core; 2072 struct nv50_mstm *mstm; 2073 struct drm_encoder *encoder; 2074 2075 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 2076 2077 drm_for_each_encoder(encoder, drm->dev) { 2078 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2079 mstm = nouveau_encoder(encoder)->dp.mstm; 2080 if (mstm && mstm->modified) 2081 nv50_mstm_prepare(mstm); 2082 } 2083 } 2084 2085 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 2086 core->func->update(core, interlock, true); 2087 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 2088 disp->core->chan.base.device)) 2089 NV_ERROR(drm, "core notifier timeout\n"); 2090 2091 drm_for_each_encoder(encoder, drm->dev) { 2092 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2093 mstm = nouveau_encoder(encoder)->dp.mstm; 2094 if (mstm && mstm->modified) 2095 nv50_mstm_cleanup(mstm); 2096 } 2097 } 2098 } 2099 2100 static void 2101 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2102 { 2103 struct drm_plane_state *new_plane_state; 2104 struct drm_plane *plane; 2105 int i; 2106 2107 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2108 struct nv50_wndw *wndw = nv50_wndw(plane); 2109 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2110 if (wndw->func->update) 2111 wndw->func->update(wndw, interlock); 2112 } 2113 } 2114 } 2115 2116 static void 2117 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2118 { 2119 struct drm_device *dev = state->dev; 2120 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2121 struct drm_crtc *crtc; 2122 struct drm_plane_state *new_plane_state; 2123 struct drm_plane *plane; 2124 struct nouveau_drm *drm = nouveau_drm(dev); 2125 struct nv50_disp *disp = nv50_disp(dev); 2126 struct nv50_atom *atom = nv50_atom(state); 2127 struct nv50_core *core = disp->core; 2128 struct nv50_outp_atom *outp, *outt; 2129 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2130 int i; 2131 bool flushed = false; 2132 2133 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2134 nv50_crc_atomic_stop_reporting(state); 2135 drm_atomic_helper_wait_for_fences(dev, state, false); 2136 drm_atomic_helper_wait_for_dependencies(state); 2137 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2138 drm_atomic_helper_calc_timestamping_constants(state); 2139 2140 if (atom->lock_core) 2141 mutex_lock(&disp->mutex); 2142 2143 /* Disable head(s). */ 2144 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2145 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2146 struct nv50_head *head = nv50_head(crtc); 2147 2148 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2149 asyh->clr.mask, asyh->set.mask); 2150 2151 if (old_crtc_state->active && !new_crtc_state->active) { 2152 pm_runtime_put_noidle(dev->dev); 2153 drm_crtc_vblank_off(crtc); 2154 } 2155 2156 if (asyh->clr.mask) { 2157 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2158 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2159 } 2160 } 2161 2162 /* Disable plane(s). */ 2163 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2164 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2165 struct nv50_wndw *wndw = nv50_wndw(plane); 2166 2167 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2168 asyw->clr.mask, asyw->set.mask); 2169 if (!asyw->clr.mask) 2170 continue; 2171 2172 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2173 } 2174 2175 /* Disable output path(s). */ 2176 list_for_each_entry(outp, &atom->outp, head) { 2177 const struct drm_encoder_helper_funcs *help; 2178 struct drm_encoder *encoder; 2179 2180 encoder = outp->encoder; 2181 help = encoder->helper_private; 2182 2183 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2184 outp->clr.mask, outp->set.mask); 2185 2186 if (outp->clr.mask) { 2187 help->atomic_disable(encoder, state); 2188 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2189 if (outp->flush_disable) { 2190 nv50_disp_atomic_commit_wndw(state, interlock); 2191 nv50_disp_atomic_commit_core(state, interlock); 2192 memset(interlock, 0x00, sizeof(interlock)); 2193 2194 flushed = true; 2195 } 2196 } 2197 } 2198 2199 /* Flush disable. */ 2200 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2201 if (atom->flush_disable) { 2202 nv50_disp_atomic_commit_wndw(state, interlock); 2203 nv50_disp_atomic_commit_core(state, interlock); 2204 memset(interlock, 0x00, sizeof(interlock)); 2205 2206 flushed = true; 2207 } 2208 } 2209 2210 if (flushed) 2211 nv50_crc_atomic_release_notifier_contexts(state); 2212 nv50_crc_atomic_init_notifier_contexts(state); 2213 2214 /* Update output path(s). */ 2215 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2216 const struct drm_encoder_helper_funcs *help; 2217 struct drm_encoder *encoder; 2218 2219 encoder = outp->encoder; 2220 help = encoder->helper_private; 2221 2222 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2223 outp->set.mask, outp->clr.mask); 2224 2225 if (outp->set.mask) { 2226 help->atomic_enable(encoder, state); 2227 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2228 } 2229 2230 list_del(&outp->head); 2231 kfree(outp); 2232 } 2233 2234 /* Update head(s). */ 2235 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2236 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2237 struct nv50_head *head = nv50_head(crtc); 2238 2239 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2240 asyh->set.mask, asyh->clr.mask); 2241 2242 if (asyh->set.mask) { 2243 nv50_head_flush_set(head, asyh); 2244 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2245 } 2246 2247 if (new_crtc_state->active) { 2248 if (!old_crtc_state->active) { 2249 drm_crtc_vblank_on(crtc); 2250 pm_runtime_get_noresume(dev->dev); 2251 } 2252 if (new_crtc_state->event) 2253 drm_crtc_vblank_get(crtc); 2254 } 2255 } 2256 2257 /* Update window->head assignment. 2258 * 2259 * This has to happen in an update that's not interlocked with 2260 * any window channels to avoid hitting HW error checks. 2261 * 2262 *TODO: Proper handling of window ownership (Turing apparently 2263 * supports non-fixed mappings). 2264 */ 2265 if (core->assign_windows) { 2266 core->func->wndw.owner(core); 2267 nv50_disp_atomic_commit_core(state, interlock); 2268 core->assign_windows = false; 2269 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2270 } 2271 2272 /* Finish updating head(s)... 2273 * 2274 * NVD is rather picky about both where window assignments can change, 2275 * *and* about certain core and window channel states matching. 2276 * 2277 * The EFI GOP driver on newer GPUs configures window channels with a 2278 * different output format to what we do, and the core channel update 2279 * in the assign_windows case above would result in a state mismatch. 2280 * 2281 * Delay some of the head update until after that point to workaround 2282 * the issue. This only affects the initial modeset. 2283 * 2284 * TODO: handle this better when adding flexible window mapping 2285 */ 2286 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2287 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2288 struct nv50_head *head = nv50_head(crtc); 2289 2290 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2291 asyh->set.mask, asyh->clr.mask); 2292 2293 if (asyh->set.mask) { 2294 nv50_head_flush_set_wndw(head, asyh); 2295 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2296 } 2297 } 2298 2299 /* Update plane(s). */ 2300 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2301 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2302 struct nv50_wndw *wndw = nv50_wndw(plane); 2303 2304 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2305 asyw->set.mask, asyw->clr.mask); 2306 if ( !asyw->set.mask && 2307 (!asyw->clr.mask || atom->flush_disable)) 2308 continue; 2309 2310 nv50_wndw_flush_set(wndw, interlock, asyw); 2311 } 2312 2313 /* Flush update. */ 2314 nv50_disp_atomic_commit_wndw(state, interlock); 2315 2316 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2317 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2318 interlock[NV50_DISP_INTERLOCK_OVLY] || 2319 interlock[NV50_DISP_INTERLOCK_WNDW] || 2320 !atom->state.legacy_cursor_update) 2321 nv50_disp_atomic_commit_core(state, interlock); 2322 else 2323 disp->core->func->update(disp->core, interlock, false); 2324 } 2325 2326 if (atom->lock_core) 2327 mutex_unlock(&disp->mutex); 2328 2329 /* Wait for HW to signal completion. */ 2330 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2331 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2332 struct nv50_wndw *wndw = nv50_wndw(plane); 2333 int ret = nv50_wndw_wait_armed(wndw, asyw); 2334 if (ret) 2335 NV_ERROR(drm, "%s: timeout\n", plane->name); 2336 } 2337 2338 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2339 if (new_crtc_state->event) { 2340 unsigned long flags; 2341 /* Get correct count/ts if racing with vblank irq */ 2342 if (new_crtc_state->active) 2343 drm_crtc_accurate_vblank_count(crtc); 2344 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2345 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2346 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2347 2348 new_crtc_state->event = NULL; 2349 if (new_crtc_state->active) 2350 drm_crtc_vblank_put(crtc); 2351 } 2352 } 2353 2354 nv50_crc_atomic_start_reporting(state); 2355 if (!flushed) 2356 nv50_crc_atomic_release_notifier_contexts(state); 2357 2358 drm_atomic_helper_commit_hw_done(state); 2359 drm_atomic_helper_cleanup_planes(dev, state); 2360 drm_atomic_helper_commit_cleanup_done(state); 2361 drm_atomic_state_put(state); 2362 2363 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2364 pm_runtime_mark_last_busy(dev->dev); 2365 pm_runtime_put_autosuspend(dev->dev); 2366 } 2367 2368 static void 2369 nv50_disp_atomic_commit_work(struct work_struct *work) 2370 { 2371 struct drm_atomic_state *state = 2372 container_of(work, typeof(*state), commit_work); 2373 nv50_disp_atomic_commit_tail(state); 2374 } 2375 2376 static int 2377 nv50_disp_atomic_commit(struct drm_device *dev, 2378 struct drm_atomic_state *state, bool nonblock) 2379 { 2380 struct drm_plane_state *new_plane_state; 2381 struct drm_plane *plane; 2382 int ret, i; 2383 2384 ret = pm_runtime_get_sync(dev->dev); 2385 if (ret < 0 && ret != -EACCES) { 2386 pm_runtime_put_autosuspend(dev->dev); 2387 return ret; 2388 } 2389 2390 ret = drm_atomic_helper_setup_commit(state, nonblock); 2391 if (ret) 2392 goto done; 2393 2394 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2395 2396 ret = drm_atomic_helper_prepare_planes(dev, state); 2397 if (ret) 2398 goto done; 2399 2400 if (!nonblock) { 2401 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2402 if (ret) 2403 goto err_cleanup; 2404 } 2405 2406 ret = drm_atomic_helper_swap_state(state, true); 2407 if (ret) 2408 goto err_cleanup; 2409 2410 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2411 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2412 struct nv50_wndw *wndw = nv50_wndw(plane); 2413 2414 if (asyw->set.image) 2415 nv50_wndw_ntfy_enable(wndw, asyw); 2416 } 2417 2418 drm_atomic_state_get(state); 2419 2420 /* 2421 * Grab another RPM ref for the commit tail, which will release the 2422 * ref when it's finished 2423 */ 2424 pm_runtime_get_noresume(dev->dev); 2425 2426 if (nonblock) 2427 queue_work(system_unbound_wq, &state->commit_work); 2428 else 2429 nv50_disp_atomic_commit_tail(state); 2430 2431 err_cleanup: 2432 if (ret) 2433 drm_atomic_helper_cleanup_planes(dev, state); 2434 done: 2435 pm_runtime_put_autosuspend(dev->dev); 2436 return ret; 2437 } 2438 2439 static struct nv50_outp_atom * 2440 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2441 { 2442 struct nv50_outp_atom *outp; 2443 2444 list_for_each_entry(outp, &atom->outp, head) { 2445 if (outp->encoder == encoder) 2446 return outp; 2447 } 2448 2449 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2450 if (!outp) 2451 return ERR_PTR(-ENOMEM); 2452 2453 list_add(&outp->head, &atom->outp); 2454 outp->encoder = encoder; 2455 return outp; 2456 } 2457 2458 static int 2459 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2460 struct drm_connector_state *old_connector_state) 2461 { 2462 struct drm_encoder *encoder = old_connector_state->best_encoder; 2463 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2464 struct drm_crtc *crtc; 2465 struct nv50_outp_atom *outp; 2466 2467 if (!(crtc = old_connector_state->crtc)) 2468 return 0; 2469 2470 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2471 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2472 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2473 outp = nv50_disp_outp_atomic_add(atom, encoder); 2474 if (IS_ERR(outp)) 2475 return PTR_ERR(outp); 2476 2477 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2478 outp->flush_disable = true; 2479 atom->flush_disable = true; 2480 } 2481 outp->clr.ctrl = true; 2482 atom->lock_core = true; 2483 } 2484 2485 return 0; 2486 } 2487 2488 static int 2489 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2490 struct drm_connector_state *connector_state) 2491 { 2492 struct drm_encoder *encoder = connector_state->best_encoder; 2493 struct drm_crtc_state *new_crtc_state; 2494 struct drm_crtc *crtc; 2495 struct nv50_outp_atom *outp; 2496 2497 if (!(crtc = connector_state->crtc)) 2498 return 0; 2499 2500 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2501 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2502 outp = nv50_disp_outp_atomic_add(atom, encoder); 2503 if (IS_ERR(outp)) 2504 return PTR_ERR(outp); 2505 2506 outp->set.ctrl = true; 2507 atom->lock_core = true; 2508 } 2509 2510 return 0; 2511 } 2512 2513 static int 2514 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2515 { 2516 struct nv50_atom *atom = nv50_atom(state); 2517 struct nv50_core *core = nv50_disp(dev)->core; 2518 struct drm_connector_state *old_connector_state, *new_connector_state; 2519 struct drm_connector *connector; 2520 struct drm_crtc_state *new_crtc_state; 2521 struct drm_crtc *crtc; 2522 struct nv50_head *head; 2523 struct nv50_head_atom *asyh; 2524 int ret, i; 2525 2526 if (core->assign_windows && core->func->head->static_wndw_map) { 2527 drm_for_each_crtc(crtc, dev) { 2528 new_crtc_state = drm_atomic_get_crtc_state(state, 2529 crtc); 2530 if (IS_ERR(new_crtc_state)) 2531 return PTR_ERR(new_crtc_state); 2532 2533 head = nv50_head(crtc); 2534 asyh = nv50_head_atom(new_crtc_state); 2535 core->func->head->static_wndw_map(head, asyh); 2536 } 2537 } 2538 2539 /* We need to handle colour management on a per-plane basis. */ 2540 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2541 if (new_crtc_state->color_mgmt_changed) { 2542 ret = drm_atomic_add_affected_planes(state, crtc); 2543 if (ret) 2544 return ret; 2545 } 2546 } 2547 2548 ret = drm_atomic_helper_check(dev, state); 2549 if (ret) 2550 return ret; 2551 2552 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2553 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2554 if (ret) 2555 return ret; 2556 2557 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2558 if (ret) 2559 return ret; 2560 } 2561 2562 ret = drm_dp_mst_atomic_check(state); 2563 if (ret) 2564 return ret; 2565 2566 nv50_crc_atomic_check_outp(atom); 2567 2568 return 0; 2569 } 2570 2571 static void 2572 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2573 { 2574 struct nv50_atom *atom = nv50_atom(state); 2575 struct nv50_outp_atom *outp, *outt; 2576 2577 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2578 list_del(&outp->head); 2579 kfree(outp); 2580 } 2581 2582 drm_atomic_state_default_clear(state); 2583 } 2584 2585 static void 2586 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2587 { 2588 struct nv50_atom *atom = nv50_atom(state); 2589 drm_atomic_state_default_release(&atom->state); 2590 kfree(atom); 2591 } 2592 2593 static struct drm_atomic_state * 2594 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2595 { 2596 struct nv50_atom *atom; 2597 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2598 drm_atomic_state_init(dev, &atom->state) < 0) { 2599 kfree(atom); 2600 return NULL; 2601 } 2602 INIT_LIST_HEAD(&atom->outp); 2603 return &atom->state; 2604 } 2605 2606 static const struct drm_mode_config_funcs 2607 nv50_disp_func = { 2608 .fb_create = nouveau_user_framebuffer_create, 2609 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2610 .atomic_check = nv50_disp_atomic_check, 2611 .atomic_commit = nv50_disp_atomic_commit, 2612 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2613 .atomic_state_clear = nv50_disp_atomic_state_clear, 2614 .atomic_state_free = nv50_disp_atomic_state_free, 2615 }; 2616 2617 /****************************************************************************** 2618 * Init 2619 *****************************************************************************/ 2620 2621 static void 2622 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2623 { 2624 struct nouveau_drm *drm = nouveau_drm(dev); 2625 struct drm_encoder *encoder; 2626 struct drm_plane *plane; 2627 2628 drm_for_each_plane(plane, dev) { 2629 struct nv50_wndw *wndw = nv50_wndw(plane); 2630 if (plane->funcs != &nv50_wndw) 2631 continue; 2632 nv50_wndw_fini(wndw); 2633 } 2634 2635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2636 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2637 nv50_mstm_fini(nouveau_encoder(encoder)); 2638 } 2639 2640 if (!runtime) 2641 cancel_work_sync(&drm->hpd_work); 2642 } 2643 2644 static int 2645 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2646 { 2647 struct nv50_core *core = nv50_disp(dev)->core; 2648 struct drm_encoder *encoder; 2649 struct drm_plane *plane; 2650 2651 if (resume || runtime) 2652 core->func->init(core); 2653 2654 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2655 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2656 struct nouveau_encoder *nv_encoder = 2657 nouveau_encoder(encoder); 2658 nv50_mstm_init(nv_encoder, runtime); 2659 } 2660 } 2661 2662 drm_for_each_plane(plane, dev) { 2663 struct nv50_wndw *wndw = nv50_wndw(plane); 2664 if (plane->funcs != &nv50_wndw) 2665 continue; 2666 nv50_wndw_init(wndw); 2667 } 2668 2669 return 0; 2670 } 2671 2672 static void 2673 nv50_display_destroy(struct drm_device *dev) 2674 { 2675 struct nv50_disp *disp = nv50_disp(dev); 2676 2677 nv50_audio_component_fini(nouveau_drm(dev)); 2678 2679 nvif_object_unmap(&disp->caps); 2680 nvif_object_dtor(&disp->caps); 2681 nv50_core_del(&disp->core); 2682 2683 nouveau_bo_unmap(disp->sync); 2684 if (disp->sync) 2685 nouveau_bo_unpin(disp->sync); 2686 nouveau_bo_ref(NULL, &disp->sync); 2687 2688 nouveau_display(dev)->priv = NULL; 2689 kfree(disp); 2690 } 2691 2692 int 2693 nv50_display_create(struct drm_device *dev) 2694 { 2695 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2696 struct nouveau_drm *drm = nouveau_drm(dev); 2697 struct dcb_table *dcb = &drm->vbios.dcb; 2698 struct drm_connector *connector, *tmp; 2699 struct nv50_disp *disp; 2700 struct dcb_output *dcbe; 2701 int crtcs, ret, i; 2702 bool has_mst = nv50_has_mst(drm); 2703 2704 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2705 if (!disp) 2706 return -ENOMEM; 2707 2708 mutex_init(&disp->mutex); 2709 2710 nouveau_display(dev)->priv = disp; 2711 nouveau_display(dev)->dtor = nv50_display_destroy; 2712 nouveau_display(dev)->init = nv50_display_init; 2713 nouveau_display(dev)->fini = nv50_display_fini; 2714 disp->disp = &nouveau_display(dev)->disp; 2715 dev->mode_config.funcs = &nv50_disp_func; 2716 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2717 dev->mode_config.normalize_zpos = true; 2718 2719 /* small shared memory area we use for notifiers and semaphores */ 2720 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2721 NOUVEAU_GEM_DOMAIN_VRAM, 2722 0, 0x0000, NULL, NULL, &disp->sync); 2723 if (!ret) { 2724 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2725 if (!ret) { 2726 ret = nouveau_bo_map(disp->sync); 2727 if (ret) 2728 nouveau_bo_unpin(disp->sync); 2729 } 2730 if (ret) 2731 nouveau_bo_ref(NULL, &disp->sync); 2732 } 2733 2734 if (ret) 2735 goto out; 2736 2737 /* allocate master evo channel */ 2738 ret = nv50_core_new(drm, &disp->core); 2739 if (ret) 2740 goto out; 2741 2742 disp->core->func->init(disp->core); 2743 if (disp->core->func->caps_init) { 2744 ret = disp->core->func->caps_init(drm, disp); 2745 if (ret) 2746 goto out; 2747 } 2748 2749 /* Assign the correct format modifiers */ 2750 if (disp->disp->object.oclass >= TU102_DISP) 2751 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2752 else 2753 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2754 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2755 else 2756 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2757 2758 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later 2759 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The 2760 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to 2761 * small page allocations in prepare_fb(). When this is implemented, we should also force 2762 * large pages (128K) for ovly fbs in order to fix Kepler ovlys. 2763 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using 2764 * large pages. 2765 */ 2766 if (disp->disp->object.oclass >= GM107_DISP) { 2767 dev->mode_config.cursor_width = 256; 2768 dev->mode_config.cursor_height = 256; 2769 } else if (disp->disp->object.oclass >= GK104_DISP) { 2770 dev->mode_config.cursor_width = 128; 2771 dev->mode_config.cursor_height = 128; 2772 } else { 2773 dev->mode_config.cursor_width = 64; 2774 dev->mode_config.cursor_height = 64; 2775 } 2776 2777 /* create crtc objects to represent the hw heads */ 2778 if (disp->disp->object.oclass >= GV100_DISP) 2779 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2780 else 2781 if (disp->disp->object.oclass >= GF110_DISP) 2782 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2783 else 2784 crtcs = 0x3; 2785 2786 for (i = 0; i < fls(crtcs); i++) { 2787 struct nv50_head *head; 2788 2789 if (!(crtcs & (1 << i))) 2790 continue; 2791 2792 head = nv50_head_create(dev, i); 2793 if (IS_ERR(head)) { 2794 ret = PTR_ERR(head); 2795 goto out; 2796 } 2797 2798 if (has_mst) { 2799 head->msto = nv50_msto_new(dev, head, i); 2800 if (IS_ERR(head->msto)) { 2801 ret = PTR_ERR(head->msto); 2802 head->msto = NULL; 2803 goto out; 2804 } 2805 2806 /* 2807 * FIXME: This is a hack to workaround the following 2808 * issues: 2809 * 2810 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2811 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2812 * 2813 * Once these issues are closed, this should be 2814 * removed 2815 */ 2816 head->msto->encoder.possible_crtcs = crtcs; 2817 } 2818 } 2819 2820 /* create encoder/connector objects based on VBIOS DCB table */ 2821 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2822 connector = nouveau_connector_create(dev, dcbe); 2823 if (IS_ERR(connector)) 2824 continue; 2825 2826 if (dcbe->location == DCB_LOC_ON_CHIP) { 2827 switch (dcbe->type) { 2828 case DCB_OUTPUT_TMDS: 2829 case DCB_OUTPUT_LVDS: 2830 case DCB_OUTPUT_DP: 2831 ret = nv50_sor_create(connector, dcbe); 2832 break; 2833 case DCB_OUTPUT_ANALOG: 2834 ret = nv50_dac_create(connector, dcbe); 2835 break; 2836 default: 2837 ret = -ENODEV; 2838 break; 2839 } 2840 } else { 2841 ret = nv50_pior_create(connector, dcbe); 2842 } 2843 2844 if (ret) { 2845 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2846 dcbe->location, dcbe->type, 2847 ffs(dcbe->or) - 1, ret); 2848 ret = 0; 2849 } 2850 } 2851 2852 /* cull any connectors we created that don't have an encoder */ 2853 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2854 if (connector->possible_encoders) 2855 continue; 2856 2857 NV_WARN(drm, "%s has no encoders, removing\n", 2858 connector->name); 2859 connector->funcs->destroy(connector); 2860 } 2861 2862 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2863 dev->vblank_disable_immediate = true; 2864 2865 nv50_audio_component_init(drm); 2866 2867 out: 2868 if (ret) 2869 nv50_display_destroy(dev); 2870 return ret; 2871 } 2872 2873 /****************************************************************************** 2874 * Format modifiers 2875 *****************************************************************************/ 2876 2877 /**************************************************************** 2878 * Log2(block height) ----------------------------+ * 2879 * Page Kind ----------------------------------+ | * 2880 * Gob Height/Page Kind Generation ------+ | | * 2881 * Sector layout -------+ | | | * 2882 * Compression ------+ | | | | */ 2883 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2884 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2885 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2886 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2887 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2888 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2889 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2890 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2891 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2892 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2893 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2894 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2895 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2896 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2897 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2898 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2899 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2900 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2901 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2902 DRM_FORMAT_MOD_LINEAR, 2903 DRM_FORMAT_MOD_INVALID 2904 }; 2905 2906 /**************************************************************** 2907 * Log2(block height) ----------------------------+ * 2908 * Page Kind ----------------------------------+ | * 2909 * Gob Height/Page Kind Generation ------+ | | * 2910 * Sector layout -------+ | | | * 2911 * Compression ------+ | | | | */ 2912 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2913 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2914 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2915 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2916 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2917 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2918 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2919 DRM_FORMAT_MOD_LINEAR, 2920 DRM_FORMAT_MOD_INVALID 2921 }; 2922