1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_plane_helper.h> 39 #include <drm/drm_scdc_helper.h> 40 #include <drm/drm_edid.h> 41 42 #include <nvif/class.h> 43 #include <nvif/cl0002.h> 44 #include <nvif/cl5070.h> 45 #include <nvif/cl507d.h> 46 #include <nvif/event.h> 47 48 #include "nouveau_drv.h" 49 #include "nouveau_dma.h" 50 #include "nouveau_gem.h" 51 #include "nouveau_connector.h" 52 #include "nouveau_encoder.h" 53 #include "nouveau_fence.h" 54 #include "nouveau_fbcon.h" 55 56 #include <subdev/bios/dp.h> 57 58 /****************************************************************************** 59 * Atomic state 60 *****************************************************************************/ 61 62 struct nv50_outp_atom { 63 struct list_head head; 64 65 struct drm_encoder *encoder; 66 bool flush_disable; 67 68 union nv50_outp_atom_mask { 69 struct { 70 bool ctrl:1; 71 }; 72 u8 mask; 73 } set, clr; 74 }; 75 76 /****************************************************************************** 77 * EVO channel 78 *****************************************************************************/ 79 80 static int 81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 82 const s32 *oclass, u8 head, void *data, u32 size, 83 struct nv50_chan *chan) 84 { 85 struct nvif_sclass *sclass; 86 int ret, i, n; 87 88 chan->device = device; 89 90 ret = n = nvif_object_sclass_get(disp, &sclass); 91 if (ret < 0) 92 return ret; 93 94 while (oclass[0]) { 95 for (i = 0; i < n; i++) { 96 if (sclass[i].oclass == oclass[0]) { 97 ret = nvif_object_init(disp, 0, oclass[0], 98 data, size, &chan->user); 99 if (ret == 0) 100 nvif_object_map(&chan->user, NULL, 0); 101 nvif_object_sclass_put(&sclass); 102 return ret; 103 } 104 } 105 oclass++; 106 } 107 108 nvif_object_sclass_put(&sclass); 109 return -ENOSYS; 110 } 111 112 static void 113 nv50_chan_destroy(struct nv50_chan *chan) 114 { 115 nvif_object_fini(&chan->user); 116 } 117 118 /****************************************************************************** 119 * DMA EVO channel 120 *****************************************************************************/ 121 122 void 123 nv50_dmac_destroy(struct nv50_dmac *dmac) 124 { 125 nvif_object_fini(&dmac->vram); 126 nvif_object_fini(&dmac->sync); 127 128 nv50_chan_destroy(&dmac->base); 129 130 nvif_mem_fini(&dmac->push); 131 } 132 133 int 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 136 struct nv50_dmac *dmac) 137 { 138 struct nouveau_cli *cli = (void *)device->object.client; 139 struct nv50_disp_core_channel_dma_v0 *args = data; 140 u8 type = NVIF_MEM_COHERENT; 141 int ret; 142 143 mutex_init(&dmac->lock); 144 145 /* Pascal added support for 47-bit physical addresses, but some 146 * parts of EVO still only accept 40-bit PAs. 147 * 148 * To avoid issues on systems with large amounts of RAM, and on 149 * systems where an IOMMU maps pages at a high address, we need 150 * to allocate push buffers in VRAM instead. 151 * 152 * This appears to match NVIDIA's behaviour on Pascal. 153 */ 154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 155 type |= NVIF_MEM_VRAM; 156 157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 158 if (ret) 159 return ret; 160 161 dmac->ptr = dmac->push.object.map.ptr; 162 163 args->pushbuf = nvif_handle(&dmac->push.object); 164 165 ret = nv50_chan_create(device, disp, oclass, head, data, size, 166 &dmac->base); 167 if (ret) 168 return ret; 169 170 if (!syncbuf) 171 return 0; 172 173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 174 &(struct nv_dma_v0) { 175 .target = NV_DMA_V0_TARGET_VRAM, 176 .access = NV_DMA_V0_ACCESS_RDWR, 177 .start = syncbuf + 0x0000, 178 .limit = syncbuf + 0x0fff, 179 }, sizeof(struct nv_dma_v0), 180 &dmac->sync); 181 if (ret) 182 return ret; 183 184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 185 &(struct nv_dma_v0) { 186 .target = NV_DMA_V0_TARGET_VRAM, 187 .access = NV_DMA_V0_ACCESS_RDWR, 188 .start = 0, 189 .limit = device->info.ram_user - 1, 190 }, sizeof(struct nv_dma_v0), 191 &dmac->vram); 192 if (ret) 193 return ret; 194 195 return ret; 196 } 197 198 /****************************************************************************** 199 * EVO channel helpers 200 *****************************************************************************/ 201 u32 * 202 evo_wait(struct nv50_dmac *evoc, int nr) 203 { 204 struct nv50_dmac *dmac = evoc; 205 struct nvif_device *device = dmac->base.device; 206 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 207 208 mutex_lock(&dmac->lock); 209 if (put + nr >= (PAGE_SIZE / 4) - 8) { 210 dmac->ptr[put] = 0x20000000; 211 212 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 213 if (nvif_msec(device, 2000, 214 if (!nvif_rd32(&dmac->base.user, 0x0004)) 215 break; 216 ) < 0) { 217 mutex_unlock(&dmac->lock); 218 pr_err("nouveau: evo channel stalled\n"); 219 return NULL; 220 } 221 222 put = 0; 223 } 224 225 return dmac->ptr + put; 226 } 227 228 void 229 evo_kick(u32 *push, struct nv50_dmac *evoc) 230 { 231 struct nv50_dmac *dmac = evoc; 232 233 /* Push buffer fetches are not coherent with BAR1, we need to ensure 234 * writes have been flushed right through to VRAM before writing PUT. 235 */ 236 if (dmac->push.type & NVIF_MEM_VRAM) { 237 struct nvif_device *device = dmac->base.device; 238 nvif_wr32(&device->object, 0x070000, 0x00000001); 239 nvif_msec(device, 2000, 240 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 241 break; 242 ); 243 } 244 245 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 246 mutex_unlock(&dmac->lock); 247 } 248 249 /****************************************************************************** 250 * Output path helpers 251 *****************************************************************************/ 252 static void 253 nv50_outp_release(struct nouveau_encoder *nv_encoder) 254 { 255 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 256 struct { 257 struct nv50_disp_mthd_v1 base; 258 } args = { 259 .base.version = 1, 260 .base.method = NV50_DISP_MTHD_V1_RELEASE, 261 .base.hasht = nv_encoder->dcb->hasht, 262 .base.hashm = nv_encoder->dcb->hashm, 263 }; 264 265 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 266 nv_encoder->or = -1; 267 nv_encoder->link = 0; 268 } 269 270 static int 271 nv50_outp_acquire(struct nouveau_encoder *nv_encoder) 272 { 273 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 274 struct nv50_disp *disp = nv50_disp(drm->dev); 275 struct { 276 struct nv50_disp_mthd_v1 base; 277 struct nv50_disp_acquire_v0 info; 278 } args = { 279 .base.version = 1, 280 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 281 .base.hasht = nv_encoder->dcb->hasht, 282 .base.hashm = nv_encoder->dcb->hashm, 283 }; 284 int ret; 285 286 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 287 if (ret) { 288 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 289 return ret; 290 } 291 292 nv_encoder->or = args.info.or; 293 nv_encoder->link = args.info.link; 294 return 0; 295 } 296 297 static int 298 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 299 struct drm_crtc_state *crtc_state, 300 struct drm_connector_state *conn_state, 301 struct drm_display_mode *native_mode) 302 { 303 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 304 struct drm_display_mode *mode = &crtc_state->mode; 305 struct drm_connector *connector = conn_state->connector; 306 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 307 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 308 309 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 310 asyc->scaler.full = false; 311 if (!native_mode) 312 return 0; 313 314 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 315 switch (connector->connector_type) { 316 case DRM_MODE_CONNECTOR_LVDS: 317 case DRM_MODE_CONNECTOR_eDP: 318 /* Force use of scaler for non-EDID modes. */ 319 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) 320 break; 321 mode = native_mode; 322 asyc->scaler.full = true; 323 break; 324 default: 325 break; 326 } 327 } else { 328 mode = native_mode; 329 } 330 331 if (!drm_mode_equal(adjusted_mode, mode)) { 332 drm_mode_copy(adjusted_mode, mode); 333 crtc_state->mode_changed = true; 334 } 335 336 return 0; 337 } 338 339 static int 340 nv50_outp_atomic_check(struct drm_encoder *encoder, 341 struct drm_crtc_state *crtc_state, 342 struct drm_connector_state *conn_state) 343 { 344 struct nouveau_connector *nv_connector = 345 nouveau_connector(conn_state->connector); 346 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 347 nv_connector->native_mode); 348 } 349 350 /****************************************************************************** 351 * DAC 352 *****************************************************************************/ 353 static void 354 nv50_dac_disable(struct drm_encoder *encoder) 355 { 356 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 357 struct nv50_core *core = nv50_disp(encoder->dev)->core; 358 if (nv_encoder->crtc) 359 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 360 nv_encoder->crtc = NULL; 361 nv50_outp_release(nv_encoder); 362 } 363 364 static void 365 nv50_dac_enable(struct drm_encoder *encoder) 366 { 367 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 368 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 369 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 370 struct nv50_core *core = nv50_disp(encoder->dev)->core; 371 372 nv50_outp_acquire(nv_encoder); 373 374 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 375 asyh->or.depth = 0; 376 377 nv_encoder->crtc = encoder->crtc; 378 } 379 380 static enum drm_connector_status 381 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 382 { 383 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 384 struct nv50_disp *disp = nv50_disp(encoder->dev); 385 struct { 386 struct nv50_disp_mthd_v1 base; 387 struct nv50_disp_dac_load_v0 load; 388 } args = { 389 .base.version = 1, 390 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 391 .base.hasht = nv_encoder->dcb->hasht, 392 .base.hashm = nv_encoder->dcb->hashm, 393 }; 394 int ret; 395 396 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 397 if (args.load.data == 0) 398 args.load.data = 340; 399 400 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 401 if (ret || !args.load.load) 402 return connector_status_disconnected; 403 404 return connector_status_connected; 405 } 406 407 static const struct drm_encoder_helper_funcs 408 nv50_dac_help = { 409 .atomic_check = nv50_outp_atomic_check, 410 .enable = nv50_dac_enable, 411 .disable = nv50_dac_disable, 412 .detect = nv50_dac_detect 413 }; 414 415 static void 416 nv50_dac_destroy(struct drm_encoder *encoder) 417 { 418 drm_encoder_cleanup(encoder); 419 kfree(encoder); 420 } 421 422 static const struct drm_encoder_funcs 423 nv50_dac_func = { 424 .destroy = nv50_dac_destroy, 425 }; 426 427 static int 428 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 429 { 430 struct nouveau_drm *drm = nouveau_drm(connector->dev); 431 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 432 struct nvkm_i2c_bus *bus; 433 struct nouveau_encoder *nv_encoder; 434 struct drm_encoder *encoder; 435 int type = DRM_MODE_ENCODER_DAC; 436 437 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 438 if (!nv_encoder) 439 return -ENOMEM; 440 nv_encoder->dcb = dcbe; 441 442 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 443 if (bus) 444 nv_encoder->i2c = &bus->i2c; 445 446 encoder = to_drm_encoder(nv_encoder); 447 encoder->possible_crtcs = dcbe->heads; 448 encoder->possible_clones = 0; 449 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 450 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 451 drm_encoder_helper_add(encoder, &nv50_dac_help); 452 453 drm_connector_attach_encoder(connector, encoder); 454 return 0; 455 } 456 457 /****************************************************************************** 458 * Audio 459 *****************************************************************************/ 460 static void 461 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 462 { 463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 464 struct nv50_disp *disp = nv50_disp(encoder->dev); 465 struct { 466 struct nv50_disp_mthd_v1 base; 467 struct nv50_disp_sor_hda_eld_v0 eld; 468 } args = { 469 .base.version = 1, 470 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 471 .base.hasht = nv_encoder->dcb->hasht, 472 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 473 (0x0100 << nv_crtc->index), 474 }; 475 476 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 477 } 478 479 static void 480 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 481 { 482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 483 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 484 struct nouveau_connector *nv_connector; 485 struct nv50_disp *disp = nv50_disp(encoder->dev); 486 struct __packed { 487 struct { 488 struct nv50_disp_mthd_v1 mthd; 489 struct nv50_disp_sor_hda_eld_v0 eld; 490 } base; 491 u8 data[sizeof(nv_connector->base.eld)]; 492 } args = { 493 .base.mthd.version = 1, 494 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 495 .base.mthd.hasht = nv_encoder->dcb->hasht, 496 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 497 (0x0100 << nv_crtc->index), 498 }; 499 500 nv_connector = nouveau_encoder_connector_get(nv_encoder); 501 if (!drm_detect_monitor_audio(nv_connector->edid)) 502 return; 503 504 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 505 506 nvif_mthd(&disp->disp->object, 0, &args, 507 sizeof(args.base) + drm_eld_size(args.data)); 508 } 509 510 /****************************************************************************** 511 * HDMI 512 *****************************************************************************/ 513 static void 514 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 515 { 516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 517 struct nv50_disp *disp = nv50_disp(encoder->dev); 518 struct { 519 struct nv50_disp_mthd_v1 base; 520 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 521 } args = { 522 .base.version = 1, 523 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 524 .base.hasht = nv_encoder->dcb->hasht, 525 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 526 (0x0100 << nv_crtc->index), 527 }; 528 529 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 530 } 531 532 static void 533 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 534 { 535 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 536 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 537 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 538 struct nv50_disp *disp = nv50_disp(encoder->dev); 539 struct { 540 struct nv50_disp_mthd_v1 base; 541 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 542 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 543 } args = { 544 .base.version = 1, 545 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 546 .base.hasht = nv_encoder->dcb->hasht, 547 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 548 (0x0100 << nv_crtc->index), 549 .pwr.state = 1, 550 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 551 }; 552 struct nouveau_connector *nv_connector; 553 struct drm_hdmi_info *hdmi; 554 u32 max_ac_packet; 555 union hdmi_infoframe avi_frame; 556 union hdmi_infoframe vendor_frame; 557 bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false; 558 u8 config; 559 int ret; 560 int size; 561 562 nv_connector = nouveau_encoder_connector_get(nv_encoder); 563 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 564 return; 565 566 hdmi = &nv_connector->base.display_info.hdmi; 567 scdc_supported = hdmi->scdc.supported; 568 569 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode, 570 scdc_supported); 571 if (!ret) { 572 /* We have an AVI InfoFrame, populate it to the display */ 573 args.pwr.avi_infoframe_length 574 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 575 } 576 577 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 578 &nv_connector->base, mode); 579 if (!ret) { 580 /* We have a Vendor InfoFrame, populate it to the display */ 581 args.pwr.vendor_infoframe_length 582 = hdmi_infoframe_pack(&vendor_frame, 583 args.infoframes 584 + args.pwr.avi_infoframe_length, 585 17); 586 } 587 588 max_ac_packet = mode->htotal - mode->hdisplay; 589 max_ac_packet -= args.pwr.rekey; 590 max_ac_packet -= 18; /* constant from tegra */ 591 args.pwr.max_ac_packet = max_ac_packet / 32; 592 593 if (hdmi->scdc.scrambling.supported) { 594 high_tmds_clock_ratio = mode->clock > 340000; 595 scrambling = high_tmds_clock_ratio || 596 hdmi->scdc.scrambling.low_rates; 597 } 598 599 args.pwr.scdc = 600 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 601 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 602 603 size = sizeof(args.base) 604 + sizeof(args.pwr) 605 + args.pwr.avi_infoframe_length 606 + args.pwr.vendor_infoframe_length; 607 nvif_mthd(&disp->disp->object, 0, &args, size); 608 609 nv50_audio_enable(encoder, mode); 610 611 /* If SCDC is supported by the downstream monitor, update 612 * divider / scrambling settings to what we programmed above. 613 */ 614 if (!hdmi->scdc.scrambling.supported) 615 return; 616 617 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 618 if (ret < 0) { 619 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 620 return; 621 } 622 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 623 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 624 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 625 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 626 if (ret < 0) 627 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 628 config, ret); 629 } 630 631 /****************************************************************************** 632 * MST 633 *****************************************************************************/ 634 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 635 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 636 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 637 638 struct nv50_mstm { 639 struct nouveau_encoder *outp; 640 641 struct drm_dp_mst_topology_mgr mgr; 642 struct nv50_msto *msto[4]; 643 644 bool modified; 645 bool disabled; 646 int links; 647 }; 648 649 struct nv50_mstc { 650 struct nv50_mstm *mstm; 651 struct drm_dp_mst_port *port; 652 struct drm_connector connector; 653 654 struct drm_display_mode *native; 655 struct edid *edid; 656 657 int pbn; 658 }; 659 660 struct nv50_msto { 661 struct drm_encoder encoder; 662 663 struct nv50_head *head; 664 struct nv50_mstc *mstc; 665 bool disabled; 666 }; 667 668 static struct drm_dp_payload * 669 nv50_msto_payload(struct nv50_msto *msto) 670 { 671 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 672 struct nv50_mstc *mstc = msto->mstc; 673 struct nv50_mstm *mstm = mstc->mstm; 674 int vcpi = mstc->port->vcpi.vcpi, i; 675 676 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 677 for (i = 0; i < mstm->mgr.max_payloads; i++) { 678 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 679 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 680 mstm->outp->base.base.name, i, payload->vcpi, 681 payload->start_slot, payload->num_slots); 682 } 683 684 for (i = 0; i < mstm->mgr.max_payloads; i++) { 685 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 686 if (payload->vcpi == vcpi) 687 return payload; 688 } 689 690 return NULL; 691 } 692 693 static void 694 nv50_msto_cleanup(struct nv50_msto *msto) 695 { 696 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 697 struct nv50_mstc *mstc = msto->mstc; 698 struct nv50_mstm *mstm = mstc->mstm; 699 700 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 701 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto)) 702 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 703 if (msto->disabled) { 704 msto->mstc = NULL; 705 msto->head = NULL; 706 msto->disabled = false; 707 } 708 } 709 710 static void 711 nv50_msto_prepare(struct nv50_msto *msto) 712 { 713 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 714 struct nv50_mstc *mstc = msto->mstc; 715 struct nv50_mstm *mstm = mstc->mstm; 716 struct { 717 struct nv50_disp_mthd_v1 base; 718 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 719 } args = { 720 .base.version = 1, 721 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 722 .base.hasht = mstm->outp->dcb->hasht, 723 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 724 (0x0100 << msto->head->base.index), 725 }; 726 727 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 728 if (mstc->port && mstc->port->vcpi.vcpi > 0) { 729 struct drm_dp_payload *payload = nv50_msto_payload(msto); 730 if (payload) { 731 args.vcpi.start_slot = payload->start_slot; 732 args.vcpi.num_slots = payload->num_slots; 733 args.vcpi.pbn = mstc->port->vcpi.pbn; 734 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 735 } 736 } 737 738 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 739 msto->encoder.name, msto->head->base.base.name, 740 args.vcpi.start_slot, args.vcpi.num_slots, 741 args.vcpi.pbn, args.vcpi.aligned_pbn); 742 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 743 } 744 745 static int 746 nv50_msto_atomic_check(struct drm_encoder *encoder, 747 struct drm_crtc_state *crtc_state, 748 struct drm_connector_state *conn_state) 749 { 750 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector); 751 struct nv50_mstm *mstm = mstc->mstm; 752 int bpp = conn_state->connector->display_info.bpc * 3; 753 int slots; 754 755 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp); 756 757 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 758 if (slots < 0) 759 return slots; 760 761 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 762 mstc->native); 763 } 764 765 static void 766 nv50_msto_enable(struct drm_encoder *encoder) 767 { 768 struct nv50_head *head = nv50_head(encoder->crtc); 769 struct nv50_msto *msto = nv50_msto(encoder); 770 struct nv50_mstc *mstc = NULL; 771 struct nv50_mstm *mstm = NULL; 772 struct drm_connector *connector; 773 struct drm_connector_list_iter conn_iter; 774 u8 proto, depth; 775 int slots; 776 bool r; 777 778 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 779 drm_for_each_connector_iter(connector, &conn_iter) { 780 if (connector->state->best_encoder == &msto->encoder) { 781 mstc = nv50_mstc(connector); 782 mstm = mstc->mstm; 783 break; 784 } 785 } 786 drm_connector_list_iter_end(&conn_iter); 787 788 if (WARN_ON(!mstc)) 789 return; 790 791 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 792 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots); 793 WARN_ON(!r); 794 795 if (!mstm->links++) 796 nv50_outp_acquire(mstm->outp); 797 798 if (mstm->outp->link & 1) 799 proto = 0x8; 800 else 801 proto = 0x9; 802 803 switch (mstc->connector.display_info.bpc) { 804 case 6: depth = 0x2; break; 805 case 8: depth = 0x5; break; 806 case 10: 807 default: depth = 0x6; break; 808 } 809 810 mstm->outp->update(mstm->outp, head->base.index, 811 nv50_head_atom(head->base.base.state), proto, depth); 812 813 msto->head = head; 814 msto->mstc = mstc; 815 mstm->modified = true; 816 } 817 818 static void 819 nv50_msto_disable(struct drm_encoder *encoder) 820 { 821 struct nv50_msto *msto = nv50_msto(encoder); 822 struct nv50_mstc *mstc = msto->mstc; 823 struct nv50_mstm *mstm = mstc->mstm; 824 825 if (mstc->port) 826 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 827 828 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 829 mstm->modified = true; 830 if (!--mstm->links) 831 mstm->disabled = true; 832 msto->disabled = true; 833 } 834 835 static const struct drm_encoder_helper_funcs 836 nv50_msto_help = { 837 .disable = nv50_msto_disable, 838 .enable = nv50_msto_enable, 839 .atomic_check = nv50_msto_atomic_check, 840 }; 841 842 static void 843 nv50_msto_destroy(struct drm_encoder *encoder) 844 { 845 struct nv50_msto *msto = nv50_msto(encoder); 846 drm_encoder_cleanup(&msto->encoder); 847 kfree(msto); 848 } 849 850 static const struct drm_encoder_funcs 851 nv50_msto = { 852 .destroy = nv50_msto_destroy, 853 }; 854 855 static int 856 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, 857 struct nv50_msto **pmsto) 858 { 859 struct nv50_msto *msto; 860 int ret; 861 862 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) 863 return -ENOMEM; 864 865 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 866 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); 867 if (ret) { 868 kfree(*pmsto); 869 *pmsto = NULL; 870 return ret; 871 } 872 873 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 874 msto->encoder.possible_crtcs = heads; 875 return 0; 876 } 877 878 static struct drm_encoder * 879 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 880 struct drm_connector_state *connector_state) 881 { 882 struct nv50_head *head = nv50_head(connector_state->crtc); 883 struct nv50_mstc *mstc = nv50_mstc(connector); 884 if (mstc->port) { 885 struct nv50_mstm *mstm = mstc->mstm; 886 return &mstm->msto[head->base.index]->encoder; 887 } 888 return NULL; 889 } 890 891 static struct drm_encoder * 892 nv50_mstc_best_encoder(struct drm_connector *connector) 893 { 894 struct nv50_mstc *mstc = nv50_mstc(connector); 895 if (mstc->port) { 896 struct nv50_mstm *mstm = mstc->mstm; 897 return &mstm->msto[0]->encoder; 898 } 899 return NULL; 900 } 901 902 static enum drm_mode_status 903 nv50_mstc_mode_valid(struct drm_connector *connector, 904 struct drm_display_mode *mode) 905 { 906 return MODE_OK; 907 } 908 909 static int 910 nv50_mstc_get_modes(struct drm_connector *connector) 911 { 912 struct nv50_mstc *mstc = nv50_mstc(connector); 913 int ret = 0; 914 915 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 916 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 917 if (mstc->edid) 918 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 919 920 if (!mstc->connector.display_info.bpc) 921 mstc->connector.display_info.bpc = 8; 922 923 if (mstc->native) 924 drm_mode_destroy(mstc->connector.dev, mstc->native); 925 mstc->native = nouveau_conn_native_mode(&mstc->connector); 926 return ret; 927 } 928 929 static const struct drm_connector_helper_funcs 930 nv50_mstc_help = { 931 .get_modes = nv50_mstc_get_modes, 932 .mode_valid = nv50_mstc_mode_valid, 933 .best_encoder = nv50_mstc_best_encoder, 934 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 935 }; 936 937 static enum drm_connector_status 938 nv50_mstc_detect(struct drm_connector *connector, bool force) 939 { 940 struct nv50_mstc *mstc = nv50_mstc(connector); 941 enum drm_connector_status conn_status; 942 int ret; 943 944 if (!mstc->port) 945 return connector_status_disconnected; 946 947 ret = pm_runtime_get_sync(connector->dev->dev); 948 if (ret < 0 && ret != -EACCES) 949 return connector_status_disconnected; 950 951 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr, 952 mstc->port); 953 954 pm_runtime_mark_last_busy(connector->dev->dev); 955 pm_runtime_put_autosuspend(connector->dev->dev); 956 return conn_status; 957 } 958 959 static void 960 nv50_mstc_destroy(struct drm_connector *connector) 961 { 962 struct nv50_mstc *mstc = nv50_mstc(connector); 963 drm_connector_cleanup(&mstc->connector); 964 kfree(mstc); 965 } 966 967 static const struct drm_connector_funcs 968 nv50_mstc = { 969 .reset = nouveau_conn_reset, 970 .detect = nv50_mstc_detect, 971 .fill_modes = drm_helper_probe_single_connector_modes, 972 .destroy = nv50_mstc_destroy, 973 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 974 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 975 .atomic_set_property = nouveau_conn_atomic_set_property, 976 .atomic_get_property = nouveau_conn_atomic_get_property, 977 }; 978 979 static int 980 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 981 const char *path, struct nv50_mstc **pmstc) 982 { 983 struct drm_device *dev = mstm->outp->base.base.dev; 984 struct nv50_mstc *mstc; 985 int ret, i; 986 987 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 988 return -ENOMEM; 989 mstc->mstm = mstm; 990 mstc->port = port; 991 992 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 993 DRM_MODE_CONNECTOR_DisplayPort); 994 if (ret) { 995 kfree(*pmstc); 996 *pmstc = NULL; 997 return ret; 998 } 999 1000 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1001 1002 mstc->connector.funcs->reset(&mstc->connector); 1003 nouveau_conn_attach_properties(&mstc->connector); 1004 1005 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) 1006 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); 1007 1008 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1009 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1010 drm_connector_set_path_property(&mstc->connector, path); 1011 return 0; 1012 } 1013 1014 static void 1015 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1016 { 1017 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1018 struct drm_encoder *encoder; 1019 int ret; 1020 1021 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1022 ret = drm_dp_check_act_status(&mstm->mgr); 1023 1024 ret = drm_dp_update_payload_part2(&mstm->mgr); 1025 1026 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1027 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1028 struct nv50_msto *msto = nv50_msto(encoder); 1029 struct nv50_mstc *mstc = msto->mstc; 1030 if (mstc && mstc->mstm == mstm) 1031 nv50_msto_cleanup(msto); 1032 } 1033 } 1034 1035 mstm->modified = false; 1036 } 1037 1038 static void 1039 nv50_mstm_prepare(struct nv50_mstm *mstm) 1040 { 1041 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1042 struct drm_encoder *encoder; 1043 int ret; 1044 1045 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1046 ret = drm_dp_update_payload_part1(&mstm->mgr); 1047 1048 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1049 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1050 struct nv50_msto *msto = nv50_msto(encoder); 1051 struct nv50_mstc *mstc = msto->mstc; 1052 if (mstc && mstc->mstm == mstm) 1053 nv50_msto_prepare(msto); 1054 } 1055 } 1056 1057 if (mstm->disabled) { 1058 if (!mstm->links) 1059 nv50_outp_release(mstm->outp); 1060 mstm->disabled = false; 1061 } 1062 } 1063 1064 static void 1065 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr) 1066 { 1067 struct nv50_mstm *mstm = nv50_mstm(mgr); 1068 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev); 1069 } 1070 1071 static void 1072 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 1073 struct drm_connector *connector) 1074 { 1075 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1076 struct nv50_mstc *mstc = nv50_mstc(connector); 1077 1078 drm_connector_unregister(&mstc->connector); 1079 1080 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 1081 1082 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL); 1083 mstc->port = NULL; 1084 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex); 1085 1086 drm_connector_put(&mstc->connector); 1087 } 1088 1089 static void 1090 nv50_mstm_register_connector(struct drm_connector *connector) 1091 { 1092 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1093 1094 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 1095 1096 drm_connector_register(connector); 1097 } 1098 1099 static struct drm_connector * 1100 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1101 struct drm_dp_mst_port *port, const char *path) 1102 { 1103 struct nv50_mstm *mstm = nv50_mstm(mgr); 1104 struct nv50_mstc *mstc; 1105 int ret; 1106 1107 ret = nv50_mstc_new(mstm, port, path, &mstc); 1108 if (ret) { 1109 if (mstc) 1110 mstc->connector.funcs->destroy(&mstc->connector); 1111 return NULL; 1112 } 1113 1114 return &mstc->connector; 1115 } 1116 1117 static const struct drm_dp_mst_topology_cbs 1118 nv50_mstm = { 1119 .add_connector = nv50_mstm_add_connector, 1120 .register_connector = nv50_mstm_register_connector, 1121 .destroy_connector = nv50_mstm_destroy_connector, 1122 .hotplug = nv50_mstm_hotplug, 1123 }; 1124 1125 void 1126 nv50_mstm_service(struct nv50_mstm *mstm) 1127 { 1128 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1129 bool handled = true; 1130 int ret; 1131 u8 esi[8] = {}; 1132 1133 if (!aux) 1134 return; 1135 1136 while (handled) { 1137 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1138 if (ret != 8) { 1139 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1140 return; 1141 } 1142 1143 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1144 if (!handled) 1145 break; 1146 1147 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1148 } 1149 } 1150 1151 void 1152 nv50_mstm_remove(struct nv50_mstm *mstm) 1153 { 1154 if (mstm) 1155 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1156 } 1157 1158 static int 1159 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1160 { 1161 struct nouveau_encoder *outp = mstm->outp; 1162 struct { 1163 struct nv50_disp_mthd_v1 base; 1164 struct nv50_disp_sor_dp_mst_link_v0 mst; 1165 } args = { 1166 .base.version = 1, 1167 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1168 .base.hasht = outp->dcb->hasht, 1169 .base.hashm = outp->dcb->hashm, 1170 .mst.state = state, 1171 }; 1172 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1173 struct nvif_object *disp = &drm->display->disp.object; 1174 int ret; 1175 1176 if (dpcd >= 0x12) { 1177 /* Even if we're enabling MST, start with disabling the 1178 * branching unit to clear any sink-side MST topology state 1179 * that wasn't set by us 1180 */ 1181 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1182 if (ret < 0) 1183 return ret; 1184 1185 if (state) { 1186 /* Now, start initializing */ 1187 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1188 DP_MST_EN); 1189 if (ret < 0) 1190 return ret; 1191 } 1192 } 1193 1194 return nvif_mthd(disp, 0, &args, sizeof(args)); 1195 } 1196 1197 int 1198 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1199 { 1200 struct drm_dp_aux *aux; 1201 int ret; 1202 bool old_state, new_state; 1203 u8 mstm_ctrl; 1204 1205 if (!mstm) 1206 return 0; 1207 1208 mutex_lock(&mstm->mgr.lock); 1209 1210 old_state = mstm->mgr.mst_state; 1211 new_state = old_state; 1212 aux = mstm->mgr.aux; 1213 1214 if (old_state) { 1215 /* Just check that the MST hub is still as we expect it */ 1216 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1217 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1218 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1219 new_state = false; 1220 } 1221 } else if (dpcd[0] >= 0x12) { 1222 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1223 if (ret < 0) 1224 goto probe_error; 1225 1226 if (!(dpcd[1] & DP_MST_CAP)) 1227 dpcd[0] = 0x11; 1228 else 1229 new_state = allow; 1230 } 1231 1232 if (new_state == old_state) { 1233 mutex_unlock(&mstm->mgr.lock); 1234 return new_state; 1235 } 1236 1237 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1238 if (ret) 1239 goto probe_error; 1240 1241 mutex_unlock(&mstm->mgr.lock); 1242 1243 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1244 if (ret) 1245 return nv50_mstm_enable(mstm, dpcd[0], 0); 1246 1247 return new_state; 1248 1249 probe_error: 1250 mutex_unlock(&mstm->mgr.lock); 1251 return ret; 1252 } 1253 1254 static void 1255 nv50_mstm_fini(struct nv50_mstm *mstm) 1256 { 1257 if (mstm && mstm->mgr.mst_state) 1258 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1259 } 1260 1261 static void 1262 nv50_mstm_init(struct nv50_mstm *mstm) 1263 { 1264 if (mstm && mstm->mgr.mst_state) 1265 drm_dp_mst_topology_mgr_resume(&mstm->mgr); 1266 } 1267 1268 static void 1269 nv50_mstm_del(struct nv50_mstm **pmstm) 1270 { 1271 struct nv50_mstm *mstm = *pmstm; 1272 if (mstm) { 1273 kfree(*pmstm); 1274 *pmstm = NULL; 1275 } 1276 } 1277 1278 static int 1279 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1280 int conn_base_id, struct nv50_mstm **pmstm) 1281 { 1282 const int max_payloads = hweight8(outp->dcb->heads); 1283 struct drm_device *dev = outp->base.base.dev; 1284 struct nv50_mstm *mstm; 1285 int ret, i; 1286 u8 dpcd; 1287 1288 /* This is a workaround for some monitors not functioning 1289 * correctly in MST mode on initial module load. I think 1290 * some bad interaction with the VBIOS may be responsible. 1291 * 1292 * A good ol' off and on again seems to work here ;) 1293 */ 1294 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1295 if (ret >= 0 && dpcd >= 0x12) 1296 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1297 1298 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1299 return -ENOMEM; 1300 mstm->outp = outp; 1301 mstm->mgr.cbs = &nv50_mstm; 1302 1303 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1304 max_payloads, conn_base_id); 1305 if (ret) 1306 return ret; 1307 1308 for (i = 0; i < max_payloads; i++) { 1309 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, 1310 i, &mstm->msto[i]); 1311 if (ret) 1312 return ret; 1313 } 1314 1315 return 0; 1316 } 1317 1318 /****************************************************************************** 1319 * SOR 1320 *****************************************************************************/ 1321 static void 1322 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1323 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1324 { 1325 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1326 struct nv50_core *core = disp->core; 1327 1328 if (!asyh) { 1329 nv_encoder->ctrl &= ~BIT(head); 1330 if (!(nv_encoder->ctrl & 0x0000000f)) 1331 nv_encoder->ctrl = 0; 1332 } else { 1333 nv_encoder->ctrl |= proto << 8; 1334 nv_encoder->ctrl |= BIT(head); 1335 asyh->or.depth = depth; 1336 } 1337 1338 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1339 } 1340 1341 static void 1342 nv50_sor_disable(struct drm_encoder *encoder) 1343 { 1344 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1345 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1346 1347 nv_encoder->crtc = NULL; 1348 1349 if (nv_crtc) { 1350 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1351 u8 pwr; 1352 1353 if (aux) { 1354 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1355 if (ret == 0) { 1356 pwr &= ~DP_SET_POWER_MASK; 1357 pwr |= DP_SET_POWER_D3; 1358 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1359 } 1360 } 1361 1362 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1363 nv50_audio_disable(encoder, nv_crtc); 1364 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1365 nv50_outp_release(nv_encoder); 1366 } 1367 } 1368 1369 static void 1370 nv50_sor_enable(struct drm_encoder *encoder) 1371 { 1372 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1373 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1374 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1375 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1376 struct { 1377 struct nv50_disp_mthd_v1 base; 1378 struct nv50_disp_sor_lvds_script_v0 lvds; 1379 } lvds = { 1380 .base.version = 1, 1381 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1382 .base.hasht = nv_encoder->dcb->hasht, 1383 .base.hashm = nv_encoder->dcb->hashm, 1384 }; 1385 struct nv50_disp *disp = nv50_disp(encoder->dev); 1386 struct drm_device *dev = encoder->dev; 1387 struct nouveau_drm *drm = nouveau_drm(dev); 1388 struct nouveau_connector *nv_connector; 1389 struct nvbios *bios = &drm->vbios; 1390 u8 proto = 0xf; 1391 u8 depth = 0x0; 1392 1393 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1394 nv_encoder->crtc = encoder->crtc; 1395 nv50_outp_acquire(nv_encoder); 1396 1397 switch (nv_encoder->dcb->type) { 1398 case DCB_OUTPUT_TMDS: 1399 if (nv_encoder->link & 1) { 1400 proto = 0x1; 1401 /* Only enable dual-link if: 1402 * - Need to (i.e. rate > 165MHz) 1403 * - DCB says we can 1404 * - Not an HDMI monitor, since there's no dual-link 1405 * on HDMI. 1406 */ 1407 if (mode->clock >= 165000 && 1408 nv_encoder->dcb->duallink_possible && 1409 !drm_detect_hdmi_monitor(nv_connector->edid)) 1410 proto |= 0x4; 1411 } else { 1412 proto = 0x2; 1413 } 1414 1415 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1416 break; 1417 case DCB_OUTPUT_LVDS: 1418 proto = 0x0; 1419 1420 if (bios->fp_no_ddc) { 1421 if (bios->fp.dual_link) 1422 lvds.lvds.script |= 0x0100; 1423 if (bios->fp.if_is_24bit) 1424 lvds.lvds.script |= 0x0200; 1425 } else { 1426 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1427 if (((u8 *)nv_connector->edid)[121] == 2) 1428 lvds.lvds.script |= 0x0100; 1429 } else 1430 if (mode->clock >= bios->fp.duallink_transition_clk) { 1431 lvds.lvds.script |= 0x0100; 1432 } 1433 1434 if (lvds.lvds.script & 0x0100) { 1435 if (bios->fp.strapless_is_24bit & 2) 1436 lvds.lvds.script |= 0x0200; 1437 } else { 1438 if (bios->fp.strapless_is_24bit & 1) 1439 lvds.lvds.script |= 0x0200; 1440 } 1441 1442 if (nv_connector->base.display_info.bpc == 8) 1443 lvds.lvds.script |= 0x0200; 1444 } 1445 1446 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1447 break; 1448 case DCB_OUTPUT_DP: 1449 if (nv_connector->base.display_info.bpc == 6) 1450 depth = 0x2; 1451 else 1452 if (nv_connector->base.display_info.bpc == 8) 1453 depth = 0x5; 1454 else 1455 depth = 0x6; 1456 1457 if (nv_encoder->link & 1) 1458 proto = 0x8; 1459 else 1460 proto = 0x9; 1461 1462 nv50_audio_enable(encoder, mode); 1463 break; 1464 default: 1465 BUG(); 1466 break; 1467 } 1468 1469 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1470 } 1471 1472 static const struct drm_encoder_helper_funcs 1473 nv50_sor_help = { 1474 .atomic_check = nv50_outp_atomic_check, 1475 .enable = nv50_sor_enable, 1476 .disable = nv50_sor_disable, 1477 }; 1478 1479 static void 1480 nv50_sor_destroy(struct drm_encoder *encoder) 1481 { 1482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1483 nv50_mstm_del(&nv_encoder->dp.mstm); 1484 drm_encoder_cleanup(encoder); 1485 kfree(encoder); 1486 } 1487 1488 static const struct drm_encoder_funcs 1489 nv50_sor_func = { 1490 .destroy = nv50_sor_destroy, 1491 }; 1492 1493 static int 1494 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1495 { 1496 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1497 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1498 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1499 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1500 struct nouveau_encoder *nv_encoder; 1501 struct drm_encoder *encoder; 1502 u8 ver, hdr, cnt, len; 1503 u32 data; 1504 int type, ret; 1505 1506 switch (dcbe->type) { 1507 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1508 case DCB_OUTPUT_TMDS: 1509 case DCB_OUTPUT_DP: 1510 default: 1511 type = DRM_MODE_ENCODER_TMDS; 1512 break; 1513 } 1514 1515 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1516 if (!nv_encoder) 1517 return -ENOMEM; 1518 nv_encoder->dcb = dcbe; 1519 nv_encoder->update = nv50_sor_update; 1520 1521 encoder = to_drm_encoder(nv_encoder); 1522 encoder->possible_crtcs = dcbe->heads; 1523 encoder->possible_clones = 0; 1524 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1525 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1526 drm_encoder_helper_add(encoder, &nv50_sor_help); 1527 1528 drm_connector_attach_encoder(connector, encoder); 1529 1530 if (dcbe->type == DCB_OUTPUT_DP) { 1531 struct nv50_disp *disp = nv50_disp(encoder->dev); 1532 struct nvkm_i2c_aux *aux = 1533 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1534 if (aux) { 1535 if (disp->disp->object.oclass < GF110_DISP) { 1536 /* HW has no support for address-only 1537 * transactions, so we're required to 1538 * use custom I2C-over-AUX code. 1539 */ 1540 nv_encoder->i2c = &aux->i2c; 1541 } else { 1542 nv_encoder->i2c = &nv_connector->aux.ddc; 1543 } 1544 nv_encoder->aux = aux; 1545 } 1546 1547 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && 1548 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) { 1549 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, 1550 nv_connector->base.base.id, 1551 &nv_encoder->dp.mstm); 1552 if (ret) 1553 return ret; 1554 } 1555 } else { 1556 struct nvkm_i2c_bus *bus = 1557 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1558 if (bus) 1559 nv_encoder->i2c = &bus->i2c; 1560 } 1561 1562 return 0; 1563 } 1564 1565 /****************************************************************************** 1566 * PIOR 1567 *****************************************************************************/ 1568 static int 1569 nv50_pior_atomic_check(struct drm_encoder *encoder, 1570 struct drm_crtc_state *crtc_state, 1571 struct drm_connector_state *conn_state) 1572 { 1573 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1574 if (ret) 1575 return ret; 1576 crtc_state->adjusted_mode.clock *= 2; 1577 return 0; 1578 } 1579 1580 static void 1581 nv50_pior_disable(struct drm_encoder *encoder) 1582 { 1583 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1584 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1585 if (nv_encoder->crtc) 1586 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1587 nv_encoder->crtc = NULL; 1588 nv50_outp_release(nv_encoder); 1589 } 1590 1591 static void 1592 nv50_pior_enable(struct drm_encoder *encoder) 1593 { 1594 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1595 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1596 struct nouveau_connector *nv_connector; 1597 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1598 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1599 u8 owner = 1 << nv_crtc->index; 1600 u8 proto; 1601 1602 nv50_outp_acquire(nv_encoder); 1603 1604 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1605 switch (nv_connector->base.display_info.bpc) { 1606 case 10: asyh->or.depth = 0x6; break; 1607 case 8: asyh->or.depth = 0x5; break; 1608 case 6: asyh->or.depth = 0x2; break; 1609 default: asyh->or.depth = 0x0; break; 1610 } 1611 1612 switch (nv_encoder->dcb->type) { 1613 case DCB_OUTPUT_TMDS: 1614 case DCB_OUTPUT_DP: 1615 proto = 0x0; 1616 break; 1617 default: 1618 BUG(); 1619 break; 1620 } 1621 1622 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1623 nv_encoder->crtc = encoder->crtc; 1624 } 1625 1626 static const struct drm_encoder_helper_funcs 1627 nv50_pior_help = { 1628 .atomic_check = nv50_pior_atomic_check, 1629 .enable = nv50_pior_enable, 1630 .disable = nv50_pior_disable, 1631 }; 1632 1633 static void 1634 nv50_pior_destroy(struct drm_encoder *encoder) 1635 { 1636 drm_encoder_cleanup(encoder); 1637 kfree(encoder); 1638 } 1639 1640 static const struct drm_encoder_funcs 1641 nv50_pior_func = { 1642 .destroy = nv50_pior_destroy, 1643 }; 1644 1645 static int 1646 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1647 { 1648 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1649 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1650 struct nvkm_i2c_bus *bus = NULL; 1651 struct nvkm_i2c_aux *aux = NULL; 1652 struct i2c_adapter *ddc; 1653 struct nouveau_encoder *nv_encoder; 1654 struct drm_encoder *encoder; 1655 int type; 1656 1657 switch (dcbe->type) { 1658 case DCB_OUTPUT_TMDS: 1659 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1660 ddc = bus ? &bus->i2c : NULL; 1661 type = DRM_MODE_ENCODER_TMDS; 1662 break; 1663 case DCB_OUTPUT_DP: 1664 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1665 ddc = aux ? &aux->i2c : NULL; 1666 type = DRM_MODE_ENCODER_TMDS; 1667 break; 1668 default: 1669 return -ENODEV; 1670 } 1671 1672 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1673 if (!nv_encoder) 1674 return -ENOMEM; 1675 nv_encoder->dcb = dcbe; 1676 nv_encoder->i2c = ddc; 1677 nv_encoder->aux = aux; 1678 1679 encoder = to_drm_encoder(nv_encoder); 1680 encoder->possible_crtcs = dcbe->heads; 1681 encoder->possible_clones = 0; 1682 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1683 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1684 drm_encoder_helper_add(encoder, &nv50_pior_help); 1685 1686 drm_connector_attach_encoder(connector, encoder); 1687 return 0; 1688 } 1689 1690 /****************************************************************************** 1691 * Atomic 1692 *****************************************************************************/ 1693 1694 static void 1695 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1696 { 1697 struct nouveau_drm *drm = nouveau_drm(state->dev); 1698 struct nv50_disp *disp = nv50_disp(drm->dev); 1699 struct nv50_core *core = disp->core; 1700 struct nv50_mstm *mstm; 1701 struct drm_encoder *encoder; 1702 1703 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1704 1705 drm_for_each_encoder(encoder, drm->dev) { 1706 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1707 mstm = nouveau_encoder(encoder)->dp.mstm; 1708 if (mstm && mstm->modified) 1709 nv50_mstm_prepare(mstm); 1710 } 1711 } 1712 1713 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1714 core->func->update(core, interlock, true); 1715 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1716 disp->core->chan.base.device)) 1717 NV_ERROR(drm, "core notifier timeout\n"); 1718 1719 drm_for_each_encoder(encoder, drm->dev) { 1720 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1721 mstm = nouveau_encoder(encoder)->dp.mstm; 1722 if (mstm && mstm->modified) 1723 nv50_mstm_cleanup(mstm); 1724 } 1725 } 1726 } 1727 1728 static void 1729 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1730 { 1731 struct drm_plane_state *new_plane_state; 1732 struct drm_plane *plane; 1733 int i; 1734 1735 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1736 struct nv50_wndw *wndw = nv50_wndw(plane); 1737 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1738 if (wndw->func->update) 1739 wndw->func->update(wndw, interlock); 1740 } 1741 } 1742 } 1743 1744 static void 1745 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1746 { 1747 struct drm_device *dev = state->dev; 1748 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1749 struct drm_crtc *crtc; 1750 struct drm_plane_state *new_plane_state; 1751 struct drm_plane *plane; 1752 struct nouveau_drm *drm = nouveau_drm(dev); 1753 struct nv50_disp *disp = nv50_disp(dev); 1754 struct nv50_atom *atom = nv50_atom(state); 1755 struct nv50_outp_atom *outp, *outt; 1756 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1757 int i; 1758 1759 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1760 drm_atomic_helper_wait_for_fences(dev, state, false); 1761 drm_atomic_helper_wait_for_dependencies(state); 1762 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1763 1764 if (atom->lock_core) 1765 mutex_lock(&disp->mutex); 1766 1767 /* Disable head(s). */ 1768 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1769 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1770 struct nv50_head *head = nv50_head(crtc); 1771 1772 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1773 asyh->clr.mask, asyh->set.mask); 1774 if (old_crtc_state->active && !new_crtc_state->active) 1775 drm_crtc_vblank_off(crtc); 1776 1777 if (asyh->clr.mask) { 1778 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1779 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1780 } 1781 } 1782 1783 /* Disable plane(s). */ 1784 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1785 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1786 struct nv50_wndw *wndw = nv50_wndw(plane); 1787 1788 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1789 asyw->clr.mask, asyw->set.mask); 1790 if (!asyw->clr.mask) 1791 continue; 1792 1793 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1794 } 1795 1796 /* Disable output path(s). */ 1797 list_for_each_entry(outp, &atom->outp, head) { 1798 const struct drm_encoder_helper_funcs *help; 1799 struct drm_encoder *encoder; 1800 1801 encoder = outp->encoder; 1802 help = encoder->helper_private; 1803 1804 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1805 outp->clr.mask, outp->set.mask); 1806 1807 if (outp->clr.mask) { 1808 help->disable(encoder); 1809 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1810 if (outp->flush_disable) { 1811 nv50_disp_atomic_commit_wndw(state, interlock); 1812 nv50_disp_atomic_commit_core(state, interlock); 1813 memset(interlock, 0x00, sizeof(interlock)); 1814 } 1815 } 1816 } 1817 1818 /* Flush disable. */ 1819 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1820 if (atom->flush_disable) { 1821 nv50_disp_atomic_commit_wndw(state, interlock); 1822 nv50_disp_atomic_commit_core(state, interlock); 1823 memset(interlock, 0x00, sizeof(interlock)); 1824 } 1825 } 1826 1827 /* Update output path(s). */ 1828 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1829 const struct drm_encoder_helper_funcs *help; 1830 struct drm_encoder *encoder; 1831 1832 encoder = outp->encoder; 1833 help = encoder->helper_private; 1834 1835 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 1836 outp->set.mask, outp->clr.mask); 1837 1838 if (outp->set.mask) { 1839 help->enable(encoder); 1840 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1841 } 1842 1843 list_del(&outp->head); 1844 kfree(outp); 1845 } 1846 1847 /* Update head(s). */ 1848 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1849 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1850 struct nv50_head *head = nv50_head(crtc); 1851 1852 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 1853 asyh->set.mask, asyh->clr.mask); 1854 1855 if (asyh->set.mask) { 1856 nv50_head_flush_set(head, asyh); 1857 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1858 } 1859 1860 if (new_crtc_state->active) { 1861 if (!old_crtc_state->active) 1862 drm_crtc_vblank_on(crtc); 1863 if (new_crtc_state->event) 1864 drm_crtc_vblank_get(crtc); 1865 } 1866 } 1867 1868 /* Update plane(s). */ 1869 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1870 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1871 struct nv50_wndw *wndw = nv50_wndw(plane); 1872 1873 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 1874 asyw->set.mask, asyw->clr.mask); 1875 if ( !asyw->set.mask && 1876 (!asyw->clr.mask || atom->flush_disable)) 1877 continue; 1878 1879 nv50_wndw_flush_set(wndw, interlock, asyw); 1880 } 1881 1882 /* Flush update. */ 1883 nv50_disp_atomic_commit_wndw(state, interlock); 1884 1885 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1886 if (interlock[NV50_DISP_INTERLOCK_BASE] || 1887 interlock[NV50_DISP_INTERLOCK_OVLY] || 1888 interlock[NV50_DISP_INTERLOCK_WNDW] || 1889 !atom->state.legacy_cursor_update) 1890 nv50_disp_atomic_commit_core(state, interlock); 1891 else 1892 disp->core->func->update(disp->core, interlock, false); 1893 } 1894 1895 if (atom->lock_core) 1896 mutex_unlock(&disp->mutex); 1897 1898 /* Wait for HW to signal completion. */ 1899 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1900 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1901 struct nv50_wndw *wndw = nv50_wndw(plane); 1902 int ret = nv50_wndw_wait_armed(wndw, asyw); 1903 if (ret) 1904 NV_ERROR(drm, "%s: timeout\n", plane->name); 1905 } 1906 1907 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 1908 if (new_crtc_state->event) { 1909 unsigned long flags; 1910 /* Get correct count/ts if racing with vblank irq */ 1911 if (new_crtc_state->active) 1912 drm_crtc_accurate_vblank_count(crtc); 1913 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1914 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 1915 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1916 1917 new_crtc_state->event = NULL; 1918 if (new_crtc_state->active) 1919 drm_crtc_vblank_put(crtc); 1920 } 1921 } 1922 1923 drm_atomic_helper_commit_hw_done(state); 1924 drm_atomic_helper_cleanup_planes(dev, state); 1925 drm_atomic_helper_commit_cleanup_done(state); 1926 drm_atomic_state_put(state); 1927 } 1928 1929 static void 1930 nv50_disp_atomic_commit_work(struct work_struct *work) 1931 { 1932 struct drm_atomic_state *state = 1933 container_of(work, typeof(*state), commit_work); 1934 nv50_disp_atomic_commit_tail(state); 1935 } 1936 1937 static int 1938 nv50_disp_atomic_commit(struct drm_device *dev, 1939 struct drm_atomic_state *state, bool nonblock) 1940 { 1941 struct nouveau_drm *drm = nouveau_drm(dev); 1942 struct drm_plane_state *new_plane_state; 1943 struct drm_plane *plane; 1944 struct drm_crtc *crtc; 1945 bool active = false; 1946 int ret, i; 1947 1948 ret = pm_runtime_get_sync(dev->dev); 1949 if (ret < 0 && ret != -EACCES) 1950 return ret; 1951 1952 ret = drm_atomic_helper_setup_commit(state, nonblock); 1953 if (ret) 1954 goto done; 1955 1956 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 1957 1958 ret = drm_atomic_helper_prepare_planes(dev, state); 1959 if (ret) 1960 goto done; 1961 1962 if (!nonblock) { 1963 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 1964 if (ret) 1965 goto err_cleanup; 1966 } 1967 1968 ret = drm_atomic_helper_swap_state(state, true); 1969 if (ret) 1970 goto err_cleanup; 1971 1972 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1973 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1974 struct nv50_wndw *wndw = nv50_wndw(plane); 1975 1976 if (asyw->set.image) 1977 nv50_wndw_ntfy_enable(wndw, asyw); 1978 } 1979 1980 drm_atomic_state_get(state); 1981 1982 if (nonblock) 1983 queue_work(system_unbound_wq, &state->commit_work); 1984 else 1985 nv50_disp_atomic_commit_tail(state); 1986 1987 drm_for_each_crtc(crtc, dev) { 1988 if (crtc->state->active) { 1989 if (!drm->have_disp_power_ref) { 1990 drm->have_disp_power_ref = true; 1991 return 0; 1992 } 1993 active = true; 1994 break; 1995 } 1996 } 1997 1998 if (!active && drm->have_disp_power_ref) { 1999 pm_runtime_put_autosuspend(dev->dev); 2000 drm->have_disp_power_ref = false; 2001 } 2002 2003 err_cleanup: 2004 if (ret) 2005 drm_atomic_helper_cleanup_planes(dev, state); 2006 done: 2007 pm_runtime_put_autosuspend(dev->dev); 2008 return ret; 2009 } 2010 2011 static struct nv50_outp_atom * 2012 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2013 { 2014 struct nv50_outp_atom *outp; 2015 2016 list_for_each_entry(outp, &atom->outp, head) { 2017 if (outp->encoder == encoder) 2018 return outp; 2019 } 2020 2021 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2022 if (!outp) 2023 return ERR_PTR(-ENOMEM); 2024 2025 list_add(&outp->head, &atom->outp); 2026 outp->encoder = encoder; 2027 return outp; 2028 } 2029 2030 static int 2031 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2032 struct drm_connector_state *old_connector_state) 2033 { 2034 struct drm_encoder *encoder = old_connector_state->best_encoder; 2035 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2036 struct drm_crtc *crtc; 2037 struct nv50_outp_atom *outp; 2038 2039 if (!(crtc = old_connector_state->crtc)) 2040 return 0; 2041 2042 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2043 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2044 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2045 outp = nv50_disp_outp_atomic_add(atom, encoder); 2046 if (IS_ERR(outp)) 2047 return PTR_ERR(outp); 2048 2049 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2050 outp->flush_disable = true; 2051 atom->flush_disable = true; 2052 } 2053 outp->clr.ctrl = true; 2054 atom->lock_core = true; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static int 2061 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2062 struct drm_connector_state *connector_state) 2063 { 2064 struct drm_encoder *encoder = connector_state->best_encoder; 2065 struct drm_crtc_state *new_crtc_state; 2066 struct drm_crtc *crtc; 2067 struct nv50_outp_atom *outp; 2068 2069 if (!(crtc = connector_state->crtc)) 2070 return 0; 2071 2072 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2073 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2074 outp = nv50_disp_outp_atomic_add(atom, encoder); 2075 if (IS_ERR(outp)) 2076 return PTR_ERR(outp); 2077 2078 outp->set.ctrl = true; 2079 atom->lock_core = true; 2080 } 2081 2082 return 0; 2083 } 2084 2085 static int 2086 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2087 { 2088 struct nv50_atom *atom = nv50_atom(state); 2089 struct drm_connector_state *old_connector_state, *new_connector_state; 2090 struct drm_connector *connector; 2091 struct drm_crtc_state *new_crtc_state; 2092 struct drm_crtc *crtc; 2093 int ret, i; 2094 2095 /* We need to handle colour management on a per-plane basis. */ 2096 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2097 if (new_crtc_state->color_mgmt_changed) { 2098 ret = drm_atomic_add_affected_planes(state, crtc); 2099 if (ret) 2100 return ret; 2101 } 2102 } 2103 2104 ret = drm_atomic_helper_check(dev, state); 2105 if (ret) 2106 return ret; 2107 2108 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2109 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2110 if (ret) 2111 return ret; 2112 2113 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2114 if (ret) 2115 return ret; 2116 } 2117 2118 return 0; 2119 } 2120 2121 static void 2122 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2123 { 2124 struct nv50_atom *atom = nv50_atom(state); 2125 struct nv50_outp_atom *outp, *outt; 2126 2127 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2128 list_del(&outp->head); 2129 kfree(outp); 2130 } 2131 2132 drm_atomic_state_default_clear(state); 2133 } 2134 2135 static void 2136 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2137 { 2138 struct nv50_atom *atom = nv50_atom(state); 2139 drm_atomic_state_default_release(&atom->state); 2140 kfree(atom); 2141 } 2142 2143 static struct drm_atomic_state * 2144 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2145 { 2146 struct nv50_atom *atom; 2147 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2148 drm_atomic_state_init(dev, &atom->state) < 0) { 2149 kfree(atom); 2150 return NULL; 2151 } 2152 INIT_LIST_HEAD(&atom->outp); 2153 return &atom->state; 2154 } 2155 2156 static const struct drm_mode_config_funcs 2157 nv50_disp_func = { 2158 .fb_create = nouveau_user_framebuffer_create, 2159 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2160 .atomic_check = nv50_disp_atomic_check, 2161 .atomic_commit = nv50_disp_atomic_commit, 2162 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2163 .atomic_state_clear = nv50_disp_atomic_state_clear, 2164 .atomic_state_free = nv50_disp_atomic_state_free, 2165 }; 2166 2167 /****************************************************************************** 2168 * Init 2169 *****************************************************************************/ 2170 2171 void 2172 nv50_display_fini(struct drm_device *dev) 2173 { 2174 struct nouveau_encoder *nv_encoder; 2175 struct drm_encoder *encoder; 2176 struct drm_plane *plane; 2177 2178 drm_for_each_plane(plane, dev) { 2179 struct nv50_wndw *wndw = nv50_wndw(plane); 2180 if (plane->funcs != &nv50_wndw) 2181 continue; 2182 nv50_wndw_fini(wndw); 2183 } 2184 2185 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2186 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2187 nv_encoder = nouveau_encoder(encoder); 2188 nv50_mstm_fini(nv_encoder->dp.mstm); 2189 } 2190 } 2191 } 2192 2193 int 2194 nv50_display_init(struct drm_device *dev) 2195 { 2196 struct nv50_core *core = nv50_disp(dev)->core; 2197 struct drm_encoder *encoder; 2198 struct drm_plane *plane; 2199 2200 core->func->init(core); 2201 2202 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2203 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2204 struct nouveau_encoder *nv_encoder = 2205 nouveau_encoder(encoder); 2206 nv50_mstm_init(nv_encoder->dp.mstm); 2207 } 2208 } 2209 2210 drm_for_each_plane(plane, dev) { 2211 struct nv50_wndw *wndw = nv50_wndw(plane); 2212 if (plane->funcs != &nv50_wndw) 2213 continue; 2214 nv50_wndw_init(wndw); 2215 } 2216 2217 return 0; 2218 } 2219 2220 void 2221 nv50_display_destroy(struct drm_device *dev) 2222 { 2223 struct nv50_disp *disp = nv50_disp(dev); 2224 2225 nv50_core_del(&disp->core); 2226 2227 nouveau_bo_unmap(disp->sync); 2228 if (disp->sync) 2229 nouveau_bo_unpin(disp->sync); 2230 nouveau_bo_ref(NULL, &disp->sync); 2231 2232 nouveau_display(dev)->priv = NULL; 2233 kfree(disp); 2234 } 2235 2236 int 2237 nv50_display_create(struct drm_device *dev) 2238 { 2239 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2240 struct nouveau_drm *drm = nouveau_drm(dev); 2241 struct dcb_table *dcb = &drm->vbios.dcb; 2242 struct drm_connector *connector, *tmp; 2243 struct nv50_disp *disp; 2244 struct dcb_output *dcbe; 2245 int crtcs, ret, i; 2246 2247 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2248 if (!disp) 2249 return -ENOMEM; 2250 2251 mutex_init(&disp->mutex); 2252 2253 nouveau_display(dev)->priv = disp; 2254 nouveau_display(dev)->dtor = nv50_display_destroy; 2255 nouveau_display(dev)->init = nv50_display_init; 2256 nouveau_display(dev)->fini = nv50_display_fini; 2257 disp->disp = &nouveau_display(dev)->disp; 2258 dev->mode_config.funcs = &nv50_disp_func; 2259 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2260 2261 /* small shared memory area we use for notifiers and semaphores */ 2262 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2263 0, 0x0000, NULL, NULL, &disp->sync); 2264 if (!ret) { 2265 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2266 if (!ret) { 2267 ret = nouveau_bo_map(disp->sync); 2268 if (ret) 2269 nouveau_bo_unpin(disp->sync); 2270 } 2271 if (ret) 2272 nouveau_bo_ref(NULL, &disp->sync); 2273 } 2274 2275 if (ret) 2276 goto out; 2277 2278 /* allocate master evo channel */ 2279 ret = nv50_core_new(drm, &disp->core); 2280 if (ret) 2281 goto out; 2282 2283 /* create crtc objects to represent the hw heads */ 2284 if (disp->disp->object.oclass >= GV100_DISP) 2285 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2286 else 2287 if (disp->disp->object.oclass >= GF110_DISP) 2288 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2289 else 2290 crtcs = 0x3; 2291 2292 for (i = 0; i < fls(crtcs); i++) { 2293 if (!(crtcs & (1 << i))) 2294 continue; 2295 ret = nv50_head_create(dev, i); 2296 if (ret) 2297 goto out; 2298 } 2299 2300 /* create encoder/connector objects based on VBIOS DCB table */ 2301 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2302 connector = nouveau_connector_create(dev, dcbe->connector); 2303 if (IS_ERR(connector)) 2304 continue; 2305 2306 if (dcbe->location == DCB_LOC_ON_CHIP) { 2307 switch (dcbe->type) { 2308 case DCB_OUTPUT_TMDS: 2309 case DCB_OUTPUT_LVDS: 2310 case DCB_OUTPUT_DP: 2311 ret = nv50_sor_create(connector, dcbe); 2312 break; 2313 case DCB_OUTPUT_ANALOG: 2314 ret = nv50_dac_create(connector, dcbe); 2315 break; 2316 default: 2317 ret = -ENODEV; 2318 break; 2319 } 2320 } else { 2321 ret = nv50_pior_create(connector, dcbe); 2322 } 2323 2324 if (ret) { 2325 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2326 dcbe->location, dcbe->type, 2327 ffs(dcbe->or) - 1, ret); 2328 ret = 0; 2329 } 2330 } 2331 2332 /* cull any connectors we created that don't have an encoder */ 2333 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2334 if (connector->encoder_ids[0]) 2335 continue; 2336 2337 NV_WARN(drm, "%s has no encoders, removing\n", 2338 connector->name); 2339 connector->funcs->destroy(connector); 2340 } 2341 2342 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2343 dev->vblank_disable_immediate = true; 2344 2345 out: 2346 if (ret) 2347 nv50_display_destroy(dev); 2348 return ret; 2349 } 2350