1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 35 #include <drm/drm_atomic.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_fb_helper.h> 40 #include <drm/drm_plane_helper.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_scdc_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #include <nvif/push507c.h> 46 47 #include <nvif/class.h> 48 #include <nvif/cl0002.h> 49 #include <nvif/cl5070.h> 50 #include <nvif/cl507d.h> 51 #include <nvif/event.h> 52 #include <nvif/timer.h> 53 54 #include <nvhw/class/cl507c.h> 55 #include <nvhw/class/cl507d.h> 56 #include <nvhw/class/cl837d.h> 57 #include <nvhw/class/cl887d.h> 58 #include <nvhw/class/cl907d.h> 59 #include <nvhw/class/cl917d.h> 60 61 #include "nouveau_drv.h" 62 #include "nouveau_dma.h" 63 #include "nouveau_gem.h" 64 #include "nouveau_connector.h" 65 #include "nouveau_encoder.h" 66 #include "nouveau_fence.h" 67 #include "nouveau_fbcon.h" 68 69 #include <subdev/bios/dp.h> 70 71 /****************************************************************************** 72 * EVO channel 73 *****************************************************************************/ 74 75 static int 76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 77 const s32 *oclass, u8 head, void *data, u32 size, 78 struct nv50_chan *chan) 79 { 80 struct nvif_sclass *sclass; 81 int ret, i, n; 82 83 chan->device = device; 84 85 ret = n = nvif_object_sclass_get(disp, &sclass); 86 if (ret < 0) 87 return ret; 88 89 while (oclass[0]) { 90 for (i = 0; i < n; i++) { 91 if (sclass[i].oclass == oclass[0]) { 92 ret = nvif_object_ctor(disp, "kmsChan", 0, 93 oclass[0], data, size, 94 &chan->user); 95 if (ret == 0) 96 nvif_object_map(&chan->user, NULL, 0); 97 nvif_object_sclass_put(&sclass); 98 return ret; 99 } 100 } 101 oclass++; 102 } 103 104 nvif_object_sclass_put(&sclass); 105 return -ENOSYS; 106 } 107 108 static void 109 nv50_chan_destroy(struct nv50_chan *chan) 110 { 111 nvif_object_dtor(&chan->user); 112 } 113 114 /****************************************************************************** 115 * DMA EVO channel 116 *****************************************************************************/ 117 118 void 119 nv50_dmac_destroy(struct nv50_dmac *dmac) 120 { 121 nvif_object_dtor(&dmac->vram); 122 nvif_object_dtor(&dmac->sync); 123 124 nv50_chan_destroy(&dmac->base); 125 126 nvif_mem_dtor(&dmac->_push.mem); 127 } 128 129 static void 130 nv50_dmac_kick(struct nvif_push *push) 131 { 132 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 133 134 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 135 if (dmac->put != dmac->cur) { 136 /* Push buffer fetches are not coherent with BAR1, we need to ensure 137 * writes have been flushed right through to VRAM before writing PUT. 138 */ 139 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 140 struct nvif_device *device = dmac->base.device; 141 nvif_wr32(&device->object, 0x070000, 0x00000001); 142 nvif_msec(device, 2000, 143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 144 break; 145 ); 146 } 147 148 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 149 dmac->put = dmac->cur; 150 } 151 152 push->bgn = push->cur; 153 } 154 155 static int 156 nv50_dmac_free(struct nv50_dmac *dmac) 157 { 158 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 159 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 160 return get - dmac->cur - 5; 161 return dmac->max - dmac->cur; 162 } 163 164 static int 165 nv50_dmac_wind(struct nv50_dmac *dmac) 166 { 167 /* Wait for GET to depart from the beginning of the push buffer to 168 * prevent writing PUT == GET, which would be ignored by HW. 169 */ 170 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 171 if (get == 0) { 172 /* Corner-case, HW idle, but non-committed work pending. */ 173 if (dmac->put == 0) 174 nv50_dmac_kick(dmac->push); 175 176 if (nvif_msec(dmac->base.device, 2000, 177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 178 break; 179 ) < 0) 180 return -ETIMEDOUT; 181 } 182 183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 184 dmac->cur = 0; 185 return 0; 186 } 187 188 static int 189 nv50_dmac_wait(struct nvif_push *push, u32 size) 190 { 191 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 192 int free; 193 194 if (WARN_ON(size > dmac->max)) 195 return -EINVAL; 196 197 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 198 if (dmac->cur + size >= dmac->max) { 199 int ret = nv50_dmac_wind(dmac); 200 if (ret) 201 return ret; 202 203 push->cur = dmac->_push.mem.object.map.ptr; 204 push->cur = push->cur + dmac->cur; 205 nv50_dmac_kick(push); 206 } 207 208 if (nvif_msec(dmac->base.device, 2000, 209 if ((free = nv50_dmac_free(dmac)) >= size) 210 break; 211 ) < 0) { 212 WARN_ON(1); 213 return -ETIMEDOUT; 214 } 215 216 push->bgn = dmac->_push.mem.object.map.ptr; 217 push->bgn = push->bgn + dmac->cur; 218 push->cur = push->bgn; 219 push->end = push->cur + free; 220 return 0; 221 } 222 223 int 224 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 225 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 226 struct nv50_dmac *dmac) 227 { 228 struct nouveau_cli *cli = (void *)device->object.client; 229 struct nv50_disp_core_channel_dma_v0 *args = data; 230 u8 type = NVIF_MEM_COHERENT; 231 int ret; 232 233 mutex_init(&dmac->lock); 234 235 /* Pascal added support for 47-bit physical addresses, but some 236 * parts of EVO still only accept 40-bit PAs. 237 * 238 * To avoid issues on systems with large amounts of RAM, and on 239 * systems where an IOMMU maps pages at a high address, we need 240 * to allocate push buffers in VRAM instead. 241 * 242 * This appears to match NVIDIA's behaviour on Pascal. 243 */ 244 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 245 type |= NVIF_MEM_VRAM; 246 247 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 248 &dmac->_push.mem); 249 if (ret) 250 return ret; 251 252 dmac->ptr = dmac->_push.mem.object.map.ptr; 253 dmac->_push.wait = nv50_dmac_wait; 254 dmac->_push.kick = nv50_dmac_kick; 255 dmac->push = &dmac->_push; 256 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 257 dmac->push->cur = dmac->push->bgn; 258 dmac->push->end = dmac->push->bgn; 259 dmac->max = 0x1000/4 - 1; 260 261 /* EVO channels are affected by a HW bug where the last 12 DWORDs 262 * of the push buffer aren't able to be used safely. 263 */ 264 if (disp->oclass < GV100_DISP) 265 dmac->max -= 12; 266 267 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 268 269 ret = nv50_chan_create(device, disp, oclass, head, data, size, 270 &dmac->base); 271 if (ret) 272 return ret; 273 274 if (!syncbuf) 275 return 0; 276 277 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 278 NV_DMA_IN_MEMORY, 279 &(struct nv_dma_v0) { 280 .target = NV_DMA_V0_TARGET_VRAM, 281 .access = NV_DMA_V0_ACCESS_RDWR, 282 .start = syncbuf + 0x0000, 283 .limit = syncbuf + 0x0fff, 284 }, sizeof(struct nv_dma_v0), 285 &dmac->sync); 286 if (ret) 287 return ret; 288 289 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 290 NV_DMA_IN_MEMORY, 291 &(struct nv_dma_v0) { 292 .target = NV_DMA_V0_TARGET_VRAM, 293 .access = NV_DMA_V0_ACCESS_RDWR, 294 .start = 0, 295 .limit = device->info.ram_user - 1, 296 }, sizeof(struct nv_dma_v0), 297 &dmac->vram); 298 if (ret) 299 return ret; 300 301 return ret; 302 } 303 304 /****************************************************************************** 305 * Output path helpers 306 *****************************************************************************/ 307 static void 308 nv50_outp_release(struct nouveau_encoder *nv_encoder) 309 { 310 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 311 struct { 312 struct nv50_disp_mthd_v1 base; 313 } args = { 314 .base.version = 1, 315 .base.method = NV50_DISP_MTHD_V1_RELEASE, 316 .base.hasht = nv_encoder->dcb->hasht, 317 .base.hashm = nv_encoder->dcb->hashm, 318 }; 319 320 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 321 nv_encoder->or = -1; 322 nv_encoder->link = 0; 323 } 324 325 static int 326 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 327 { 328 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 329 struct nv50_disp *disp = nv50_disp(drm->dev); 330 struct { 331 struct nv50_disp_mthd_v1 base; 332 struct nv50_disp_acquire_v0 info; 333 } args = { 334 .base.version = 1, 335 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 336 .base.hasht = nv_encoder->dcb->hasht, 337 .base.hashm = nv_encoder->dcb->hashm, 338 .info.hda = hda, 339 }; 340 int ret; 341 342 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 343 if (ret) { 344 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 345 return ret; 346 } 347 348 nv_encoder->or = args.info.or; 349 nv_encoder->link = args.info.link; 350 return 0; 351 } 352 353 static int 354 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 355 struct drm_crtc_state *crtc_state, 356 struct drm_connector_state *conn_state, 357 struct drm_display_mode *native_mode) 358 { 359 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 360 struct drm_display_mode *mode = &crtc_state->mode; 361 struct drm_connector *connector = conn_state->connector; 362 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 363 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 364 365 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 366 asyc->scaler.full = false; 367 if (!native_mode) 368 return 0; 369 370 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 371 switch (connector->connector_type) { 372 case DRM_MODE_CONNECTOR_LVDS: 373 case DRM_MODE_CONNECTOR_eDP: 374 /* Don't force scaler for EDID modes with 375 * same size as the native one (e.g. different 376 * refresh rate) 377 */ 378 if (mode->hdisplay == native_mode->hdisplay && 379 mode->vdisplay == native_mode->vdisplay && 380 mode->type & DRM_MODE_TYPE_DRIVER) 381 break; 382 mode = native_mode; 383 asyc->scaler.full = true; 384 break; 385 default: 386 break; 387 } 388 } else { 389 mode = native_mode; 390 } 391 392 if (!drm_mode_equal(adjusted_mode, mode)) { 393 drm_mode_copy(adjusted_mode, mode); 394 crtc_state->mode_changed = true; 395 } 396 397 return 0; 398 } 399 400 static int 401 nv50_outp_atomic_check(struct drm_encoder *encoder, 402 struct drm_crtc_state *crtc_state, 403 struct drm_connector_state *conn_state) 404 { 405 struct drm_connector *connector = conn_state->connector; 406 struct nouveau_connector *nv_connector = nouveau_connector(connector); 407 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 408 int ret; 409 410 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 411 nv_connector->native_mode); 412 if (ret) 413 return ret; 414 415 if (crtc_state->mode_changed || crtc_state->connectors_changed) 416 asyh->or.bpc = connector->display_info.bpc; 417 418 return 0; 419 } 420 421 struct nouveau_connector * 422 nv50_outp_get_new_connector(struct nouveau_encoder *outp, 423 struct drm_atomic_state *state) 424 { 425 struct drm_connector *connector; 426 struct drm_connector_state *connector_state; 427 struct drm_encoder *encoder = to_drm_encoder(outp); 428 int i; 429 430 for_each_new_connector_in_state(state, connector, connector_state, i) { 431 if (connector_state->best_encoder == encoder) 432 return nouveau_connector(connector); 433 } 434 435 return NULL; 436 } 437 438 struct nouveau_connector * 439 nv50_outp_get_old_connector(struct nouveau_encoder *outp, 440 struct drm_atomic_state *state) 441 { 442 struct drm_connector *connector; 443 struct drm_connector_state *connector_state; 444 struct drm_encoder *encoder = to_drm_encoder(outp); 445 int i; 446 447 for_each_old_connector_in_state(state, connector, connector_state, i) { 448 if (connector_state->best_encoder == encoder) 449 return nouveau_connector(connector); 450 } 451 452 return NULL; 453 } 454 455 /****************************************************************************** 456 * DAC 457 *****************************************************************************/ 458 static void 459 nv50_dac_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 460 { 461 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 462 struct nv50_core *core = nv50_disp(encoder->dev)->core; 463 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 464 if (nv_encoder->crtc) 465 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); 466 nv_encoder->crtc = NULL; 467 nv50_outp_release(nv_encoder); 468 } 469 470 static void 471 nv50_dac_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 472 { 473 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 474 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 475 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 476 struct nv50_core *core = nv50_disp(encoder->dev)->core; 477 u32 ctrl = 0; 478 479 switch (nv_crtc->index) { 480 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 481 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 482 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 483 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 484 default: 485 WARN_ON(1); 486 break; 487 } 488 489 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 490 491 nv50_outp_acquire(nv_encoder, false); 492 493 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); 494 asyh->or.depth = 0; 495 496 nv_encoder->crtc = encoder->crtc; 497 } 498 499 static enum drm_connector_status 500 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 501 { 502 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 503 struct nv50_disp *disp = nv50_disp(encoder->dev); 504 struct { 505 struct nv50_disp_mthd_v1 base; 506 struct nv50_disp_dac_load_v0 load; 507 } args = { 508 .base.version = 1, 509 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 510 .base.hasht = nv_encoder->dcb->hasht, 511 .base.hashm = nv_encoder->dcb->hashm, 512 }; 513 int ret; 514 515 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 516 if (args.load.data == 0) 517 args.load.data = 340; 518 519 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 520 if (ret || !args.load.load) 521 return connector_status_disconnected; 522 523 return connector_status_connected; 524 } 525 526 static const struct drm_encoder_helper_funcs 527 nv50_dac_help = { 528 .atomic_check = nv50_outp_atomic_check, 529 .atomic_enable = nv50_dac_enable, 530 .atomic_disable = nv50_dac_disable, 531 .detect = nv50_dac_detect 532 }; 533 534 static void 535 nv50_dac_destroy(struct drm_encoder *encoder) 536 { 537 drm_encoder_cleanup(encoder); 538 kfree(encoder); 539 } 540 541 static const struct drm_encoder_funcs 542 nv50_dac_func = { 543 .destroy = nv50_dac_destroy, 544 }; 545 546 static int 547 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 548 { 549 struct nouveau_drm *drm = nouveau_drm(connector->dev); 550 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 551 struct nvkm_i2c_bus *bus; 552 struct nouveau_encoder *nv_encoder; 553 struct drm_encoder *encoder; 554 int type = DRM_MODE_ENCODER_DAC; 555 556 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 557 if (!nv_encoder) 558 return -ENOMEM; 559 nv_encoder->dcb = dcbe; 560 561 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 562 if (bus) 563 nv_encoder->i2c = &bus->i2c; 564 565 encoder = to_drm_encoder(nv_encoder); 566 encoder->possible_crtcs = dcbe->heads; 567 encoder->possible_clones = 0; 568 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 569 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 570 drm_encoder_helper_add(encoder, &nv50_dac_help); 571 572 drm_connector_attach_encoder(connector, encoder); 573 return 0; 574 } 575 576 /* 577 * audio component binding for ELD notification 578 */ 579 static void 580 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 581 int dev_id) 582 { 583 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 584 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 585 port, dev_id); 586 } 587 588 static int 589 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 590 bool *enabled, unsigned char *buf, int max_bytes) 591 { 592 struct drm_device *drm_dev = dev_get_drvdata(kdev); 593 struct nouveau_drm *drm = nouveau_drm(drm_dev); 594 struct drm_encoder *encoder; 595 struct nouveau_encoder *nv_encoder; 596 struct drm_connector *connector; 597 struct nouveau_crtc *nv_crtc; 598 struct drm_connector_list_iter conn_iter; 599 int ret = 0; 600 601 *enabled = false; 602 603 drm_for_each_encoder(encoder, drm->dev) { 604 struct nouveau_connector *nv_connector = NULL; 605 606 nv_encoder = nouveau_encoder(encoder); 607 608 drm_connector_list_iter_begin(drm_dev, &conn_iter); 609 drm_for_each_connector_iter(connector, &conn_iter) { 610 if (connector->state->best_encoder == encoder) { 611 nv_connector = nouveau_connector(connector); 612 break; 613 } 614 } 615 drm_connector_list_iter_end(&conn_iter); 616 if (!nv_connector) 617 continue; 618 619 nv_crtc = nouveau_crtc(encoder->crtc); 620 if (!nv_crtc || nv_encoder->or != port || 621 nv_crtc->index != dev_id) 622 continue; 623 *enabled = nv_encoder->audio; 624 if (*enabled) { 625 ret = drm_eld_size(nv_connector->base.eld); 626 memcpy(buf, nv_connector->base.eld, 627 min(max_bytes, ret)); 628 } 629 break; 630 } 631 632 return ret; 633 } 634 635 static const struct drm_audio_component_ops nv50_audio_component_ops = { 636 .get_eld = nv50_audio_component_get_eld, 637 }; 638 639 static int 640 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 641 void *data) 642 { 643 struct drm_device *drm_dev = dev_get_drvdata(kdev); 644 struct nouveau_drm *drm = nouveau_drm(drm_dev); 645 struct drm_audio_component *acomp = data; 646 647 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 648 return -ENOMEM; 649 650 drm_modeset_lock_all(drm_dev); 651 acomp->ops = &nv50_audio_component_ops; 652 acomp->dev = kdev; 653 drm->audio.component = acomp; 654 drm_modeset_unlock_all(drm_dev); 655 return 0; 656 } 657 658 static void 659 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 660 void *data) 661 { 662 struct drm_device *drm_dev = dev_get_drvdata(kdev); 663 struct nouveau_drm *drm = nouveau_drm(drm_dev); 664 struct drm_audio_component *acomp = data; 665 666 drm_modeset_lock_all(drm_dev); 667 drm->audio.component = NULL; 668 acomp->ops = NULL; 669 acomp->dev = NULL; 670 drm_modeset_unlock_all(drm_dev); 671 } 672 673 static const struct component_ops nv50_audio_component_bind_ops = { 674 .bind = nv50_audio_component_bind, 675 .unbind = nv50_audio_component_unbind, 676 }; 677 678 static void 679 nv50_audio_component_init(struct nouveau_drm *drm) 680 { 681 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 682 drm->audio.component_registered = true; 683 } 684 685 static void 686 nv50_audio_component_fini(struct nouveau_drm *drm) 687 { 688 if (drm->audio.component_registered) { 689 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 690 drm->audio.component_registered = false; 691 } 692 } 693 694 /****************************************************************************** 695 * Audio 696 *****************************************************************************/ 697 static void 698 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 699 { 700 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 701 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 702 struct nv50_disp *disp = nv50_disp(encoder->dev); 703 struct { 704 struct nv50_disp_mthd_v1 base; 705 struct nv50_disp_sor_hda_eld_v0 eld; 706 } args = { 707 .base.version = 1, 708 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 709 .base.hasht = nv_encoder->dcb->hasht, 710 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 711 (0x0100 << nv_crtc->index), 712 }; 713 714 if (!nv_encoder->audio) 715 return; 716 717 nv_encoder->audio = false; 718 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 719 720 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 721 nv_crtc->index); 722 } 723 724 static void 725 nv50_audio_enable(struct drm_encoder *encoder, struct drm_atomic_state *state, 726 struct drm_display_mode *mode) 727 { 728 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 729 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 730 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 731 struct nouveau_connector *nv_connector; 732 struct nv50_disp *disp = nv50_disp(encoder->dev); 733 struct __packed { 734 struct { 735 struct nv50_disp_mthd_v1 mthd; 736 struct nv50_disp_sor_hda_eld_v0 eld; 737 } base; 738 u8 data[sizeof(nv_connector->base.eld)]; 739 } args = { 740 .base.mthd.version = 1, 741 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 742 .base.mthd.hasht = nv_encoder->dcb->hasht, 743 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 744 (0x0100 << nv_crtc->index), 745 }; 746 747 nv_connector = nv50_outp_get_new_connector(nv_encoder, state); 748 if (!drm_detect_monitor_audio(nv_connector->edid)) 749 return; 750 751 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 752 753 nvif_mthd(&disp->disp->object, 0, &args, 754 sizeof(args.base) + drm_eld_size(args.data)); 755 nv_encoder->audio = true; 756 757 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 758 nv_crtc->index); 759 } 760 761 /****************************************************************************** 762 * HDMI 763 *****************************************************************************/ 764 static void 765 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 766 { 767 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 768 struct nv50_disp *disp = nv50_disp(encoder->dev); 769 struct { 770 struct nv50_disp_mthd_v1 base; 771 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 772 } args = { 773 .base.version = 1, 774 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 775 .base.hasht = nv_encoder->dcb->hasht, 776 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 777 (0x0100 << nv_crtc->index), 778 }; 779 780 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 781 } 782 783 static void 784 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_atomic_state *state, 785 struct drm_display_mode *mode) 786 { 787 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 788 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 789 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 790 struct nv50_disp *disp = nv50_disp(encoder->dev); 791 struct { 792 struct nv50_disp_mthd_v1 base; 793 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 794 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 795 } args = { 796 .base.version = 1, 797 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 798 .base.hasht = nv_encoder->dcb->hasht, 799 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 800 (0x0100 << nv_crtc->index), 801 .pwr.state = 1, 802 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 803 }; 804 struct nouveau_connector *nv_connector; 805 struct drm_hdmi_info *hdmi; 806 u32 max_ac_packet; 807 union hdmi_infoframe avi_frame; 808 union hdmi_infoframe vendor_frame; 809 bool high_tmds_clock_ratio = false, scrambling = false; 810 u8 config; 811 int ret; 812 int size; 813 814 nv_connector = nv50_outp_get_new_connector(nv_encoder, state); 815 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 816 return; 817 818 hdmi = &nv_connector->base.display_info.hdmi; 819 820 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 821 &nv_connector->base, mode); 822 if (!ret) { 823 /* We have an AVI InfoFrame, populate it to the display */ 824 args.pwr.avi_infoframe_length 825 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 826 } 827 828 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 829 &nv_connector->base, mode); 830 if (!ret) { 831 /* We have a Vendor InfoFrame, populate it to the display */ 832 args.pwr.vendor_infoframe_length 833 = hdmi_infoframe_pack(&vendor_frame, 834 args.infoframes 835 + args.pwr.avi_infoframe_length, 836 17); 837 } 838 839 max_ac_packet = mode->htotal - mode->hdisplay; 840 max_ac_packet -= args.pwr.rekey; 841 max_ac_packet -= 18; /* constant from tegra */ 842 args.pwr.max_ac_packet = max_ac_packet / 32; 843 844 if (hdmi->scdc.scrambling.supported) { 845 high_tmds_clock_ratio = mode->clock > 340000; 846 scrambling = high_tmds_clock_ratio || 847 hdmi->scdc.scrambling.low_rates; 848 } 849 850 args.pwr.scdc = 851 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 852 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 853 854 size = sizeof(args.base) 855 + sizeof(args.pwr) 856 + args.pwr.avi_infoframe_length 857 + args.pwr.vendor_infoframe_length; 858 nvif_mthd(&disp->disp->object, 0, &args, size); 859 860 nv50_audio_enable(encoder, state, mode); 861 862 /* If SCDC is supported by the downstream monitor, update 863 * divider / scrambling settings to what we programmed above. 864 */ 865 if (!hdmi->scdc.scrambling.supported) 866 return; 867 868 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 869 if (ret < 0) { 870 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 871 return; 872 } 873 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 874 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 875 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 876 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 877 if (ret < 0) 878 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 879 config, ret); 880 } 881 882 /****************************************************************************** 883 * MST 884 *****************************************************************************/ 885 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 886 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 887 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 888 889 struct nv50_mstc { 890 struct nv50_mstm *mstm; 891 struct drm_dp_mst_port *port; 892 struct drm_connector connector; 893 894 struct drm_display_mode *native; 895 struct edid *edid; 896 }; 897 898 struct nv50_msto { 899 struct drm_encoder encoder; 900 901 struct nv50_head *head; 902 struct nv50_mstc *mstc; 903 bool disabled; 904 }; 905 906 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 907 { 908 struct nv50_msto *msto; 909 910 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 911 return nouveau_encoder(encoder); 912 913 msto = nv50_msto(encoder); 914 if (!msto->mstc) 915 return NULL; 916 return msto->mstc->mstm->outp; 917 } 918 919 static struct drm_dp_payload * 920 nv50_msto_payload(struct nv50_msto *msto) 921 { 922 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 923 struct nv50_mstc *mstc = msto->mstc; 924 struct nv50_mstm *mstm = mstc->mstm; 925 int vcpi = mstc->port->vcpi.vcpi, i; 926 927 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 928 929 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 930 for (i = 0; i < mstm->mgr.max_payloads; i++) { 931 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 932 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 933 mstm->outp->base.base.name, i, payload->vcpi, 934 payload->start_slot, payload->num_slots); 935 } 936 937 for (i = 0; i < mstm->mgr.max_payloads; i++) { 938 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 939 if (payload->vcpi == vcpi) 940 return payload; 941 } 942 943 return NULL; 944 } 945 946 static void 947 nv50_msto_cleanup(struct nv50_msto *msto) 948 { 949 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 950 struct nv50_mstc *mstc = msto->mstc; 951 struct nv50_mstm *mstm = mstc->mstm; 952 953 if (!msto->disabled) 954 return; 955 956 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 957 958 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 959 960 msto->mstc = NULL; 961 msto->disabled = false; 962 } 963 964 static void 965 nv50_msto_prepare(struct nv50_msto *msto) 966 { 967 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 968 struct nv50_mstc *mstc = msto->mstc; 969 struct nv50_mstm *mstm = mstc->mstm; 970 struct { 971 struct nv50_disp_mthd_v1 base; 972 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 973 } args = { 974 .base.version = 1, 975 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 976 .base.hasht = mstm->outp->dcb->hasht, 977 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 978 (0x0100 << msto->head->base.index), 979 }; 980 981 mutex_lock(&mstm->mgr.payload_lock); 982 983 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 984 if (mstc->port->vcpi.vcpi > 0) { 985 struct drm_dp_payload *payload = nv50_msto_payload(msto); 986 if (payload) { 987 args.vcpi.start_slot = payload->start_slot; 988 args.vcpi.num_slots = payload->num_slots; 989 args.vcpi.pbn = mstc->port->vcpi.pbn; 990 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 991 } 992 } 993 994 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 995 msto->encoder.name, msto->head->base.base.name, 996 args.vcpi.start_slot, args.vcpi.num_slots, 997 args.vcpi.pbn, args.vcpi.aligned_pbn); 998 999 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 1000 mutex_unlock(&mstm->mgr.payload_lock); 1001 } 1002 1003 static int 1004 nv50_msto_atomic_check(struct drm_encoder *encoder, 1005 struct drm_crtc_state *crtc_state, 1006 struct drm_connector_state *conn_state) 1007 { 1008 struct drm_atomic_state *state = crtc_state->state; 1009 struct drm_connector *connector = conn_state->connector; 1010 struct nv50_mstc *mstc = nv50_mstc(connector); 1011 struct nv50_mstm *mstm = mstc->mstm; 1012 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 1013 int slots; 1014 int ret; 1015 1016 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 1017 mstc->native); 1018 if (ret) 1019 return ret; 1020 1021 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 1022 return 0; 1023 1024 /* 1025 * When restoring duplicated states, we need to make sure that the bw 1026 * remains the same and avoid recalculating it, as the connector's bpc 1027 * may have changed after the state was duplicated 1028 */ 1029 if (!state->duplicated) { 1030 const int clock = crtc_state->adjusted_mode.clock; 1031 1032 asyh->or.bpc = connector->display_info.bpc; 1033 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 1034 false); 1035 } 1036 1037 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 1038 asyh->dp.pbn, 0); 1039 if (slots < 0) 1040 return slots; 1041 1042 asyh->dp.tu = slots; 1043 1044 return 0; 1045 } 1046 1047 static u8 1048 nv50_dp_bpc_to_depth(unsigned int bpc) 1049 { 1050 switch (bpc) { 1051 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1052 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1053 case 10: 1054 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1055 } 1056 } 1057 1058 static void 1059 nv50_msto_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1060 { 1061 struct nv50_head *head = nv50_head(encoder->crtc); 1062 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 1063 struct nv50_msto *msto = nv50_msto(encoder); 1064 struct nv50_mstc *mstc = NULL; 1065 struct nv50_mstm *mstm = NULL; 1066 struct drm_connector *connector; 1067 struct drm_connector_list_iter conn_iter; 1068 u8 proto; 1069 bool r; 1070 1071 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1072 drm_for_each_connector_iter(connector, &conn_iter) { 1073 if (connector->state->best_encoder == &msto->encoder) { 1074 mstc = nv50_mstc(connector); 1075 mstm = mstc->mstm; 1076 break; 1077 } 1078 } 1079 drm_connector_list_iter_end(&conn_iter); 1080 1081 if (WARN_ON(!mstc)) 1082 return; 1083 1084 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 1085 armh->dp.tu); 1086 if (!r) 1087 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 1088 1089 if (!mstm->links++) 1090 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 1091 1092 if (mstm->outp->link & 1) 1093 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1094 else 1095 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1096 1097 mstm->outp->update(mstm->outp, head->base.index, armh, proto, 1098 nv50_dp_bpc_to_depth(armh->or.bpc)); 1099 1100 msto->mstc = mstc; 1101 mstm->modified = true; 1102 } 1103 1104 static void 1105 nv50_msto_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1106 { 1107 struct nv50_msto *msto = nv50_msto(encoder); 1108 struct nv50_mstc *mstc = msto->mstc; 1109 struct nv50_mstm *mstm = mstc->mstm; 1110 1111 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 1112 1113 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1114 mstm->modified = true; 1115 if (!--mstm->links) 1116 mstm->disabled = true; 1117 msto->disabled = true; 1118 } 1119 1120 static const struct drm_encoder_helper_funcs 1121 nv50_msto_help = { 1122 .atomic_disable = nv50_msto_disable, 1123 .atomic_enable = nv50_msto_enable, 1124 .atomic_check = nv50_msto_atomic_check, 1125 }; 1126 1127 static void 1128 nv50_msto_destroy(struct drm_encoder *encoder) 1129 { 1130 struct nv50_msto *msto = nv50_msto(encoder); 1131 drm_encoder_cleanup(&msto->encoder); 1132 kfree(msto); 1133 } 1134 1135 static const struct drm_encoder_funcs 1136 nv50_msto = { 1137 .destroy = nv50_msto_destroy, 1138 }; 1139 1140 static struct nv50_msto * 1141 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1142 { 1143 struct nv50_msto *msto; 1144 int ret; 1145 1146 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1147 if (!msto) 1148 return ERR_PTR(-ENOMEM); 1149 1150 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1151 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1152 if (ret) { 1153 kfree(msto); 1154 return ERR_PTR(ret); 1155 } 1156 1157 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1158 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1159 msto->head = head; 1160 return msto; 1161 } 1162 1163 static struct drm_encoder * 1164 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1165 struct drm_atomic_state *state) 1166 { 1167 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1168 connector); 1169 struct nv50_mstc *mstc = nv50_mstc(connector); 1170 struct drm_crtc *crtc = connector_state->crtc; 1171 1172 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1173 return NULL; 1174 1175 return &nv50_head(crtc)->msto->encoder; 1176 } 1177 1178 static enum drm_mode_status 1179 nv50_mstc_mode_valid(struct drm_connector *connector, 1180 struct drm_display_mode *mode) 1181 { 1182 struct nv50_mstc *mstc = nv50_mstc(connector); 1183 struct nouveau_encoder *outp = mstc->mstm->outp; 1184 1185 /* TODO: calculate the PBN from the dotclock and validate against the 1186 * MSTB's max possible PBN 1187 */ 1188 1189 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1190 } 1191 1192 static int 1193 nv50_mstc_get_modes(struct drm_connector *connector) 1194 { 1195 struct nv50_mstc *mstc = nv50_mstc(connector); 1196 int ret = 0; 1197 1198 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1199 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1200 if (mstc->edid) 1201 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1202 1203 /* 1204 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1205 * to 8 to save bandwidth on the topology. In the future, we'll want 1206 * to properly fix this by dynamically selecting the highest possible 1207 * bpc that would fit in the topology 1208 */ 1209 if (connector->display_info.bpc) 1210 connector->display_info.bpc = 1211 clamp(connector->display_info.bpc, 6U, 8U); 1212 else 1213 connector->display_info.bpc = 8; 1214 1215 if (mstc->native) 1216 drm_mode_destroy(mstc->connector.dev, mstc->native); 1217 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1218 return ret; 1219 } 1220 1221 static int 1222 nv50_mstc_atomic_check(struct drm_connector *connector, 1223 struct drm_atomic_state *state) 1224 { 1225 struct nv50_mstc *mstc = nv50_mstc(connector); 1226 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1227 struct drm_connector_state *new_conn_state = 1228 drm_atomic_get_new_connector_state(state, connector); 1229 struct drm_connector_state *old_conn_state = 1230 drm_atomic_get_old_connector_state(state, connector); 1231 struct drm_crtc_state *crtc_state; 1232 struct drm_crtc *new_crtc = new_conn_state->crtc; 1233 1234 if (!old_conn_state->crtc) 1235 return 0; 1236 1237 /* We only want to free VCPI if this state disables the CRTC on this 1238 * connector 1239 */ 1240 if (new_crtc) { 1241 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1242 1243 if (!crtc_state || 1244 !drm_atomic_crtc_needs_modeset(crtc_state) || 1245 crtc_state->enable) 1246 return 0; 1247 } 1248 1249 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1250 } 1251 1252 static int 1253 nv50_mstc_detect(struct drm_connector *connector, 1254 struct drm_modeset_acquire_ctx *ctx, bool force) 1255 { 1256 struct nv50_mstc *mstc = nv50_mstc(connector); 1257 int ret; 1258 1259 if (drm_connector_is_unregistered(connector)) 1260 return connector_status_disconnected; 1261 1262 ret = pm_runtime_get_sync(connector->dev->dev); 1263 if (ret < 0 && ret != -EACCES) { 1264 pm_runtime_put_autosuspend(connector->dev->dev); 1265 return connector_status_disconnected; 1266 } 1267 1268 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1269 mstc->port); 1270 if (ret != connector_status_connected) 1271 goto out; 1272 1273 out: 1274 pm_runtime_mark_last_busy(connector->dev->dev); 1275 pm_runtime_put_autosuspend(connector->dev->dev); 1276 return ret; 1277 } 1278 1279 static const struct drm_connector_helper_funcs 1280 nv50_mstc_help = { 1281 .get_modes = nv50_mstc_get_modes, 1282 .mode_valid = nv50_mstc_mode_valid, 1283 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1284 .atomic_check = nv50_mstc_atomic_check, 1285 .detect_ctx = nv50_mstc_detect, 1286 }; 1287 1288 static void 1289 nv50_mstc_destroy(struct drm_connector *connector) 1290 { 1291 struct nv50_mstc *mstc = nv50_mstc(connector); 1292 1293 drm_connector_cleanup(&mstc->connector); 1294 drm_dp_mst_put_port_malloc(mstc->port); 1295 1296 kfree(mstc); 1297 } 1298 1299 static const struct drm_connector_funcs 1300 nv50_mstc = { 1301 .reset = nouveau_conn_reset, 1302 .fill_modes = drm_helper_probe_single_connector_modes, 1303 .destroy = nv50_mstc_destroy, 1304 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1305 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1306 .atomic_set_property = nouveau_conn_atomic_set_property, 1307 .atomic_get_property = nouveau_conn_atomic_get_property, 1308 }; 1309 1310 static int 1311 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1312 const char *path, struct nv50_mstc **pmstc) 1313 { 1314 struct drm_device *dev = mstm->outp->base.base.dev; 1315 struct drm_crtc *crtc; 1316 struct nv50_mstc *mstc; 1317 int ret; 1318 1319 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1320 return -ENOMEM; 1321 mstc->mstm = mstm; 1322 mstc->port = port; 1323 1324 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1325 DRM_MODE_CONNECTOR_DisplayPort); 1326 if (ret) { 1327 kfree(*pmstc); 1328 *pmstc = NULL; 1329 return ret; 1330 } 1331 1332 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1333 1334 mstc->connector.funcs->reset(&mstc->connector); 1335 nouveau_conn_attach_properties(&mstc->connector); 1336 1337 drm_for_each_crtc(crtc, dev) { 1338 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1339 continue; 1340 1341 drm_connector_attach_encoder(&mstc->connector, 1342 &nv50_head(crtc)->msto->encoder); 1343 } 1344 1345 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1346 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1347 drm_connector_set_path_property(&mstc->connector, path); 1348 drm_dp_mst_get_port_malloc(port); 1349 return 0; 1350 } 1351 1352 static void 1353 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1354 { 1355 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1356 struct drm_encoder *encoder; 1357 int ret; 1358 1359 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1360 ret = drm_dp_check_act_status(&mstm->mgr); 1361 1362 ret = drm_dp_update_payload_part2(&mstm->mgr); 1363 1364 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1365 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1366 struct nv50_msto *msto = nv50_msto(encoder); 1367 struct nv50_mstc *mstc = msto->mstc; 1368 if (mstc && mstc->mstm == mstm) 1369 nv50_msto_cleanup(msto); 1370 } 1371 } 1372 1373 mstm->modified = false; 1374 } 1375 1376 static void 1377 nv50_mstm_prepare(struct nv50_mstm *mstm) 1378 { 1379 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1380 struct drm_encoder *encoder; 1381 int ret; 1382 1383 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1384 ret = drm_dp_update_payload_part1(&mstm->mgr); 1385 1386 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1387 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1388 struct nv50_msto *msto = nv50_msto(encoder); 1389 struct nv50_mstc *mstc = msto->mstc; 1390 if (mstc && mstc->mstm == mstm) 1391 nv50_msto_prepare(msto); 1392 } 1393 } 1394 1395 if (mstm->disabled) { 1396 if (!mstm->links) 1397 nv50_outp_release(mstm->outp); 1398 mstm->disabled = false; 1399 } 1400 } 1401 1402 static struct drm_connector * 1403 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1404 struct drm_dp_mst_port *port, const char *path) 1405 { 1406 struct nv50_mstm *mstm = nv50_mstm(mgr); 1407 struct nv50_mstc *mstc; 1408 int ret; 1409 1410 ret = nv50_mstc_new(mstm, port, path, &mstc); 1411 if (ret) 1412 return NULL; 1413 1414 return &mstc->connector; 1415 } 1416 1417 static const struct drm_dp_mst_topology_cbs 1418 nv50_mstm = { 1419 .add_connector = nv50_mstm_add_connector, 1420 }; 1421 1422 bool 1423 nv50_mstm_service(struct nouveau_drm *drm, 1424 struct nouveau_connector *nv_connector, 1425 struct nv50_mstm *mstm) 1426 { 1427 struct drm_dp_aux *aux = &nv_connector->aux; 1428 bool handled = true, ret = true; 1429 int rc; 1430 u8 esi[8] = {}; 1431 1432 while (handled) { 1433 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1434 if (rc != 8) { 1435 ret = false; 1436 break; 1437 } 1438 1439 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1440 if (!handled) 1441 break; 1442 1443 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 1444 3); 1445 if (rc != 3) { 1446 ret = false; 1447 break; 1448 } 1449 } 1450 1451 if (!ret) 1452 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1453 nv_connector->base.name, rc); 1454 1455 return ret; 1456 } 1457 1458 void 1459 nv50_mstm_remove(struct nv50_mstm *mstm) 1460 { 1461 mstm->is_mst = false; 1462 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1463 } 1464 1465 static int 1466 nv50_mstm_enable(struct nv50_mstm *mstm, int state) 1467 { 1468 struct nouveau_encoder *outp = mstm->outp; 1469 struct { 1470 struct nv50_disp_mthd_v1 base; 1471 struct nv50_disp_sor_dp_mst_link_v0 mst; 1472 } args = { 1473 .base.version = 1, 1474 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1475 .base.hasht = outp->dcb->hasht, 1476 .base.hashm = outp->dcb->hashm, 1477 .mst.state = state, 1478 }; 1479 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1480 struct nvif_object *disp = &drm->display->disp.object; 1481 1482 return nvif_mthd(disp, 0, &args, sizeof(args)); 1483 } 1484 1485 int 1486 nv50_mstm_detect(struct nouveau_encoder *outp) 1487 { 1488 struct nv50_mstm *mstm = outp->dp.mstm; 1489 struct drm_dp_aux *aux; 1490 int ret; 1491 1492 if (!mstm || !mstm->can_mst) 1493 return 0; 1494 1495 aux = mstm->mgr.aux; 1496 1497 /* Clear any leftover MST state we didn't set ourselves by first 1498 * disabling MST if it was already enabled 1499 */ 1500 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1501 if (ret < 0) 1502 return ret; 1503 1504 /* And start enabling */ 1505 ret = nv50_mstm_enable(mstm, true); 1506 if (ret) 1507 return ret; 1508 1509 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1510 if (ret) { 1511 nv50_mstm_enable(mstm, false); 1512 return ret; 1513 } 1514 1515 mstm->is_mst = true; 1516 return 1; 1517 } 1518 1519 static void 1520 nv50_mstm_fini(struct nouveau_encoder *outp) 1521 { 1522 struct nv50_mstm *mstm = outp->dp.mstm; 1523 1524 if (!mstm) 1525 return; 1526 1527 /* Don't change the MST state of this connector until we've finished 1528 * resuming, since we can't safely grab hpd_irq_lock in our resume 1529 * path to protect mstm->is_mst without potentially deadlocking 1530 */ 1531 mutex_lock(&outp->dp.hpd_irq_lock); 1532 mstm->suspended = true; 1533 mutex_unlock(&outp->dp.hpd_irq_lock); 1534 1535 if (mstm->is_mst) 1536 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1537 } 1538 1539 static void 1540 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1541 { 1542 struct nv50_mstm *mstm = outp->dp.mstm; 1543 int ret = 0; 1544 1545 if (!mstm) 1546 return; 1547 1548 if (mstm->is_mst) { 1549 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1550 if (ret == -1) 1551 nv50_mstm_remove(mstm); 1552 } 1553 1554 mutex_lock(&outp->dp.hpd_irq_lock); 1555 mstm->suspended = false; 1556 mutex_unlock(&outp->dp.hpd_irq_lock); 1557 1558 if (ret == -1) 1559 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1560 } 1561 1562 static void 1563 nv50_mstm_del(struct nv50_mstm **pmstm) 1564 { 1565 struct nv50_mstm *mstm = *pmstm; 1566 if (mstm) { 1567 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1568 kfree(*pmstm); 1569 *pmstm = NULL; 1570 } 1571 } 1572 1573 static int 1574 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1575 int conn_base_id, struct nv50_mstm **pmstm) 1576 { 1577 const int max_payloads = hweight8(outp->dcb->heads); 1578 struct drm_device *dev = outp->base.base.dev; 1579 struct nv50_mstm *mstm; 1580 int ret; 1581 1582 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1583 return -ENOMEM; 1584 mstm->outp = outp; 1585 mstm->mgr.cbs = &nv50_mstm; 1586 1587 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1588 max_payloads, conn_base_id); 1589 if (ret) 1590 return ret; 1591 1592 return 0; 1593 } 1594 1595 /****************************************************************************** 1596 * SOR 1597 *****************************************************************************/ 1598 static void 1599 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1600 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1601 { 1602 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1603 struct nv50_core *core = disp->core; 1604 1605 if (!asyh) { 1606 nv_encoder->ctrl &= ~BIT(head); 1607 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1608 nv_encoder->ctrl = 0; 1609 } else { 1610 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1611 nv_encoder->ctrl |= BIT(head); 1612 asyh->or.depth = depth; 1613 } 1614 1615 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1616 } 1617 1618 static void 1619 nv50_sor_disable(struct drm_encoder *encoder, 1620 struct drm_atomic_state *state) 1621 { 1622 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1623 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1624 struct nouveau_connector *nv_connector = 1625 nv50_outp_get_old_connector(nv_encoder, state); 1626 1627 nv_encoder->crtc = NULL; 1628 1629 if (nv_crtc) { 1630 struct drm_dp_aux *aux = &nv_connector->aux; 1631 u8 pwr; 1632 1633 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1634 int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1635 1636 if (ret == 0) { 1637 pwr &= ~DP_SET_POWER_MASK; 1638 pwr |= DP_SET_POWER_D3; 1639 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1640 } 1641 } 1642 1643 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1644 nv50_audio_disable(encoder, nv_crtc); 1645 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1646 nv50_outp_release(nv_encoder); 1647 } 1648 } 1649 1650 static void 1651 nv50_sor_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1652 { 1653 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1654 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1655 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1656 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1657 struct { 1658 struct nv50_disp_mthd_v1 base; 1659 struct nv50_disp_sor_lvds_script_v0 lvds; 1660 } lvds = { 1661 .base.version = 1, 1662 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1663 .base.hasht = nv_encoder->dcb->hasht, 1664 .base.hashm = nv_encoder->dcb->hashm, 1665 }; 1666 struct nv50_disp *disp = nv50_disp(encoder->dev); 1667 struct drm_device *dev = encoder->dev; 1668 struct nouveau_drm *drm = nouveau_drm(dev); 1669 struct nouveau_connector *nv_connector; 1670 struct nvbios *bios = &drm->vbios; 1671 bool hda = false; 1672 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1673 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1674 1675 nv_connector = nv50_outp_get_new_connector(nv_encoder, state); 1676 nv_encoder->crtc = encoder->crtc; 1677 1678 if ((disp->disp->object.oclass == GT214_DISP || 1679 disp->disp->object.oclass >= GF110_DISP) && 1680 drm_detect_monitor_audio(nv_connector->edid)) 1681 hda = true; 1682 nv50_outp_acquire(nv_encoder, hda); 1683 1684 switch (nv_encoder->dcb->type) { 1685 case DCB_OUTPUT_TMDS: 1686 if (nv_encoder->link & 1) { 1687 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1688 /* Only enable dual-link if: 1689 * - Need to (i.e. rate > 165MHz) 1690 * - DCB says we can 1691 * - Not an HDMI monitor, since there's no dual-link 1692 * on HDMI. 1693 */ 1694 if (mode->clock >= 165000 && 1695 nv_encoder->dcb->duallink_possible && 1696 !drm_detect_hdmi_monitor(nv_connector->edid)) 1697 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1698 } else { 1699 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1700 } 1701 1702 nv50_hdmi_enable(&nv_encoder->base.base, state, mode); 1703 break; 1704 case DCB_OUTPUT_LVDS: 1705 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1706 1707 if (bios->fp_no_ddc) { 1708 if (bios->fp.dual_link) 1709 lvds.lvds.script |= 0x0100; 1710 if (bios->fp.if_is_24bit) 1711 lvds.lvds.script |= 0x0200; 1712 } else { 1713 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1714 if (((u8 *)nv_connector->edid)[121] == 2) 1715 lvds.lvds.script |= 0x0100; 1716 } else 1717 if (mode->clock >= bios->fp.duallink_transition_clk) { 1718 lvds.lvds.script |= 0x0100; 1719 } 1720 1721 if (lvds.lvds.script & 0x0100) { 1722 if (bios->fp.strapless_is_24bit & 2) 1723 lvds.lvds.script |= 0x0200; 1724 } else { 1725 if (bios->fp.strapless_is_24bit & 1) 1726 lvds.lvds.script |= 0x0200; 1727 } 1728 1729 if (asyh->or.bpc == 8) 1730 lvds.lvds.script |= 0x0200; 1731 } 1732 1733 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1734 break; 1735 case DCB_OUTPUT_DP: 1736 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1737 1738 if (nv_encoder->link & 1) 1739 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1740 else 1741 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1742 1743 nv50_audio_enable(encoder, state, mode); 1744 break; 1745 default: 1746 BUG(); 1747 break; 1748 } 1749 1750 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1751 } 1752 1753 static const struct drm_encoder_helper_funcs 1754 nv50_sor_help = { 1755 .atomic_check = nv50_outp_atomic_check, 1756 .atomic_enable = nv50_sor_enable, 1757 .atomic_disable = nv50_sor_disable, 1758 }; 1759 1760 static void 1761 nv50_sor_destroy(struct drm_encoder *encoder) 1762 { 1763 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1764 nv50_mstm_del(&nv_encoder->dp.mstm); 1765 drm_encoder_cleanup(encoder); 1766 1767 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1768 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1769 1770 kfree(encoder); 1771 } 1772 1773 static const struct drm_encoder_funcs 1774 nv50_sor_func = { 1775 .destroy = nv50_sor_destroy, 1776 }; 1777 1778 static bool nv50_has_mst(struct nouveau_drm *drm) 1779 { 1780 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1781 u32 data; 1782 u8 ver, hdr, cnt, len; 1783 1784 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1785 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1786 } 1787 1788 static int 1789 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1790 { 1791 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1792 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1793 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1794 struct nouveau_encoder *nv_encoder; 1795 struct drm_encoder *encoder; 1796 struct nv50_disp *disp = nv50_disp(connector->dev); 1797 int type, ret; 1798 1799 switch (dcbe->type) { 1800 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1801 case DCB_OUTPUT_TMDS: 1802 case DCB_OUTPUT_DP: 1803 default: 1804 type = DRM_MODE_ENCODER_TMDS; 1805 break; 1806 } 1807 1808 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1809 if (!nv_encoder) 1810 return -ENOMEM; 1811 nv_encoder->dcb = dcbe; 1812 nv_encoder->update = nv50_sor_update; 1813 1814 encoder = to_drm_encoder(nv_encoder); 1815 encoder->possible_crtcs = dcbe->heads; 1816 encoder->possible_clones = 0; 1817 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1818 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1819 drm_encoder_helper_add(encoder, &nv50_sor_help); 1820 1821 drm_connector_attach_encoder(connector, encoder); 1822 1823 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1824 1825 if (dcbe->type == DCB_OUTPUT_DP) { 1826 struct nvkm_i2c_aux *aux = 1827 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1828 1829 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1830 1831 if (aux) { 1832 if (disp->disp->object.oclass < GF110_DISP) { 1833 /* HW has no support for address-only 1834 * transactions, so we're required to 1835 * use custom I2C-over-AUX code. 1836 */ 1837 nv_encoder->i2c = &aux->i2c; 1838 } else { 1839 nv_encoder->i2c = &nv_connector->aux.ddc; 1840 } 1841 nv_encoder->aux = aux; 1842 } 1843 1844 if (nv_connector->type != DCB_CONNECTOR_eDP && 1845 nv50_has_mst(drm)) { 1846 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1847 16, nv_connector->base.base.id, 1848 &nv_encoder->dp.mstm); 1849 if (ret) 1850 return ret; 1851 } 1852 } else { 1853 struct nvkm_i2c_bus *bus = 1854 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1855 if (bus) 1856 nv_encoder->i2c = &bus->i2c; 1857 } 1858 1859 return 0; 1860 } 1861 1862 /****************************************************************************** 1863 * PIOR 1864 *****************************************************************************/ 1865 static int 1866 nv50_pior_atomic_check(struct drm_encoder *encoder, 1867 struct drm_crtc_state *crtc_state, 1868 struct drm_connector_state *conn_state) 1869 { 1870 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1871 if (ret) 1872 return ret; 1873 crtc_state->adjusted_mode.clock *= 2; 1874 return 0; 1875 } 1876 1877 static void 1878 nv50_pior_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1879 { 1880 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1881 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1882 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1883 if (nv_encoder->crtc) 1884 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); 1885 nv_encoder->crtc = NULL; 1886 nv50_outp_release(nv_encoder); 1887 } 1888 1889 static void 1890 nv50_pior_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1891 { 1892 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1893 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1894 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1895 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1896 u32 ctrl = 0; 1897 1898 switch (nv_crtc->index) { 1899 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1900 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1901 default: 1902 WARN_ON(1); 1903 break; 1904 } 1905 1906 nv50_outp_acquire(nv_encoder, false); 1907 1908 switch (asyh->or.bpc) { 1909 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1910 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1911 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1912 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1913 } 1914 1915 switch (nv_encoder->dcb->type) { 1916 case DCB_OUTPUT_TMDS: 1917 case DCB_OUTPUT_DP: 1918 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1919 break; 1920 default: 1921 BUG(); 1922 break; 1923 } 1924 1925 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); 1926 nv_encoder->crtc = &nv_crtc->base; 1927 } 1928 1929 static const struct drm_encoder_helper_funcs 1930 nv50_pior_help = { 1931 .atomic_check = nv50_pior_atomic_check, 1932 .atomic_enable = nv50_pior_enable, 1933 .atomic_disable = nv50_pior_disable, 1934 }; 1935 1936 static void 1937 nv50_pior_destroy(struct drm_encoder *encoder) 1938 { 1939 drm_encoder_cleanup(encoder); 1940 kfree(encoder); 1941 } 1942 1943 static const struct drm_encoder_funcs 1944 nv50_pior_func = { 1945 .destroy = nv50_pior_destroy, 1946 }; 1947 1948 static int 1949 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1950 { 1951 struct drm_device *dev = connector->dev; 1952 struct nouveau_drm *drm = nouveau_drm(dev); 1953 struct nv50_disp *disp = nv50_disp(dev); 1954 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1955 struct nvkm_i2c_bus *bus = NULL; 1956 struct nvkm_i2c_aux *aux = NULL; 1957 struct i2c_adapter *ddc; 1958 struct nouveau_encoder *nv_encoder; 1959 struct drm_encoder *encoder; 1960 int type; 1961 1962 switch (dcbe->type) { 1963 case DCB_OUTPUT_TMDS: 1964 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1965 ddc = bus ? &bus->i2c : NULL; 1966 type = DRM_MODE_ENCODER_TMDS; 1967 break; 1968 case DCB_OUTPUT_DP: 1969 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1970 ddc = aux ? &aux->i2c : NULL; 1971 type = DRM_MODE_ENCODER_TMDS; 1972 break; 1973 default: 1974 return -ENODEV; 1975 } 1976 1977 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1978 if (!nv_encoder) 1979 return -ENOMEM; 1980 nv_encoder->dcb = dcbe; 1981 nv_encoder->i2c = ddc; 1982 nv_encoder->aux = aux; 1983 1984 encoder = to_drm_encoder(nv_encoder); 1985 encoder->possible_crtcs = dcbe->heads; 1986 encoder->possible_clones = 0; 1987 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1988 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1989 drm_encoder_helper_add(encoder, &nv50_pior_help); 1990 1991 drm_connector_attach_encoder(connector, encoder); 1992 1993 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1994 1995 return 0; 1996 } 1997 1998 /****************************************************************************** 1999 * Atomic 2000 *****************************************************************************/ 2001 2002 static void 2003 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 2004 { 2005 struct nouveau_drm *drm = nouveau_drm(state->dev); 2006 struct nv50_disp *disp = nv50_disp(drm->dev); 2007 struct nv50_core *core = disp->core; 2008 struct nv50_mstm *mstm; 2009 struct drm_encoder *encoder; 2010 2011 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 2012 2013 drm_for_each_encoder(encoder, drm->dev) { 2014 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2015 mstm = nouveau_encoder(encoder)->dp.mstm; 2016 if (mstm && mstm->modified) 2017 nv50_mstm_prepare(mstm); 2018 } 2019 } 2020 2021 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 2022 core->func->update(core, interlock, true); 2023 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 2024 disp->core->chan.base.device)) 2025 NV_ERROR(drm, "core notifier timeout\n"); 2026 2027 drm_for_each_encoder(encoder, drm->dev) { 2028 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2029 mstm = nouveau_encoder(encoder)->dp.mstm; 2030 if (mstm && mstm->modified) 2031 nv50_mstm_cleanup(mstm); 2032 } 2033 } 2034 } 2035 2036 static void 2037 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2038 { 2039 struct drm_plane_state *new_plane_state; 2040 struct drm_plane *plane; 2041 int i; 2042 2043 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2044 struct nv50_wndw *wndw = nv50_wndw(plane); 2045 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2046 if (wndw->func->update) 2047 wndw->func->update(wndw, interlock); 2048 } 2049 } 2050 } 2051 2052 static void 2053 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2054 { 2055 struct drm_device *dev = state->dev; 2056 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2057 struct drm_crtc *crtc; 2058 struct drm_plane_state *new_plane_state; 2059 struct drm_plane *plane; 2060 struct nouveau_drm *drm = nouveau_drm(dev); 2061 struct nv50_disp *disp = nv50_disp(dev); 2062 struct nv50_atom *atom = nv50_atom(state); 2063 struct nv50_core *core = disp->core; 2064 struct nv50_outp_atom *outp, *outt; 2065 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2066 int i; 2067 bool flushed = false; 2068 2069 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2070 nv50_crc_atomic_stop_reporting(state); 2071 drm_atomic_helper_wait_for_fences(dev, state, false); 2072 drm_atomic_helper_wait_for_dependencies(state); 2073 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2074 drm_atomic_helper_calc_timestamping_constants(state); 2075 2076 if (atom->lock_core) 2077 mutex_lock(&disp->mutex); 2078 2079 /* Disable head(s). */ 2080 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2081 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2082 struct nv50_head *head = nv50_head(crtc); 2083 2084 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2085 asyh->clr.mask, asyh->set.mask); 2086 2087 if (old_crtc_state->active && !new_crtc_state->active) { 2088 pm_runtime_put_noidle(dev->dev); 2089 drm_crtc_vblank_off(crtc); 2090 } 2091 2092 if (asyh->clr.mask) { 2093 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2094 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2095 } 2096 } 2097 2098 /* Disable plane(s). */ 2099 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2100 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2101 struct nv50_wndw *wndw = nv50_wndw(plane); 2102 2103 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2104 asyw->clr.mask, asyw->set.mask); 2105 if (!asyw->clr.mask) 2106 continue; 2107 2108 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2109 } 2110 2111 /* Disable output path(s). */ 2112 list_for_each_entry(outp, &atom->outp, head) { 2113 const struct drm_encoder_helper_funcs *help; 2114 struct drm_encoder *encoder; 2115 2116 encoder = outp->encoder; 2117 help = encoder->helper_private; 2118 2119 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2120 outp->clr.mask, outp->set.mask); 2121 2122 if (outp->clr.mask) { 2123 help->atomic_disable(encoder, state); 2124 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2125 if (outp->flush_disable) { 2126 nv50_disp_atomic_commit_wndw(state, interlock); 2127 nv50_disp_atomic_commit_core(state, interlock); 2128 memset(interlock, 0x00, sizeof(interlock)); 2129 2130 flushed = true; 2131 } 2132 } 2133 } 2134 2135 /* Flush disable. */ 2136 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2137 if (atom->flush_disable) { 2138 nv50_disp_atomic_commit_wndw(state, interlock); 2139 nv50_disp_atomic_commit_core(state, interlock); 2140 memset(interlock, 0x00, sizeof(interlock)); 2141 2142 flushed = true; 2143 } 2144 } 2145 2146 if (flushed) 2147 nv50_crc_atomic_release_notifier_contexts(state); 2148 nv50_crc_atomic_init_notifier_contexts(state); 2149 2150 /* Update output path(s). */ 2151 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2152 const struct drm_encoder_helper_funcs *help; 2153 struct drm_encoder *encoder; 2154 2155 encoder = outp->encoder; 2156 help = encoder->helper_private; 2157 2158 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2159 outp->set.mask, outp->clr.mask); 2160 2161 if (outp->set.mask) { 2162 help->atomic_enable(encoder, state); 2163 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2164 } 2165 2166 list_del(&outp->head); 2167 kfree(outp); 2168 } 2169 2170 /* Update head(s). */ 2171 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2172 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2173 struct nv50_head *head = nv50_head(crtc); 2174 2175 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2176 asyh->set.mask, asyh->clr.mask); 2177 2178 if (asyh->set.mask) { 2179 nv50_head_flush_set(head, asyh); 2180 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2181 } 2182 2183 if (new_crtc_state->active) { 2184 if (!old_crtc_state->active) { 2185 drm_crtc_vblank_on(crtc); 2186 pm_runtime_get_noresume(dev->dev); 2187 } 2188 if (new_crtc_state->event) 2189 drm_crtc_vblank_get(crtc); 2190 } 2191 } 2192 2193 /* Update window->head assignment. 2194 * 2195 * This has to happen in an update that's not interlocked with 2196 * any window channels to avoid hitting HW error checks. 2197 * 2198 *TODO: Proper handling of window ownership (Turing apparently 2199 * supports non-fixed mappings). 2200 */ 2201 if (core->assign_windows) { 2202 core->func->wndw.owner(core); 2203 nv50_disp_atomic_commit_core(state, interlock); 2204 core->assign_windows = false; 2205 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2206 } 2207 2208 /* Update plane(s). */ 2209 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2210 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2211 struct nv50_wndw *wndw = nv50_wndw(plane); 2212 2213 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2214 asyw->set.mask, asyw->clr.mask); 2215 if ( !asyw->set.mask && 2216 (!asyw->clr.mask || atom->flush_disable)) 2217 continue; 2218 2219 nv50_wndw_flush_set(wndw, interlock, asyw); 2220 } 2221 2222 /* Flush update. */ 2223 nv50_disp_atomic_commit_wndw(state, interlock); 2224 2225 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2226 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2227 interlock[NV50_DISP_INTERLOCK_OVLY] || 2228 interlock[NV50_DISP_INTERLOCK_WNDW] || 2229 !atom->state.legacy_cursor_update) 2230 nv50_disp_atomic_commit_core(state, interlock); 2231 else 2232 disp->core->func->update(disp->core, interlock, false); 2233 } 2234 2235 if (atom->lock_core) 2236 mutex_unlock(&disp->mutex); 2237 2238 /* Wait for HW to signal completion. */ 2239 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2240 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2241 struct nv50_wndw *wndw = nv50_wndw(plane); 2242 int ret = nv50_wndw_wait_armed(wndw, asyw); 2243 if (ret) 2244 NV_ERROR(drm, "%s: timeout\n", plane->name); 2245 } 2246 2247 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2248 if (new_crtc_state->event) { 2249 unsigned long flags; 2250 /* Get correct count/ts if racing with vblank irq */ 2251 if (new_crtc_state->active) 2252 drm_crtc_accurate_vblank_count(crtc); 2253 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2254 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2255 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2256 2257 new_crtc_state->event = NULL; 2258 if (new_crtc_state->active) 2259 drm_crtc_vblank_put(crtc); 2260 } 2261 } 2262 2263 nv50_crc_atomic_start_reporting(state); 2264 if (!flushed) 2265 nv50_crc_atomic_release_notifier_contexts(state); 2266 drm_atomic_helper_commit_hw_done(state); 2267 drm_atomic_helper_cleanup_planes(dev, state); 2268 drm_atomic_helper_commit_cleanup_done(state); 2269 drm_atomic_state_put(state); 2270 2271 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2272 pm_runtime_mark_last_busy(dev->dev); 2273 pm_runtime_put_autosuspend(dev->dev); 2274 } 2275 2276 static void 2277 nv50_disp_atomic_commit_work(struct work_struct *work) 2278 { 2279 struct drm_atomic_state *state = 2280 container_of(work, typeof(*state), commit_work); 2281 nv50_disp_atomic_commit_tail(state); 2282 } 2283 2284 static int 2285 nv50_disp_atomic_commit(struct drm_device *dev, 2286 struct drm_atomic_state *state, bool nonblock) 2287 { 2288 struct drm_plane_state *new_plane_state; 2289 struct drm_plane *plane; 2290 int ret, i; 2291 2292 ret = pm_runtime_get_sync(dev->dev); 2293 if (ret < 0 && ret != -EACCES) { 2294 pm_runtime_put_autosuspend(dev->dev); 2295 return ret; 2296 } 2297 2298 ret = drm_atomic_helper_setup_commit(state, nonblock); 2299 if (ret) 2300 goto done; 2301 2302 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2303 2304 ret = drm_atomic_helper_prepare_planes(dev, state); 2305 if (ret) 2306 goto done; 2307 2308 if (!nonblock) { 2309 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2310 if (ret) 2311 goto err_cleanup; 2312 } 2313 2314 ret = drm_atomic_helper_swap_state(state, true); 2315 if (ret) 2316 goto err_cleanup; 2317 2318 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2319 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2320 struct nv50_wndw *wndw = nv50_wndw(plane); 2321 2322 if (asyw->set.image) 2323 nv50_wndw_ntfy_enable(wndw, asyw); 2324 } 2325 2326 drm_atomic_state_get(state); 2327 2328 /* 2329 * Grab another RPM ref for the commit tail, which will release the 2330 * ref when it's finished 2331 */ 2332 pm_runtime_get_noresume(dev->dev); 2333 2334 if (nonblock) 2335 queue_work(system_unbound_wq, &state->commit_work); 2336 else 2337 nv50_disp_atomic_commit_tail(state); 2338 2339 err_cleanup: 2340 if (ret) 2341 drm_atomic_helper_cleanup_planes(dev, state); 2342 done: 2343 pm_runtime_put_autosuspend(dev->dev); 2344 return ret; 2345 } 2346 2347 static struct nv50_outp_atom * 2348 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2349 { 2350 struct nv50_outp_atom *outp; 2351 2352 list_for_each_entry(outp, &atom->outp, head) { 2353 if (outp->encoder == encoder) 2354 return outp; 2355 } 2356 2357 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2358 if (!outp) 2359 return ERR_PTR(-ENOMEM); 2360 2361 list_add(&outp->head, &atom->outp); 2362 outp->encoder = encoder; 2363 return outp; 2364 } 2365 2366 static int 2367 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2368 struct drm_connector_state *old_connector_state) 2369 { 2370 struct drm_encoder *encoder = old_connector_state->best_encoder; 2371 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2372 struct drm_crtc *crtc; 2373 struct nv50_outp_atom *outp; 2374 2375 if (!(crtc = old_connector_state->crtc)) 2376 return 0; 2377 2378 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2379 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2380 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2381 outp = nv50_disp_outp_atomic_add(atom, encoder); 2382 if (IS_ERR(outp)) 2383 return PTR_ERR(outp); 2384 2385 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2386 outp->flush_disable = true; 2387 atom->flush_disable = true; 2388 } 2389 outp->clr.ctrl = true; 2390 atom->lock_core = true; 2391 } 2392 2393 return 0; 2394 } 2395 2396 static int 2397 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2398 struct drm_connector_state *connector_state) 2399 { 2400 struct drm_encoder *encoder = connector_state->best_encoder; 2401 struct drm_crtc_state *new_crtc_state; 2402 struct drm_crtc *crtc; 2403 struct nv50_outp_atom *outp; 2404 2405 if (!(crtc = connector_state->crtc)) 2406 return 0; 2407 2408 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2409 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2410 outp = nv50_disp_outp_atomic_add(atom, encoder); 2411 if (IS_ERR(outp)) 2412 return PTR_ERR(outp); 2413 2414 outp->set.ctrl = true; 2415 atom->lock_core = true; 2416 } 2417 2418 return 0; 2419 } 2420 2421 static int 2422 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2423 { 2424 struct nv50_atom *atom = nv50_atom(state); 2425 struct nv50_core *core = nv50_disp(dev)->core; 2426 struct drm_connector_state *old_connector_state, *new_connector_state; 2427 struct drm_connector *connector; 2428 struct drm_crtc_state *new_crtc_state; 2429 struct drm_crtc *crtc; 2430 struct nv50_head *head; 2431 struct nv50_head_atom *asyh; 2432 int ret, i; 2433 2434 if (core->assign_windows && core->func->head->static_wndw_map) { 2435 drm_for_each_crtc(crtc, dev) { 2436 new_crtc_state = drm_atomic_get_crtc_state(state, 2437 crtc); 2438 if (IS_ERR(new_crtc_state)) 2439 return PTR_ERR(new_crtc_state); 2440 2441 head = nv50_head(crtc); 2442 asyh = nv50_head_atom(new_crtc_state); 2443 core->func->head->static_wndw_map(head, asyh); 2444 } 2445 } 2446 2447 /* We need to handle colour management on a per-plane basis. */ 2448 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2449 if (new_crtc_state->color_mgmt_changed) { 2450 ret = drm_atomic_add_affected_planes(state, crtc); 2451 if (ret) 2452 return ret; 2453 } 2454 } 2455 2456 ret = drm_atomic_helper_check(dev, state); 2457 if (ret) 2458 return ret; 2459 2460 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2461 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2462 if (ret) 2463 return ret; 2464 2465 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2466 if (ret) 2467 return ret; 2468 } 2469 2470 ret = drm_dp_mst_atomic_check(state); 2471 if (ret) 2472 return ret; 2473 2474 nv50_crc_atomic_check_outp(atom); 2475 2476 return 0; 2477 } 2478 2479 static void 2480 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2481 { 2482 struct nv50_atom *atom = nv50_atom(state); 2483 struct nv50_outp_atom *outp, *outt; 2484 2485 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2486 list_del(&outp->head); 2487 kfree(outp); 2488 } 2489 2490 drm_atomic_state_default_clear(state); 2491 } 2492 2493 static void 2494 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2495 { 2496 struct nv50_atom *atom = nv50_atom(state); 2497 drm_atomic_state_default_release(&atom->state); 2498 kfree(atom); 2499 } 2500 2501 static struct drm_atomic_state * 2502 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2503 { 2504 struct nv50_atom *atom; 2505 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2506 drm_atomic_state_init(dev, &atom->state) < 0) { 2507 kfree(atom); 2508 return NULL; 2509 } 2510 INIT_LIST_HEAD(&atom->outp); 2511 return &atom->state; 2512 } 2513 2514 static const struct drm_mode_config_funcs 2515 nv50_disp_func = { 2516 .fb_create = nouveau_user_framebuffer_create, 2517 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2518 .atomic_check = nv50_disp_atomic_check, 2519 .atomic_commit = nv50_disp_atomic_commit, 2520 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2521 .atomic_state_clear = nv50_disp_atomic_state_clear, 2522 .atomic_state_free = nv50_disp_atomic_state_free, 2523 }; 2524 2525 /****************************************************************************** 2526 * Init 2527 *****************************************************************************/ 2528 2529 static void 2530 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2531 { 2532 struct nouveau_drm *drm = nouveau_drm(dev); 2533 struct drm_encoder *encoder; 2534 struct drm_plane *plane; 2535 2536 drm_for_each_plane(plane, dev) { 2537 struct nv50_wndw *wndw = nv50_wndw(plane); 2538 if (plane->funcs != &nv50_wndw) 2539 continue; 2540 nv50_wndw_fini(wndw); 2541 } 2542 2543 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2544 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2545 nv50_mstm_fini(nouveau_encoder(encoder)); 2546 } 2547 2548 if (!runtime) 2549 cancel_work_sync(&drm->hpd_work); 2550 } 2551 2552 static int 2553 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2554 { 2555 struct nv50_core *core = nv50_disp(dev)->core; 2556 struct drm_encoder *encoder; 2557 struct drm_plane *plane; 2558 2559 if (resume || runtime) 2560 core->func->init(core); 2561 2562 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2563 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2564 struct nouveau_encoder *nv_encoder = 2565 nouveau_encoder(encoder); 2566 nv50_mstm_init(nv_encoder, runtime); 2567 } 2568 } 2569 2570 drm_for_each_plane(plane, dev) { 2571 struct nv50_wndw *wndw = nv50_wndw(plane); 2572 if (plane->funcs != &nv50_wndw) 2573 continue; 2574 nv50_wndw_init(wndw); 2575 } 2576 2577 return 0; 2578 } 2579 2580 static void 2581 nv50_display_destroy(struct drm_device *dev) 2582 { 2583 struct nv50_disp *disp = nv50_disp(dev); 2584 2585 nv50_audio_component_fini(nouveau_drm(dev)); 2586 2587 nvif_object_unmap(&disp->caps); 2588 nvif_object_dtor(&disp->caps); 2589 nv50_core_del(&disp->core); 2590 2591 nouveau_bo_unmap(disp->sync); 2592 if (disp->sync) 2593 nouveau_bo_unpin(disp->sync); 2594 nouveau_bo_ref(NULL, &disp->sync); 2595 2596 nouveau_display(dev)->priv = NULL; 2597 kfree(disp); 2598 } 2599 2600 int 2601 nv50_display_create(struct drm_device *dev) 2602 { 2603 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2604 struct nouveau_drm *drm = nouveau_drm(dev); 2605 struct dcb_table *dcb = &drm->vbios.dcb; 2606 struct drm_connector *connector, *tmp; 2607 struct nv50_disp *disp; 2608 struct dcb_output *dcbe; 2609 int crtcs, ret, i; 2610 bool has_mst = nv50_has_mst(drm); 2611 2612 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2613 if (!disp) 2614 return -ENOMEM; 2615 2616 mutex_init(&disp->mutex); 2617 2618 nouveau_display(dev)->priv = disp; 2619 nouveau_display(dev)->dtor = nv50_display_destroy; 2620 nouveau_display(dev)->init = nv50_display_init; 2621 nouveau_display(dev)->fini = nv50_display_fini; 2622 disp->disp = &nouveau_display(dev)->disp; 2623 dev->mode_config.funcs = &nv50_disp_func; 2624 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2625 dev->mode_config.normalize_zpos = true; 2626 2627 /* small shared memory area we use for notifiers and semaphores */ 2628 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2629 NOUVEAU_GEM_DOMAIN_VRAM, 2630 0, 0x0000, NULL, NULL, &disp->sync); 2631 if (!ret) { 2632 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2633 if (!ret) { 2634 ret = nouveau_bo_map(disp->sync); 2635 if (ret) 2636 nouveau_bo_unpin(disp->sync); 2637 } 2638 if (ret) 2639 nouveau_bo_ref(NULL, &disp->sync); 2640 } 2641 2642 if (ret) 2643 goto out; 2644 2645 /* allocate master evo channel */ 2646 ret = nv50_core_new(drm, &disp->core); 2647 if (ret) 2648 goto out; 2649 2650 disp->core->func->init(disp->core); 2651 if (disp->core->func->caps_init) { 2652 ret = disp->core->func->caps_init(drm, disp); 2653 if (ret) 2654 goto out; 2655 } 2656 2657 /* Assign the correct format modifiers */ 2658 if (disp->disp->object.oclass >= TU102_DISP) 2659 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2660 else 2661 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2662 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2663 else 2664 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2665 2666 /* create crtc objects to represent the hw heads */ 2667 if (disp->disp->object.oclass >= GV100_DISP) 2668 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2669 else 2670 if (disp->disp->object.oclass >= GF110_DISP) 2671 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2672 else 2673 crtcs = 0x3; 2674 2675 for (i = 0; i < fls(crtcs); i++) { 2676 struct nv50_head *head; 2677 2678 if (!(crtcs & (1 << i))) 2679 continue; 2680 2681 head = nv50_head_create(dev, i); 2682 if (IS_ERR(head)) { 2683 ret = PTR_ERR(head); 2684 goto out; 2685 } 2686 2687 if (has_mst) { 2688 head->msto = nv50_msto_new(dev, head, i); 2689 if (IS_ERR(head->msto)) { 2690 ret = PTR_ERR(head->msto); 2691 head->msto = NULL; 2692 goto out; 2693 } 2694 2695 /* 2696 * FIXME: This is a hack to workaround the following 2697 * issues: 2698 * 2699 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2700 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2701 * 2702 * Once these issues are closed, this should be 2703 * removed 2704 */ 2705 head->msto->encoder.possible_crtcs = crtcs; 2706 } 2707 } 2708 2709 /* create encoder/connector objects based on VBIOS DCB table */ 2710 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2711 connector = nouveau_connector_create(dev, dcbe); 2712 if (IS_ERR(connector)) 2713 continue; 2714 2715 if (dcbe->location == DCB_LOC_ON_CHIP) { 2716 switch (dcbe->type) { 2717 case DCB_OUTPUT_TMDS: 2718 case DCB_OUTPUT_LVDS: 2719 case DCB_OUTPUT_DP: 2720 ret = nv50_sor_create(connector, dcbe); 2721 break; 2722 case DCB_OUTPUT_ANALOG: 2723 ret = nv50_dac_create(connector, dcbe); 2724 break; 2725 default: 2726 ret = -ENODEV; 2727 break; 2728 } 2729 } else { 2730 ret = nv50_pior_create(connector, dcbe); 2731 } 2732 2733 if (ret) { 2734 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2735 dcbe->location, dcbe->type, 2736 ffs(dcbe->or) - 1, ret); 2737 ret = 0; 2738 } 2739 } 2740 2741 /* cull any connectors we created that don't have an encoder */ 2742 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2743 if (connector->possible_encoders) 2744 continue; 2745 2746 NV_WARN(drm, "%s has no encoders, removing\n", 2747 connector->name); 2748 connector->funcs->destroy(connector); 2749 } 2750 2751 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2752 dev->vblank_disable_immediate = true; 2753 2754 nv50_audio_component_init(drm); 2755 2756 out: 2757 if (ret) 2758 nv50_display_destroy(dev); 2759 return ret; 2760 } 2761 2762 /****************************************************************************** 2763 * Format modifiers 2764 *****************************************************************************/ 2765 2766 /**************************************************************** 2767 * Log2(block height) ----------------------------+ * 2768 * Page Kind ----------------------------------+ | * 2769 * Gob Height/Page Kind Generation ------+ | | * 2770 * Sector layout -------+ | | | * 2771 * Compression ------+ | | | | */ 2772 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2773 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2774 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2775 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2776 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2777 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2778 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2779 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2780 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2781 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2782 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2783 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2784 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2785 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2786 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2787 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2788 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2789 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2790 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2791 DRM_FORMAT_MOD_LINEAR, 2792 DRM_FORMAT_MOD_INVALID 2793 }; 2794 2795 /**************************************************************** 2796 * Log2(block height) ----------------------------+ * 2797 * Page Kind ----------------------------------+ | * 2798 * Gob Height/Page Kind Generation ------+ | | * 2799 * Sector layout -------+ | | | * 2800 * Compression ------+ | | | | */ 2801 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2802 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2803 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2804 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2805 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2806 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2807 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2808 DRM_FORMAT_MOD_LINEAR, 2809 DRM_FORMAT_MOD_INVALID 2810 }; 2811