1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_plane_helper.h> 39 #include <drm/drm_scdc_helper.h> 40 #include <drm/drm_edid.h> 41 42 #include <nvif/class.h> 43 #include <nvif/cl0002.h> 44 #include <nvif/cl5070.h> 45 #include <nvif/cl507d.h> 46 #include <nvif/event.h> 47 48 #include "nouveau_drv.h" 49 #include "nouveau_dma.h" 50 #include "nouveau_gem.h" 51 #include "nouveau_connector.h" 52 #include "nouveau_encoder.h" 53 #include "nouveau_fence.h" 54 #include "nouveau_fbcon.h" 55 56 #include <subdev/bios/dp.h> 57 58 /****************************************************************************** 59 * Atomic state 60 *****************************************************************************/ 61 62 struct nv50_outp_atom { 63 struct list_head head; 64 65 struct drm_encoder *encoder; 66 bool flush_disable; 67 68 union nv50_outp_atom_mask { 69 struct { 70 bool ctrl:1; 71 }; 72 u8 mask; 73 } set, clr; 74 }; 75 76 /****************************************************************************** 77 * EVO channel 78 *****************************************************************************/ 79 80 static int 81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 82 const s32 *oclass, u8 head, void *data, u32 size, 83 struct nv50_chan *chan) 84 { 85 struct nvif_sclass *sclass; 86 int ret, i, n; 87 88 chan->device = device; 89 90 ret = n = nvif_object_sclass_get(disp, &sclass); 91 if (ret < 0) 92 return ret; 93 94 while (oclass[0]) { 95 for (i = 0; i < n; i++) { 96 if (sclass[i].oclass == oclass[0]) { 97 ret = nvif_object_init(disp, 0, oclass[0], 98 data, size, &chan->user); 99 if (ret == 0) 100 nvif_object_map(&chan->user, NULL, 0); 101 nvif_object_sclass_put(&sclass); 102 return ret; 103 } 104 } 105 oclass++; 106 } 107 108 nvif_object_sclass_put(&sclass); 109 return -ENOSYS; 110 } 111 112 static void 113 nv50_chan_destroy(struct nv50_chan *chan) 114 { 115 nvif_object_fini(&chan->user); 116 } 117 118 /****************************************************************************** 119 * DMA EVO channel 120 *****************************************************************************/ 121 122 void 123 nv50_dmac_destroy(struct nv50_dmac *dmac) 124 { 125 nvif_object_fini(&dmac->vram); 126 nvif_object_fini(&dmac->sync); 127 128 nv50_chan_destroy(&dmac->base); 129 130 nvif_mem_fini(&dmac->push); 131 } 132 133 int 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 135 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 136 struct nv50_dmac *dmac) 137 { 138 struct nouveau_cli *cli = (void *)device->object.client; 139 struct nv50_disp_core_channel_dma_v0 *args = data; 140 u8 type = NVIF_MEM_COHERENT; 141 int ret; 142 143 mutex_init(&dmac->lock); 144 145 /* Pascal added support for 47-bit physical addresses, but some 146 * parts of EVO still only accept 40-bit PAs. 147 * 148 * To avoid issues on systems with large amounts of RAM, and on 149 * systems where an IOMMU maps pages at a high address, we need 150 * to allocate push buffers in VRAM instead. 151 * 152 * This appears to match NVIDIA's behaviour on Pascal. 153 */ 154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 155 type |= NVIF_MEM_VRAM; 156 157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 158 if (ret) 159 return ret; 160 161 dmac->ptr = dmac->push.object.map.ptr; 162 163 args->pushbuf = nvif_handle(&dmac->push.object); 164 165 ret = nv50_chan_create(device, disp, oclass, head, data, size, 166 &dmac->base); 167 if (ret) 168 return ret; 169 170 if (!syncbuf) 171 return 0; 172 173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 174 &(struct nv_dma_v0) { 175 .target = NV_DMA_V0_TARGET_VRAM, 176 .access = NV_DMA_V0_ACCESS_RDWR, 177 .start = syncbuf + 0x0000, 178 .limit = syncbuf + 0x0fff, 179 }, sizeof(struct nv_dma_v0), 180 &dmac->sync); 181 if (ret) 182 return ret; 183 184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 185 &(struct nv_dma_v0) { 186 .target = NV_DMA_V0_TARGET_VRAM, 187 .access = NV_DMA_V0_ACCESS_RDWR, 188 .start = 0, 189 .limit = device->info.ram_user - 1, 190 }, sizeof(struct nv_dma_v0), 191 &dmac->vram); 192 if (ret) 193 return ret; 194 195 return ret; 196 } 197 198 /****************************************************************************** 199 * EVO channel helpers 200 *****************************************************************************/ 201 u32 * 202 evo_wait(struct nv50_dmac *evoc, int nr) 203 { 204 struct nv50_dmac *dmac = evoc; 205 struct nvif_device *device = dmac->base.device; 206 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 207 208 mutex_lock(&dmac->lock); 209 if (put + nr >= (PAGE_SIZE / 4) - 8) { 210 dmac->ptr[put] = 0x20000000; 211 212 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 213 if (nvif_msec(device, 2000, 214 if (!nvif_rd32(&dmac->base.user, 0x0004)) 215 break; 216 ) < 0) { 217 mutex_unlock(&dmac->lock); 218 pr_err("nouveau: evo channel stalled\n"); 219 return NULL; 220 } 221 222 put = 0; 223 } 224 225 return dmac->ptr + put; 226 } 227 228 void 229 evo_kick(u32 *push, struct nv50_dmac *evoc) 230 { 231 struct nv50_dmac *dmac = evoc; 232 233 /* Push buffer fetches are not coherent with BAR1, we need to ensure 234 * writes have been flushed right through to VRAM before writing PUT. 235 */ 236 if (dmac->push.type & NVIF_MEM_VRAM) { 237 struct nvif_device *device = dmac->base.device; 238 nvif_wr32(&device->object, 0x070000, 0x00000001); 239 nvif_msec(device, 2000, 240 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 241 break; 242 ); 243 } 244 245 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 246 mutex_unlock(&dmac->lock); 247 } 248 249 /****************************************************************************** 250 * Output path helpers 251 *****************************************************************************/ 252 static void 253 nv50_outp_release(struct nouveau_encoder *nv_encoder) 254 { 255 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 256 struct { 257 struct nv50_disp_mthd_v1 base; 258 } args = { 259 .base.version = 1, 260 .base.method = NV50_DISP_MTHD_V1_RELEASE, 261 .base.hasht = nv_encoder->dcb->hasht, 262 .base.hashm = nv_encoder->dcb->hashm, 263 }; 264 265 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 266 nv_encoder->or = -1; 267 nv_encoder->link = 0; 268 } 269 270 static int 271 nv50_outp_acquire(struct nouveau_encoder *nv_encoder) 272 { 273 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 274 struct nv50_disp *disp = nv50_disp(drm->dev); 275 struct { 276 struct nv50_disp_mthd_v1 base; 277 struct nv50_disp_acquire_v0 info; 278 } args = { 279 .base.version = 1, 280 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 281 .base.hasht = nv_encoder->dcb->hasht, 282 .base.hashm = nv_encoder->dcb->hashm, 283 }; 284 int ret; 285 286 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 287 if (ret) { 288 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 289 return ret; 290 } 291 292 nv_encoder->or = args.info.or; 293 nv_encoder->link = args.info.link; 294 return 0; 295 } 296 297 static int 298 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 299 struct drm_crtc_state *crtc_state, 300 struct drm_connector_state *conn_state, 301 struct drm_display_mode *native_mode) 302 { 303 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 304 struct drm_display_mode *mode = &crtc_state->mode; 305 struct drm_connector *connector = conn_state->connector; 306 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 307 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 308 309 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 310 asyc->scaler.full = false; 311 if (!native_mode) 312 return 0; 313 314 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 315 switch (connector->connector_type) { 316 case DRM_MODE_CONNECTOR_LVDS: 317 case DRM_MODE_CONNECTOR_eDP: 318 /* Force use of scaler for non-EDID modes. */ 319 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) 320 break; 321 mode = native_mode; 322 asyc->scaler.full = true; 323 break; 324 default: 325 break; 326 } 327 } else { 328 mode = native_mode; 329 } 330 331 if (!drm_mode_equal(adjusted_mode, mode)) { 332 drm_mode_copy(adjusted_mode, mode); 333 crtc_state->mode_changed = true; 334 } 335 336 return 0; 337 } 338 339 static int 340 nv50_outp_atomic_check(struct drm_encoder *encoder, 341 struct drm_crtc_state *crtc_state, 342 struct drm_connector_state *conn_state) 343 { 344 struct nouveau_connector *nv_connector = 345 nouveau_connector(conn_state->connector); 346 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 347 nv_connector->native_mode); 348 } 349 350 /****************************************************************************** 351 * DAC 352 *****************************************************************************/ 353 static void 354 nv50_dac_disable(struct drm_encoder *encoder) 355 { 356 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 357 struct nv50_core *core = nv50_disp(encoder->dev)->core; 358 if (nv_encoder->crtc) 359 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 360 nv_encoder->crtc = NULL; 361 nv50_outp_release(nv_encoder); 362 } 363 364 static void 365 nv50_dac_enable(struct drm_encoder *encoder) 366 { 367 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 368 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 369 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 370 struct nv50_core *core = nv50_disp(encoder->dev)->core; 371 372 nv50_outp_acquire(nv_encoder); 373 374 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 375 asyh->or.depth = 0; 376 377 nv_encoder->crtc = encoder->crtc; 378 } 379 380 static enum drm_connector_status 381 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 382 { 383 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 384 struct nv50_disp *disp = nv50_disp(encoder->dev); 385 struct { 386 struct nv50_disp_mthd_v1 base; 387 struct nv50_disp_dac_load_v0 load; 388 } args = { 389 .base.version = 1, 390 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 391 .base.hasht = nv_encoder->dcb->hasht, 392 .base.hashm = nv_encoder->dcb->hashm, 393 }; 394 int ret; 395 396 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 397 if (args.load.data == 0) 398 args.load.data = 340; 399 400 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 401 if (ret || !args.load.load) 402 return connector_status_disconnected; 403 404 return connector_status_connected; 405 } 406 407 static const struct drm_encoder_helper_funcs 408 nv50_dac_help = { 409 .atomic_check = nv50_outp_atomic_check, 410 .enable = nv50_dac_enable, 411 .disable = nv50_dac_disable, 412 .detect = nv50_dac_detect 413 }; 414 415 static void 416 nv50_dac_destroy(struct drm_encoder *encoder) 417 { 418 drm_encoder_cleanup(encoder); 419 kfree(encoder); 420 } 421 422 static const struct drm_encoder_funcs 423 nv50_dac_func = { 424 .destroy = nv50_dac_destroy, 425 }; 426 427 static int 428 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 429 { 430 struct nouveau_drm *drm = nouveau_drm(connector->dev); 431 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 432 struct nvkm_i2c_bus *bus; 433 struct nouveau_encoder *nv_encoder; 434 struct drm_encoder *encoder; 435 int type = DRM_MODE_ENCODER_DAC; 436 437 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 438 if (!nv_encoder) 439 return -ENOMEM; 440 nv_encoder->dcb = dcbe; 441 442 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 443 if (bus) 444 nv_encoder->i2c = &bus->i2c; 445 446 encoder = to_drm_encoder(nv_encoder); 447 encoder->possible_crtcs = dcbe->heads; 448 encoder->possible_clones = 0; 449 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 450 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 451 drm_encoder_helper_add(encoder, &nv50_dac_help); 452 453 drm_connector_attach_encoder(connector, encoder); 454 return 0; 455 } 456 457 /****************************************************************************** 458 * Audio 459 *****************************************************************************/ 460 static void 461 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 462 { 463 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 464 struct nv50_disp *disp = nv50_disp(encoder->dev); 465 struct { 466 struct nv50_disp_mthd_v1 base; 467 struct nv50_disp_sor_hda_eld_v0 eld; 468 } args = { 469 .base.version = 1, 470 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 471 .base.hasht = nv_encoder->dcb->hasht, 472 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 473 (0x0100 << nv_crtc->index), 474 }; 475 476 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 477 } 478 479 static void 480 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 481 { 482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 483 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 484 struct nouveau_connector *nv_connector; 485 struct nv50_disp *disp = nv50_disp(encoder->dev); 486 struct __packed { 487 struct { 488 struct nv50_disp_mthd_v1 mthd; 489 struct nv50_disp_sor_hda_eld_v0 eld; 490 } base; 491 u8 data[sizeof(nv_connector->base.eld)]; 492 } args = { 493 .base.mthd.version = 1, 494 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 495 .base.mthd.hasht = nv_encoder->dcb->hasht, 496 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 497 (0x0100 << nv_crtc->index), 498 }; 499 500 nv_connector = nouveau_encoder_connector_get(nv_encoder); 501 if (!drm_detect_monitor_audio(nv_connector->edid)) 502 return; 503 504 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 505 506 nvif_mthd(&disp->disp->object, 0, &args, 507 sizeof(args.base) + drm_eld_size(args.data)); 508 } 509 510 /****************************************************************************** 511 * HDMI 512 *****************************************************************************/ 513 static void 514 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 515 { 516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 517 struct nv50_disp *disp = nv50_disp(encoder->dev); 518 struct { 519 struct nv50_disp_mthd_v1 base; 520 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 521 } args = { 522 .base.version = 1, 523 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 524 .base.hasht = nv_encoder->dcb->hasht, 525 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 526 (0x0100 << nv_crtc->index), 527 }; 528 529 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 530 } 531 532 static void 533 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 534 { 535 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 536 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 537 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 538 struct nv50_disp *disp = nv50_disp(encoder->dev); 539 struct { 540 struct nv50_disp_mthd_v1 base; 541 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 542 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 543 } args = { 544 .base.version = 1, 545 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 546 .base.hasht = nv_encoder->dcb->hasht, 547 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 548 (0x0100 << nv_crtc->index), 549 .pwr.state = 1, 550 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 551 }; 552 struct nouveau_connector *nv_connector; 553 struct drm_hdmi_info *hdmi; 554 u32 max_ac_packet; 555 union hdmi_infoframe avi_frame; 556 union hdmi_infoframe vendor_frame; 557 bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false; 558 u8 config; 559 int ret; 560 int size; 561 562 nv_connector = nouveau_encoder_connector_get(nv_encoder); 563 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 564 return; 565 566 hdmi = &nv_connector->base.display_info.hdmi; 567 scdc_supported = hdmi->scdc.supported; 568 569 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode, 570 scdc_supported); 571 if (!ret) { 572 /* We have an AVI InfoFrame, populate it to the display */ 573 args.pwr.avi_infoframe_length 574 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 575 } 576 577 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 578 &nv_connector->base, mode); 579 if (!ret) { 580 /* We have a Vendor InfoFrame, populate it to the display */ 581 args.pwr.vendor_infoframe_length 582 = hdmi_infoframe_pack(&vendor_frame, 583 args.infoframes 584 + args.pwr.avi_infoframe_length, 585 17); 586 } 587 588 max_ac_packet = mode->htotal - mode->hdisplay; 589 max_ac_packet -= args.pwr.rekey; 590 max_ac_packet -= 18; /* constant from tegra */ 591 args.pwr.max_ac_packet = max_ac_packet / 32; 592 593 if (hdmi->scdc.scrambling.supported) { 594 high_tmds_clock_ratio = mode->clock > 340000; 595 scrambling = high_tmds_clock_ratio || 596 hdmi->scdc.scrambling.low_rates; 597 } 598 599 args.pwr.scdc = 600 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 601 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 602 603 size = sizeof(args.base) 604 + sizeof(args.pwr) 605 + args.pwr.avi_infoframe_length 606 + args.pwr.vendor_infoframe_length; 607 nvif_mthd(&disp->disp->object, 0, &args, size); 608 609 nv50_audio_enable(encoder, mode); 610 611 /* If SCDC is supported by the downstream monitor, update 612 * divider / scrambling settings to what we programmed above. 613 */ 614 if (!hdmi->scdc.scrambling.supported) 615 return; 616 617 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 618 if (ret < 0) { 619 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 620 return; 621 } 622 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 623 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 624 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 625 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 626 if (ret < 0) 627 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 628 config, ret); 629 } 630 631 /****************************************************************************** 632 * MST 633 *****************************************************************************/ 634 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 635 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 636 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 637 638 struct nv50_mstm { 639 struct nouveau_encoder *outp; 640 641 struct drm_dp_mst_topology_mgr mgr; 642 struct nv50_msto *msto[4]; 643 644 bool modified; 645 bool disabled; 646 int links; 647 }; 648 649 struct nv50_mstc { 650 struct nv50_mstm *mstm; 651 struct drm_dp_mst_port *port; 652 struct drm_connector connector; 653 654 struct drm_display_mode *native; 655 struct edid *edid; 656 657 int pbn; 658 }; 659 660 struct nv50_msto { 661 struct drm_encoder encoder; 662 663 struct nv50_head *head; 664 struct nv50_mstc *mstc; 665 bool disabled; 666 }; 667 668 static struct drm_dp_payload * 669 nv50_msto_payload(struct nv50_msto *msto) 670 { 671 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 672 struct nv50_mstc *mstc = msto->mstc; 673 struct nv50_mstm *mstm = mstc->mstm; 674 int vcpi = mstc->port->vcpi.vcpi, i; 675 676 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 677 for (i = 0; i < mstm->mgr.max_payloads; i++) { 678 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 679 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 680 mstm->outp->base.base.name, i, payload->vcpi, 681 payload->start_slot, payload->num_slots); 682 } 683 684 for (i = 0; i < mstm->mgr.max_payloads; i++) { 685 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 686 if (payload->vcpi == vcpi) 687 return payload; 688 } 689 690 return NULL; 691 } 692 693 static void 694 nv50_msto_cleanup(struct nv50_msto *msto) 695 { 696 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 697 struct nv50_mstc *mstc = msto->mstc; 698 struct nv50_mstm *mstm = mstc->mstm; 699 700 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 701 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto)) 702 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 703 if (msto->disabled) { 704 msto->mstc = NULL; 705 msto->head = NULL; 706 msto->disabled = false; 707 } 708 } 709 710 static void 711 nv50_msto_prepare(struct nv50_msto *msto) 712 { 713 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 714 struct nv50_mstc *mstc = msto->mstc; 715 struct nv50_mstm *mstm = mstc->mstm; 716 struct { 717 struct nv50_disp_mthd_v1 base; 718 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 719 } args = { 720 .base.version = 1, 721 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 722 .base.hasht = mstm->outp->dcb->hasht, 723 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 724 (0x0100 << msto->head->base.index), 725 }; 726 727 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 728 if (mstc->port && mstc->port->vcpi.vcpi > 0) { 729 struct drm_dp_payload *payload = nv50_msto_payload(msto); 730 if (payload) { 731 args.vcpi.start_slot = payload->start_slot; 732 args.vcpi.num_slots = payload->num_slots; 733 args.vcpi.pbn = mstc->port->vcpi.pbn; 734 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 735 } 736 } 737 738 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 739 msto->encoder.name, msto->head->base.base.name, 740 args.vcpi.start_slot, args.vcpi.num_slots, 741 args.vcpi.pbn, args.vcpi.aligned_pbn); 742 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 743 } 744 745 static int 746 nv50_msto_atomic_check(struct drm_encoder *encoder, 747 struct drm_crtc_state *crtc_state, 748 struct drm_connector_state *conn_state) 749 { 750 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector); 751 struct nv50_mstm *mstm = mstc->mstm; 752 int bpp = conn_state->connector->display_info.bpc * 3; 753 int slots; 754 755 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp); 756 757 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 758 if (slots < 0) 759 return slots; 760 761 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 762 mstc->native); 763 } 764 765 static void 766 nv50_msto_enable(struct drm_encoder *encoder) 767 { 768 struct nv50_head *head = nv50_head(encoder->crtc); 769 struct nv50_msto *msto = nv50_msto(encoder); 770 struct nv50_mstc *mstc = NULL; 771 struct nv50_mstm *mstm = NULL; 772 struct drm_connector *connector; 773 struct drm_connector_list_iter conn_iter; 774 u8 proto, depth; 775 int slots; 776 bool r; 777 778 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 779 drm_for_each_connector_iter(connector, &conn_iter) { 780 if (connector->state->best_encoder == &msto->encoder) { 781 mstc = nv50_mstc(connector); 782 mstm = mstc->mstm; 783 break; 784 } 785 } 786 drm_connector_list_iter_end(&conn_iter); 787 788 if (WARN_ON(!mstc)) 789 return; 790 791 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 792 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots); 793 WARN_ON(!r); 794 795 if (!mstm->links++) 796 nv50_outp_acquire(mstm->outp); 797 798 if (mstm->outp->link & 1) 799 proto = 0x8; 800 else 801 proto = 0x9; 802 803 switch (mstc->connector.display_info.bpc) { 804 case 6: depth = 0x2; break; 805 case 8: depth = 0x5; break; 806 case 10: 807 default: depth = 0x6; break; 808 } 809 810 mstm->outp->update(mstm->outp, head->base.index, 811 nv50_head_atom(head->base.base.state), proto, depth); 812 813 msto->head = head; 814 msto->mstc = mstc; 815 mstm->modified = true; 816 } 817 818 static void 819 nv50_msto_disable(struct drm_encoder *encoder) 820 { 821 struct nv50_msto *msto = nv50_msto(encoder); 822 struct nv50_mstc *mstc = msto->mstc; 823 struct nv50_mstm *mstm = mstc->mstm; 824 825 if (mstc->port) 826 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 827 828 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 829 mstm->modified = true; 830 if (!--mstm->links) 831 mstm->disabled = true; 832 msto->disabled = true; 833 } 834 835 static const struct drm_encoder_helper_funcs 836 nv50_msto_help = { 837 .disable = nv50_msto_disable, 838 .enable = nv50_msto_enable, 839 .atomic_check = nv50_msto_atomic_check, 840 }; 841 842 static void 843 nv50_msto_destroy(struct drm_encoder *encoder) 844 { 845 struct nv50_msto *msto = nv50_msto(encoder); 846 drm_encoder_cleanup(&msto->encoder); 847 kfree(msto); 848 } 849 850 static const struct drm_encoder_funcs 851 nv50_msto = { 852 .destroy = nv50_msto_destroy, 853 }; 854 855 static int 856 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, 857 struct nv50_msto **pmsto) 858 { 859 struct nv50_msto *msto; 860 int ret; 861 862 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) 863 return -ENOMEM; 864 865 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 866 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); 867 if (ret) { 868 kfree(*pmsto); 869 *pmsto = NULL; 870 return ret; 871 } 872 873 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 874 msto->encoder.possible_crtcs = heads; 875 return 0; 876 } 877 878 static struct drm_encoder * 879 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 880 struct drm_connector_state *connector_state) 881 { 882 struct nv50_head *head = nv50_head(connector_state->crtc); 883 struct nv50_mstc *mstc = nv50_mstc(connector); 884 885 return &mstc->mstm->msto[head->base.index]->encoder; 886 } 887 888 static struct drm_encoder * 889 nv50_mstc_best_encoder(struct drm_connector *connector) 890 { 891 struct nv50_mstc *mstc = nv50_mstc(connector); 892 893 return &mstc->mstm->msto[0]->encoder; 894 } 895 896 static enum drm_mode_status 897 nv50_mstc_mode_valid(struct drm_connector *connector, 898 struct drm_display_mode *mode) 899 { 900 return MODE_OK; 901 } 902 903 static int 904 nv50_mstc_get_modes(struct drm_connector *connector) 905 { 906 struct nv50_mstc *mstc = nv50_mstc(connector); 907 int ret = 0; 908 909 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 910 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 911 if (mstc->edid) 912 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 913 914 if (!mstc->connector.display_info.bpc) 915 mstc->connector.display_info.bpc = 8; 916 917 if (mstc->native) 918 drm_mode_destroy(mstc->connector.dev, mstc->native); 919 mstc->native = nouveau_conn_native_mode(&mstc->connector); 920 return ret; 921 } 922 923 static const struct drm_connector_helper_funcs 924 nv50_mstc_help = { 925 .get_modes = nv50_mstc_get_modes, 926 .mode_valid = nv50_mstc_mode_valid, 927 .best_encoder = nv50_mstc_best_encoder, 928 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 929 }; 930 931 static enum drm_connector_status 932 nv50_mstc_detect(struct drm_connector *connector, bool force) 933 { 934 struct nv50_mstc *mstc = nv50_mstc(connector); 935 enum drm_connector_status conn_status; 936 int ret; 937 938 if (!mstc->port) 939 return connector_status_disconnected; 940 941 ret = pm_runtime_get_sync(connector->dev->dev); 942 if (ret < 0 && ret != -EACCES) 943 return connector_status_disconnected; 944 945 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr, 946 mstc->port); 947 948 pm_runtime_mark_last_busy(connector->dev->dev); 949 pm_runtime_put_autosuspend(connector->dev->dev); 950 return conn_status; 951 } 952 953 static void 954 nv50_mstc_destroy(struct drm_connector *connector) 955 { 956 struct nv50_mstc *mstc = nv50_mstc(connector); 957 drm_connector_cleanup(&mstc->connector); 958 kfree(mstc); 959 } 960 961 static const struct drm_connector_funcs 962 nv50_mstc = { 963 .reset = nouveau_conn_reset, 964 .detect = nv50_mstc_detect, 965 .fill_modes = drm_helper_probe_single_connector_modes, 966 .destroy = nv50_mstc_destroy, 967 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 968 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 969 .atomic_set_property = nouveau_conn_atomic_set_property, 970 .atomic_get_property = nouveau_conn_atomic_get_property, 971 }; 972 973 static int 974 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 975 const char *path, struct nv50_mstc **pmstc) 976 { 977 struct drm_device *dev = mstm->outp->base.base.dev; 978 struct nv50_mstc *mstc; 979 int ret, i; 980 981 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 982 return -ENOMEM; 983 mstc->mstm = mstm; 984 mstc->port = port; 985 986 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 987 DRM_MODE_CONNECTOR_DisplayPort); 988 if (ret) { 989 kfree(*pmstc); 990 *pmstc = NULL; 991 return ret; 992 } 993 994 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 995 996 mstc->connector.funcs->reset(&mstc->connector); 997 nouveau_conn_attach_properties(&mstc->connector); 998 999 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) 1000 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); 1001 1002 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1003 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1004 drm_connector_set_path_property(&mstc->connector, path); 1005 return 0; 1006 } 1007 1008 static void 1009 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1010 { 1011 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1012 struct drm_encoder *encoder; 1013 int ret; 1014 1015 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1016 ret = drm_dp_check_act_status(&mstm->mgr); 1017 1018 ret = drm_dp_update_payload_part2(&mstm->mgr); 1019 1020 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1021 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1022 struct nv50_msto *msto = nv50_msto(encoder); 1023 struct nv50_mstc *mstc = msto->mstc; 1024 if (mstc && mstc->mstm == mstm) 1025 nv50_msto_cleanup(msto); 1026 } 1027 } 1028 1029 mstm->modified = false; 1030 } 1031 1032 static void 1033 nv50_mstm_prepare(struct nv50_mstm *mstm) 1034 { 1035 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1036 struct drm_encoder *encoder; 1037 int ret; 1038 1039 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1040 ret = drm_dp_update_payload_part1(&mstm->mgr); 1041 1042 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1043 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1044 struct nv50_msto *msto = nv50_msto(encoder); 1045 struct nv50_mstc *mstc = msto->mstc; 1046 if (mstc && mstc->mstm == mstm) 1047 nv50_msto_prepare(msto); 1048 } 1049 } 1050 1051 if (mstm->disabled) { 1052 if (!mstm->links) 1053 nv50_outp_release(mstm->outp); 1054 mstm->disabled = false; 1055 } 1056 } 1057 1058 static void 1059 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr) 1060 { 1061 struct nv50_mstm *mstm = nv50_mstm(mgr); 1062 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev); 1063 } 1064 1065 static void 1066 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 1067 struct drm_connector *connector) 1068 { 1069 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1070 struct nv50_mstc *mstc = nv50_mstc(connector); 1071 1072 drm_connector_unregister(&mstc->connector); 1073 1074 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 1075 1076 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL); 1077 mstc->port = NULL; 1078 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex); 1079 1080 drm_connector_put(&mstc->connector); 1081 } 1082 1083 static void 1084 nv50_mstm_register_connector(struct drm_connector *connector) 1085 { 1086 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1087 1088 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 1089 1090 drm_connector_register(connector); 1091 } 1092 1093 static struct drm_connector * 1094 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1095 struct drm_dp_mst_port *port, const char *path) 1096 { 1097 struct nv50_mstm *mstm = nv50_mstm(mgr); 1098 struct nv50_mstc *mstc; 1099 int ret; 1100 1101 ret = nv50_mstc_new(mstm, port, path, &mstc); 1102 if (ret) { 1103 if (mstc) 1104 mstc->connector.funcs->destroy(&mstc->connector); 1105 return NULL; 1106 } 1107 1108 return &mstc->connector; 1109 } 1110 1111 static const struct drm_dp_mst_topology_cbs 1112 nv50_mstm = { 1113 .add_connector = nv50_mstm_add_connector, 1114 .register_connector = nv50_mstm_register_connector, 1115 .destroy_connector = nv50_mstm_destroy_connector, 1116 .hotplug = nv50_mstm_hotplug, 1117 }; 1118 1119 void 1120 nv50_mstm_service(struct nv50_mstm *mstm) 1121 { 1122 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1123 bool handled = true; 1124 int ret; 1125 u8 esi[8] = {}; 1126 1127 if (!aux) 1128 return; 1129 1130 while (handled) { 1131 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1132 if (ret != 8) { 1133 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1134 return; 1135 } 1136 1137 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1138 if (!handled) 1139 break; 1140 1141 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1142 } 1143 } 1144 1145 void 1146 nv50_mstm_remove(struct nv50_mstm *mstm) 1147 { 1148 if (mstm) 1149 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1150 } 1151 1152 static int 1153 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1154 { 1155 struct nouveau_encoder *outp = mstm->outp; 1156 struct { 1157 struct nv50_disp_mthd_v1 base; 1158 struct nv50_disp_sor_dp_mst_link_v0 mst; 1159 } args = { 1160 .base.version = 1, 1161 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1162 .base.hasht = outp->dcb->hasht, 1163 .base.hashm = outp->dcb->hashm, 1164 .mst.state = state, 1165 }; 1166 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1167 struct nvif_object *disp = &drm->display->disp.object; 1168 int ret; 1169 1170 if (dpcd >= 0x12) { 1171 /* Even if we're enabling MST, start with disabling the 1172 * branching unit to clear any sink-side MST topology state 1173 * that wasn't set by us 1174 */ 1175 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1176 if (ret < 0) 1177 return ret; 1178 1179 if (state) { 1180 /* Now, start initializing */ 1181 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1182 DP_MST_EN); 1183 if (ret < 0) 1184 return ret; 1185 } 1186 } 1187 1188 return nvif_mthd(disp, 0, &args, sizeof(args)); 1189 } 1190 1191 int 1192 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1193 { 1194 struct drm_dp_aux *aux; 1195 int ret; 1196 bool old_state, new_state; 1197 u8 mstm_ctrl; 1198 1199 if (!mstm) 1200 return 0; 1201 1202 mutex_lock(&mstm->mgr.lock); 1203 1204 old_state = mstm->mgr.mst_state; 1205 new_state = old_state; 1206 aux = mstm->mgr.aux; 1207 1208 if (old_state) { 1209 /* Just check that the MST hub is still as we expect it */ 1210 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1211 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1212 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1213 new_state = false; 1214 } 1215 } else if (dpcd[0] >= 0x12) { 1216 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1217 if (ret < 0) 1218 goto probe_error; 1219 1220 if (!(dpcd[1] & DP_MST_CAP)) 1221 dpcd[0] = 0x11; 1222 else 1223 new_state = allow; 1224 } 1225 1226 if (new_state == old_state) { 1227 mutex_unlock(&mstm->mgr.lock); 1228 return new_state; 1229 } 1230 1231 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1232 if (ret) 1233 goto probe_error; 1234 1235 mutex_unlock(&mstm->mgr.lock); 1236 1237 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1238 if (ret) 1239 return nv50_mstm_enable(mstm, dpcd[0], 0); 1240 1241 return new_state; 1242 1243 probe_error: 1244 mutex_unlock(&mstm->mgr.lock); 1245 return ret; 1246 } 1247 1248 static void 1249 nv50_mstm_fini(struct nv50_mstm *mstm) 1250 { 1251 if (mstm && mstm->mgr.mst_state) 1252 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1253 } 1254 1255 static void 1256 nv50_mstm_init(struct nv50_mstm *mstm) 1257 { 1258 if (mstm && mstm->mgr.mst_state) 1259 drm_dp_mst_topology_mgr_resume(&mstm->mgr); 1260 } 1261 1262 static void 1263 nv50_mstm_del(struct nv50_mstm **pmstm) 1264 { 1265 struct nv50_mstm *mstm = *pmstm; 1266 if (mstm) { 1267 kfree(*pmstm); 1268 *pmstm = NULL; 1269 } 1270 } 1271 1272 static int 1273 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1274 int conn_base_id, struct nv50_mstm **pmstm) 1275 { 1276 const int max_payloads = hweight8(outp->dcb->heads); 1277 struct drm_device *dev = outp->base.base.dev; 1278 struct nv50_mstm *mstm; 1279 int ret, i; 1280 u8 dpcd; 1281 1282 /* This is a workaround for some monitors not functioning 1283 * correctly in MST mode on initial module load. I think 1284 * some bad interaction with the VBIOS may be responsible. 1285 * 1286 * A good ol' off and on again seems to work here ;) 1287 */ 1288 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1289 if (ret >= 0 && dpcd >= 0x12) 1290 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1291 1292 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1293 return -ENOMEM; 1294 mstm->outp = outp; 1295 mstm->mgr.cbs = &nv50_mstm; 1296 1297 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1298 max_payloads, conn_base_id); 1299 if (ret) 1300 return ret; 1301 1302 for (i = 0; i < max_payloads; i++) { 1303 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, 1304 i, &mstm->msto[i]); 1305 if (ret) 1306 return ret; 1307 } 1308 1309 return 0; 1310 } 1311 1312 /****************************************************************************** 1313 * SOR 1314 *****************************************************************************/ 1315 static void 1316 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1317 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1318 { 1319 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1320 struct nv50_core *core = disp->core; 1321 1322 if (!asyh) { 1323 nv_encoder->ctrl &= ~BIT(head); 1324 if (!(nv_encoder->ctrl & 0x0000000f)) 1325 nv_encoder->ctrl = 0; 1326 } else { 1327 nv_encoder->ctrl |= proto << 8; 1328 nv_encoder->ctrl |= BIT(head); 1329 asyh->or.depth = depth; 1330 } 1331 1332 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1333 } 1334 1335 static void 1336 nv50_sor_disable(struct drm_encoder *encoder) 1337 { 1338 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1339 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1340 1341 nv_encoder->crtc = NULL; 1342 1343 if (nv_crtc) { 1344 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1345 u8 pwr; 1346 1347 if (aux) { 1348 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1349 if (ret == 0) { 1350 pwr &= ~DP_SET_POWER_MASK; 1351 pwr |= DP_SET_POWER_D3; 1352 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1353 } 1354 } 1355 1356 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1357 nv50_audio_disable(encoder, nv_crtc); 1358 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1359 nv50_outp_release(nv_encoder); 1360 } 1361 } 1362 1363 static void 1364 nv50_sor_enable(struct drm_encoder *encoder) 1365 { 1366 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1367 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1368 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1369 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1370 struct { 1371 struct nv50_disp_mthd_v1 base; 1372 struct nv50_disp_sor_lvds_script_v0 lvds; 1373 } lvds = { 1374 .base.version = 1, 1375 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1376 .base.hasht = nv_encoder->dcb->hasht, 1377 .base.hashm = nv_encoder->dcb->hashm, 1378 }; 1379 struct nv50_disp *disp = nv50_disp(encoder->dev); 1380 struct drm_device *dev = encoder->dev; 1381 struct nouveau_drm *drm = nouveau_drm(dev); 1382 struct nouveau_connector *nv_connector; 1383 struct nvbios *bios = &drm->vbios; 1384 u8 proto = 0xf; 1385 u8 depth = 0x0; 1386 1387 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1388 nv_encoder->crtc = encoder->crtc; 1389 nv50_outp_acquire(nv_encoder); 1390 1391 switch (nv_encoder->dcb->type) { 1392 case DCB_OUTPUT_TMDS: 1393 if (nv_encoder->link & 1) { 1394 proto = 0x1; 1395 /* Only enable dual-link if: 1396 * - Need to (i.e. rate > 165MHz) 1397 * - DCB says we can 1398 * - Not an HDMI monitor, since there's no dual-link 1399 * on HDMI. 1400 */ 1401 if (mode->clock >= 165000 && 1402 nv_encoder->dcb->duallink_possible && 1403 !drm_detect_hdmi_monitor(nv_connector->edid)) 1404 proto |= 0x4; 1405 } else { 1406 proto = 0x2; 1407 } 1408 1409 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1410 break; 1411 case DCB_OUTPUT_LVDS: 1412 proto = 0x0; 1413 1414 if (bios->fp_no_ddc) { 1415 if (bios->fp.dual_link) 1416 lvds.lvds.script |= 0x0100; 1417 if (bios->fp.if_is_24bit) 1418 lvds.lvds.script |= 0x0200; 1419 } else { 1420 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1421 if (((u8 *)nv_connector->edid)[121] == 2) 1422 lvds.lvds.script |= 0x0100; 1423 } else 1424 if (mode->clock >= bios->fp.duallink_transition_clk) { 1425 lvds.lvds.script |= 0x0100; 1426 } 1427 1428 if (lvds.lvds.script & 0x0100) { 1429 if (bios->fp.strapless_is_24bit & 2) 1430 lvds.lvds.script |= 0x0200; 1431 } else { 1432 if (bios->fp.strapless_is_24bit & 1) 1433 lvds.lvds.script |= 0x0200; 1434 } 1435 1436 if (nv_connector->base.display_info.bpc == 8) 1437 lvds.lvds.script |= 0x0200; 1438 } 1439 1440 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1441 break; 1442 case DCB_OUTPUT_DP: 1443 if (nv_connector->base.display_info.bpc == 6) 1444 depth = 0x2; 1445 else 1446 if (nv_connector->base.display_info.bpc == 8) 1447 depth = 0x5; 1448 else 1449 depth = 0x6; 1450 1451 if (nv_encoder->link & 1) 1452 proto = 0x8; 1453 else 1454 proto = 0x9; 1455 1456 nv50_audio_enable(encoder, mode); 1457 break; 1458 default: 1459 BUG(); 1460 break; 1461 } 1462 1463 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1464 } 1465 1466 static const struct drm_encoder_helper_funcs 1467 nv50_sor_help = { 1468 .atomic_check = nv50_outp_atomic_check, 1469 .enable = nv50_sor_enable, 1470 .disable = nv50_sor_disable, 1471 }; 1472 1473 static void 1474 nv50_sor_destroy(struct drm_encoder *encoder) 1475 { 1476 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1477 nv50_mstm_del(&nv_encoder->dp.mstm); 1478 drm_encoder_cleanup(encoder); 1479 kfree(encoder); 1480 } 1481 1482 static const struct drm_encoder_funcs 1483 nv50_sor_func = { 1484 .destroy = nv50_sor_destroy, 1485 }; 1486 1487 static int 1488 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1489 { 1490 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1491 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1492 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1493 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1494 struct nouveau_encoder *nv_encoder; 1495 struct drm_encoder *encoder; 1496 u8 ver, hdr, cnt, len; 1497 u32 data; 1498 int type, ret; 1499 1500 switch (dcbe->type) { 1501 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1502 case DCB_OUTPUT_TMDS: 1503 case DCB_OUTPUT_DP: 1504 default: 1505 type = DRM_MODE_ENCODER_TMDS; 1506 break; 1507 } 1508 1509 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1510 if (!nv_encoder) 1511 return -ENOMEM; 1512 nv_encoder->dcb = dcbe; 1513 nv_encoder->update = nv50_sor_update; 1514 1515 encoder = to_drm_encoder(nv_encoder); 1516 encoder->possible_crtcs = dcbe->heads; 1517 encoder->possible_clones = 0; 1518 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1519 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1520 drm_encoder_helper_add(encoder, &nv50_sor_help); 1521 1522 drm_connector_attach_encoder(connector, encoder); 1523 1524 if (dcbe->type == DCB_OUTPUT_DP) { 1525 struct nv50_disp *disp = nv50_disp(encoder->dev); 1526 struct nvkm_i2c_aux *aux = 1527 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1528 if (aux) { 1529 if (disp->disp->object.oclass < GF110_DISP) { 1530 /* HW has no support for address-only 1531 * transactions, so we're required to 1532 * use custom I2C-over-AUX code. 1533 */ 1534 nv_encoder->i2c = &aux->i2c; 1535 } else { 1536 nv_encoder->i2c = &nv_connector->aux.ddc; 1537 } 1538 nv_encoder->aux = aux; 1539 } 1540 1541 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) && 1542 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) { 1543 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, 1544 nv_connector->base.base.id, 1545 &nv_encoder->dp.mstm); 1546 if (ret) 1547 return ret; 1548 } 1549 } else { 1550 struct nvkm_i2c_bus *bus = 1551 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1552 if (bus) 1553 nv_encoder->i2c = &bus->i2c; 1554 } 1555 1556 return 0; 1557 } 1558 1559 /****************************************************************************** 1560 * PIOR 1561 *****************************************************************************/ 1562 static int 1563 nv50_pior_atomic_check(struct drm_encoder *encoder, 1564 struct drm_crtc_state *crtc_state, 1565 struct drm_connector_state *conn_state) 1566 { 1567 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1568 if (ret) 1569 return ret; 1570 crtc_state->adjusted_mode.clock *= 2; 1571 return 0; 1572 } 1573 1574 static void 1575 nv50_pior_disable(struct drm_encoder *encoder) 1576 { 1577 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1578 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1579 if (nv_encoder->crtc) 1580 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1581 nv_encoder->crtc = NULL; 1582 nv50_outp_release(nv_encoder); 1583 } 1584 1585 static void 1586 nv50_pior_enable(struct drm_encoder *encoder) 1587 { 1588 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1589 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1590 struct nouveau_connector *nv_connector; 1591 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1592 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1593 u8 owner = 1 << nv_crtc->index; 1594 u8 proto; 1595 1596 nv50_outp_acquire(nv_encoder); 1597 1598 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1599 switch (nv_connector->base.display_info.bpc) { 1600 case 10: asyh->or.depth = 0x6; break; 1601 case 8: asyh->or.depth = 0x5; break; 1602 case 6: asyh->or.depth = 0x2; break; 1603 default: asyh->or.depth = 0x0; break; 1604 } 1605 1606 switch (nv_encoder->dcb->type) { 1607 case DCB_OUTPUT_TMDS: 1608 case DCB_OUTPUT_DP: 1609 proto = 0x0; 1610 break; 1611 default: 1612 BUG(); 1613 break; 1614 } 1615 1616 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1617 nv_encoder->crtc = encoder->crtc; 1618 } 1619 1620 static const struct drm_encoder_helper_funcs 1621 nv50_pior_help = { 1622 .atomic_check = nv50_pior_atomic_check, 1623 .enable = nv50_pior_enable, 1624 .disable = nv50_pior_disable, 1625 }; 1626 1627 static void 1628 nv50_pior_destroy(struct drm_encoder *encoder) 1629 { 1630 drm_encoder_cleanup(encoder); 1631 kfree(encoder); 1632 } 1633 1634 static const struct drm_encoder_funcs 1635 nv50_pior_func = { 1636 .destroy = nv50_pior_destroy, 1637 }; 1638 1639 static int 1640 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1641 { 1642 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1643 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1644 struct nvkm_i2c_bus *bus = NULL; 1645 struct nvkm_i2c_aux *aux = NULL; 1646 struct i2c_adapter *ddc; 1647 struct nouveau_encoder *nv_encoder; 1648 struct drm_encoder *encoder; 1649 int type; 1650 1651 switch (dcbe->type) { 1652 case DCB_OUTPUT_TMDS: 1653 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1654 ddc = bus ? &bus->i2c : NULL; 1655 type = DRM_MODE_ENCODER_TMDS; 1656 break; 1657 case DCB_OUTPUT_DP: 1658 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1659 ddc = aux ? &aux->i2c : NULL; 1660 type = DRM_MODE_ENCODER_TMDS; 1661 break; 1662 default: 1663 return -ENODEV; 1664 } 1665 1666 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1667 if (!nv_encoder) 1668 return -ENOMEM; 1669 nv_encoder->dcb = dcbe; 1670 nv_encoder->i2c = ddc; 1671 nv_encoder->aux = aux; 1672 1673 encoder = to_drm_encoder(nv_encoder); 1674 encoder->possible_crtcs = dcbe->heads; 1675 encoder->possible_clones = 0; 1676 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1677 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1678 drm_encoder_helper_add(encoder, &nv50_pior_help); 1679 1680 drm_connector_attach_encoder(connector, encoder); 1681 return 0; 1682 } 1683 1684 /****************************************************************************** 1685 * Atomic 1686 *****************************************************************************/ 1687 1688 static void 1689 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1690 { 1691 struct nouveau_drm *drm = nouveau_drm(state->dev); 1692 struct nv50_disp *disp = nv50_disp(drm->dev); 1693 struct nv50_core *core = disp->core; 1694 struct nv50_mstm *mstm; 1695 struct drm_encoder *encoder; 1696 1697 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1698 1699 drm_for_each_encoder(encoder, drm->dev) { 1700 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1701 mstm = nouveau_encoder(encoder)->dp.mstm; 1702 if (mstm && mstm->modified) 1703 nv50_mstm_prepare(mstm); 1704 } 1705 } 1706 1707 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1708 core->func->update(core, interlock, true); 1709 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1710 disp->core->chan.base.device)) 1711 NV_ERROR(drm, "core notifier timeout\n"); 1712 1713 drm_for_each_encoder(encoder, drm->dev) { 1714 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1715 mstm = nouveau_encoder(encoder)->dp.mstm; 1716 if (mstm && mstm->modified) 1717 nv50_mstm_cleanup(mstm); 1718 } 1719 } 1720 } 1721 1722 static void 1723 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1724 { 1725 struct drm_plane_state *new_plane_state; 1726 struct drm_plane *plane; 1727 int i; 1728 1729 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1730 struct nv50_wndw *wndw = nv50_wndw(plane); 1731 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1732 if (wndw->func->update) 1733 wndw->func->update(wndw, interlock); 1734 } 1735 } 1736 } 1737 1738 static void 1739 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1740 { 1741 struct drm_device *dev = state->dev; 1742 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1743 struct drm_crtc *crtc; 1744 struct drm_plane_state *new_plane_state; 1745 struct drm_plane *plane; 1746 struct nouveau_drm *drm = nouveau_drm(dev); 1747 struct nv50_disp *disp = nv50_disp(dev); 1748 struct nv50_atom *atom = nv50_atom(state); 1749 struct nv50_outp_atom *outp, *outt; 1750 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1751 int i; 1752 1753 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1754 drm_atomic_helper_wait_for_fences(dev, state, false); 1755 drm_atomic_helper_wait_for_dependencies(state); 1756 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1757 1758 if (atom->lock_core) 1759 mutex_lock(&disp->mutex); 1760 1761 /* Disable head(s). */ 1762 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1763 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1764 struct nv50_head *head = nv50_head(crtc); 1765 1766 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1767 asyh->clr.mask, asyh->set.mask); 1768 if (old_crtc_state->active && !new_crtc_state->active) 1769 drm_crtc_vblank_off(crtc); 1770 1771 if (asyh->clr.mask) { 1772 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1773 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1774 } 1775 } 1776 1777 /* Disable plane(s). */ 1778 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1779 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1780 struct nv50_wndw *wndw = nv50_wndw(plane); 1781 1782 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1783 asyw->clr.mask, asyw->set.mask); 1784 if (!asyw->clr.mask) 1785 continue; 1786 1787 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1788 } 1789 1790 /* Disable output path(s). */ 1791 list_for_each_entry(outp, &atom->outp, head) { 1792 const struct drm_encoder_helper_funcs *help; 1793 struct drm_encoder *encoder; 1794 1795 encoder = outp->encoder; 1796 help = encoder->helper_private; 1797 1798 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1799 outp->clr.mask, outp->set.mask); 1800 1801 if (outp->clr.mask) { 1802 help->disable(encoder); 1803 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1804 if (outp->flush_disable) { 1805 nv50_disp_atomic_commit_wndw(state, interlock); 1806 nv50_disp_atomic_commit_core(state, interlock); 1807 memset(interlock, 0x00, sizeof(interlock)); 1808 } 1809 } 1810 } 1811 1812 /* Flush disable. */ 1813 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1814 if (atom->flush_disable) { 1815 nv50_disp_atomic_commit_wndw(state, interlock); 1816 nv50_disp_atomic_commit_core(state, interlock); 1817 memset(interlock, 0x00, sizeof(interlock)); 1818 } 1819 } 1820 1821 /* Update output path(s). */ 1822 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1823 const struct drm_encoder_helper_funcs *help; 1824 struct drm_encoder *encoder; 1825 1826 encoder = outp->encoder; 1827 help = encoder->helper_private; 1828 1829 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 1830 outp->set.mask, outp->clr.mask); 1831 1832 if (outp->set.mask) { 1833 help->enable(encoder); 1834 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1835 } 1836 1837 list_del(&outp->head); 1838 kfree(outp); 1839 } 1840 1841 /* Update head(s). */ 1842 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1843 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1844 struct nv50_head *head = nv50_head(crtc); 1845 1846 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 1847 asyh->set.mask, asyh->clr.mask); 1848 1849 if (asyh->set.mask) { 1850 nv50_head_flush_set(head, asyh); 1851 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 1852 } 1853 1854 if (new_crtc_state->active) { 1855 if (!old_crtc_state->active) 1856 drm_crtc_vblank_on(crtc); 1857 if (new_crtc_state->event) 1858 drm_crtc_vblank_get(crtc); 1859 } 1860 } 1861 1862 /* Update plane(s). */ 1863 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1864 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1865 struct nv50_wndw *wndw = nv50_wndw(plane); 1866 1867 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 1868 asyw->set.mask, asyw->clr.mask); 1869 if ( !asyw->set.mask && 1870 (!asyw->clr.mask || atom->flush_disable)) 1871 continue; 1872 1873 nv50_wndw_flush_set(wndw, interlock, asyw); 1874 } 1875 1876 /* Flush update. */ 1877 nv50_disp_atomic_commit_wndw(state, interlock); 1878 1879 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 1880 if (interlock[NV50_DISP_INTERLOCK_BASE] || 1881 interlock[NV50_DISP_INTERLOCK_OVLY] || 1882 interlock[NV50_DISP_INTERLOCK_WNDW] || 1883 !atom->state.legacy_cursor_update) 1884 nv50_disp_atomic_commit_core(state, interlock); 1885 else 1886 disp->core->func->update(disp->core, interlock, false); 1887 } 1888 1889 if (atom->lock_core) 1890 mutex_unlock(&disp->mutex); 1891 1892 /* Wait for HW to signal completion. */ 1893 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1894 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1895 struct nv50_wndw *wndw = nv50_wndw(plane); 1896 int ret = nv50_wndw_wait_armed(wndw, asyw); 1897 if (ret) 1898 NV_ERROR(drm, "%s: timeout\n", plane->name); 1899 } 1900 1901 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 1902 if (new_crtc_state->event) { 1903 unsigned long flags; 1904 /* Get correct count/ts if racing with vblank irq */ 1905 if (new_crtc_state->active) 1906 drm_crtc_accurate_vblank_count(crtc); 1907 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1908 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 1909 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1910 1911 new_crtc_state->event = NULL; 1912 if (new_crtc_state->active) 1913 drm_crtc_vblank_put(crtc); 1914 } 1915 } 1916 1917 drm_atomic_helper_commit_hw_done(state); 1918 drm_atomic_helper_cleanup_planes(dev, state); 1919 drm_atomic_helper_commit_cleanup_done(state); 1920 drm_atomic_state_put(state); 1921 } 1922 1923 static void 1924 nv50_disp_atomic_commit_work(struct work_struct *work) 1925 { 1926 struct drm_atomic_state *state = 1927 container_of(work, typeof(*state), commit_work); 1928 nv50_disp_atomic_commit_tail(state); 1929 } 1930 1931 static int 1932 nv50_disp_atomic_commit(struct drm_device *dev, 1933 struct drm_atomic_state *state, bool nonblock) 1934 { 1935 struct nouveau_drm *drm = nouveau_drm(dev); 1936 struct drm_plane_state *new_plane_state; 1937 struct drm_plane *plane; 1938 struct drm_crtc *crtc; 1939 bool active = false; 1940 int ret, i; 1941 1942 ret = pm_runtime_get_sync(dev->dev); 1943 if (ret < 0 && ret != -EACCES) 1944 return ret; 1945 1946 ret = drm_atomic_helper_setup_commit(state, nonblock); 1947 if (ret) 1948 goto done; 1949 1950 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 1951 1952 ret = drm_atomic_helper_prepare_planes(dev, state); 1953 if (ret) 1954 goto done; 1955 1956 if (!nonblock) { 1957 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 1958 if (ret) 1959 goto err_cleanup; 1960 } 1961 1962 ret = drm_atomic_helper_swap_state(state, true); 1963 if (ret) 1964 goto err_cleanup; 1965 1966 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1967 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1968 struct nv50_wndw *wndw = nv50_wndw(plane); 1969 1970 if (asyw->set.image) 1971 nv50_wndw_ntfy_enable(wndw, asyw); 1972 } 1973 1974 drm_atomic_state_get(state); 1975 1976 if (nonblock) 1977 queue_work(system_unbound_wq, &state->commit_work); 1978 else 1979 nv50_disp_atomic_commit_tail(state); 1980 1981 drm_for_each_crtc(crtc, dev) { 1982 if (crtc->state->active) { 1983 if (!drm->have_disp_power_ref) { 1984 drm->have_disp_power_ref = true; 1985 return 0; 1986 } 1987 active = true; 1988 break; 1989 } 1990 } 1991 1992 if (!active && drm->have_disp_power_ref) { 1993 pm_runtime_put_autosuspend(dev->dev); 1994 drm->have_disp_power_ref = false; 1995 } 1996 1997 err_cleanup: 1998 if (ret) 1999 drm_atomic_helper_cleanup_planes(dev, state); 2000 done: 2001 pm_runtime_put_autosuspend(dev->dev); 2002 return ret; 2003 } 2004 2005 static struct nv50_outp_atom * 2006 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2007 { 2008 struct nv50_outp_atom *outp; 2009 2010 list_for_each_entry(outp, &atom->outp, head) { 2011 if (outp->encoder == encoder) 2012 return outp; 2013 } 2014 2015 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2016 if (!outp) 2017 return ERR_PTR(-ENOMEM); 2018 2019 list_add(&outp->head, &atom->outp); 2020 outp->encoder = encoder; 2021 return outp; 2022 } 2023 2024 static int 2025 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2026 struct drm_connector_state *old_connector_state) 2027 { 2028 struct drm_encoder *encoder = old_connector_state->best_encoder; 2029 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2030 struct drm_crtc *crtc; 2031 struct nv50_outp_atom *outp; 2032 2033 if (!(crtc = old_connector_state->crtc)) 2034 return 0; 2035 2036 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2037 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2038 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2039 outp = nv50_disp_outp_atomic_add(atom, encoder); 2040 if (IS_ERR(outp)) 2041 return PTR_ERR(outp); 2042 2043 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2044 outp->flush_disable = true; 2045 atom->flush_disable = true; 2046 } 2047 outp->clr.ctrl = true; 2048 atom->lock_core = true; 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int 2055 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2056 struct drm_connector_state *connector_state) 2057 { 2058 struct drm_encoder *encoder = connector_state->best_encoder; 2059 struct drm_crtc_state *new_crtc_state; 2060 struct drm_crtc *crtc; 2061 struct nv50_outp_atom *outp; 2062 2063 if (!(crtc = connector_state->crtc)) 2064 return 0; 2065 2066 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2067 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2068 outp = nv50_disp_outp_atomic_add(atom, encoder); 2069 if (IS_ERR(outp)) 2070 return PTR_ERR(outp); 2071 2072 outp->set.ctrl = true; 2073 atom->lock_core = true; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static int 2080 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2081 { 2082 struct nv50_atom *atom = nv50_atom(state); 2083 struct drm_connector_state *old_connector_state, *new_connector_state; 2084 struct drm_connector *connector; 2085 struct drm_crtc_state *new_crtc_state; 2086 struct drm_crtc *crtc; 2087 int ret, i; 2088 2089 /* We need to handle colour management on a per-plane basis. */ 2090 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2091 if (new_crtc_state->color_mgmt_changed) { 2092 ret = drm_atomic_add_affected_planes(state, crtc); 2093 if (ret) 2094 return ret; 2095 } 2096 } 2097 2098 ret = drm_atomic_helper_check(dev, state); 2099 if (ret) 2100 return ret; 2101 2102 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2103 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2104 if (ret) 2105 return ret; 2106 2107 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2108 if (ret) 2109 return ret; 2110 } 2111 2112 return 0; 2113 } 2114 2115 static void 2116 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2117 { 2118 struct nv50_atom *atom = nv50_atom(state); 2119 struct nv50_outp_atom *outp, *outt; 2120 2121 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2122 list_del(&outp->head); 2123 kfree(outp); 2124 } 2125 2126 drm_atomic_state_default_clear(state); 2127 } 2128 2129 static void 2130 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2131 { 2132 struct nv50_atom *atom = nv50_atom(state); 2133 drm_atomic_state_default_release(&atom->state); 2134 kfree(atom); 2135 } 2136 2137 static struct drm_atomic_state * 2138 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2139 { 2140 struct nv50_atom *atom; 2141 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2142 drm_atomic_state_init(dev, &atom->state) < 0) { 2143 kfree(atom); 2144 return NULL; 2145 } 2146 INIT_LIST_HEAD(&atom->outp); 2147 return &atom->state; 2148 } 2149 2150 static const struct drm_mode_config_funcs 2151 nv50_disp_func = { 2152 .fb_create = nouveau_user_framebuffer_create, 2153 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2154 .atomic_check = nv50_disp_atomic_check, 2155 .atomic_commit = nv50_disp_atomic_commit, 2156 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2157 .atomic_state_clear = nv50_disp_atomic_state_clear, 2158 .atomic_state_free = nv50_disp_atomic_state_free, 2159 }; 2160 2161 /****************************************************************************** 2162 * Init 2163 *****************************************************************************/ 2164 2165 void 2166 nv50_display_fini(struct drm_device *dev) 2167 { 2168 struct nouveau_encoder *nv_encoder; 2169 struct drm_encoder *encoder; 2170 struct drm_plane *plane; 2171 2172 drm_for_each_plane(plane, dev) { 2173 struct nv50_wndw *wndw = nv50_wndw(plane); 2174 if (plane->funcs != &nv50_wndw) 2175 continue; 2176 nv50_wndw_fini(wndw); 2177 } 2178 2179 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2180 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2181 nv_encoder = nouveau_encoder(encoder); 2182 nv50_mstm_fini(nv_encoder->dp.mstm); 2183 } 2184 } 2185 } 2186 2187 int 2188 nv50_display_init(struct drm_device *dev) 2189 { 2190 struct nv50_core *core = nv50_disp(dev)->core; 2191 struct drm_encoder *encoder; 2192 struct drm_plane *plane; 2193 2194 core->func->init(core); 2195 2196 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2197 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2198 struct nouveau_encoder *nv_encoder = 2199 nouveau_encoder(encoder); 2200 nv50_mstm_init(nv_encoder->dp.mstm); 2201 } 2202 } 2203 2204 drm_for_each_plane(plane, dev) { 2205 struct nv50_wndw *wndw = nv50_wndw(plane); 2206 if (plane->funcs != &nv50_wndw) 2207 continue; 2208 nv50_wndw_init(wndw); 2209 } 2210 2211 return 0; 2212 } 2213 2214 void 2215 nv50_display_destroy(struct drm_device *dev) 2216 { 2217 struct nv50_disp *disp = nv50_disp(dev); 2218 2219 nv50_core_del(&disp->core); 2220 2221 nouveau_bo_unmap(disp->sync); 2222 if (disp->sync) 2223 nouveau_bo_unpin(disp->sync); 2224 nouveau_bo_ref(NULL, &disp->sync); 2225 2226 nouveau_display(dev)->priv = NULL; 2227 kfree(disp); 2228 } 2229 2230 int 2231 nv50_display_create(struct drm_device *dev) 2232 { 2233 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2234 struct nouveau_drm *drm = nouveau_drm(dev); 2235 struct dcb_table *dcb = &drm->vbios.dcb; 2236 struct drm_connector *connector, *tmp; 2237 struct nv50_disp *disp; 2238 struct dcb_output *dcbe; 2239 int crtcs, ret, i; 2240 2241 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2242 if (!disp) 2243 return -ENOMEM; 2244 2245 mutex_init(&disp->mutex); 2246 2247 nouveau_display(dev)->priv = disp; 2248 nouveau_display(dev)->dtor = nv50_display_destroy; 2249 nouveau_display(dev)->init = nv50_display_init; 2250 nouveau_display(dev)->fini = nv50_display_fini; 2251 disp->disp = &nouveau_display(dev)->disp; 2252 dev->mode_config.funcs = &nv50_disp_func; 2253 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2254 2255 /* small shared memory area we use for notifiers and semaphores */ 2256 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2257 0, 0x0000, NULL, NULL, &disp->sync); 2258 if (!ret) { 2259 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2260 if (!ret) { 2261 ret = nouveau_bo_map(disp->sync); 2262 if (ret) 2263 nouveau_bo_unpin(disp->sync); 2264 } 2265 if (ret) 2266 nouveau_bo_ref(NULL, &disp->sync); 2267 } 2268 2269 if (ret) 2270 goto out; 2271 2272 /* allocate master evo channel */ 2273 ret = nv50_core_new(drm, &disp->core); 2274 if (ret) 2275 goto out; 2276 2277 /* create crtc objects to represent the hw heads */ 2278 if (disp->disp->object.oclass >= GV100_DISP) 2279 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2280 else 2281 if (disp->disp->object.oclass >= GF110_DISP) 2282 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2283 else 2284 crtcs = 0x3; 2285 2286 for (i = 0; i < fls(crtcs); i++) { 2287 if (!(crtcs & (1 << i))) 2288 continue; 2289 ret = nv50_head_create(dev, i); 2290 if (ret) 2291 goto out; 2292 } 2293 2294 /* create encoder/connector objects based on VBIOS DCB table */ 2295 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2296 connector = nouveau_connector_create(dev, dcbe->connector); 2297 if (IS_ERR(connector)) 2298 continue; 2299 2300 if (dcbe->location == DCB_LOC_ON_CHIP) { 2301 switch (dcbe->type) { 2302 case DCB_OUTPUT_TMDS: 2303 case DCB_OUTPUT_LVDS: 2304 case DCB_OUTPUT_DP: 2305 ret = nv50_sor_create(connector, dcbe); 2306 break; 2307 case DCB_OUTPUT_ANALOG: 2308 ret = nv50_dac_create(connector, dcbe); 2309 break; 2310 default: 2311 ret = -ENODEV; 2312 break; 2313 } 2314 } else { 2315 ret = nv50_pior_create(connector, dcbe); 2316 } 2317 2318 if (ret) { 2319 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2320 dcbe->location, dcbe->type, 2321 ffs(dcbe->or) - 1, ret); 2322 ret = 0; 2323 } 2324 } 2325 2326 /* cull any connectors we created that don't have an encoder */ 2327 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2328 if (connector->encoder_ids[0]) 2329 continue; 2330 2331 NV_WARN(drm, "%s has no encoders, removing\n", 2332 connector->name); 2333 connector->funcs->destroy(connector); 2334 } 2335 2336 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2337 dev->vblank_disable_immediate = true; 2338 2339 out: 2340 if (ret) 2341 nv50_display_destroy(dev); 2342 return ret; 2343 } 2344