1 // SPDX-License-Identifier: MIT 2 #include <linux/string.h> 3 #include <drm/drm_crtc.h> 4 #include <drm/drm_atomic_helper.h> 5 #include <drm/drm_vblank.h> 6 #include <drm/drm_vblank_work.h> 7 8 #include <nvif/class.h> 9 #include <nvif/cl0002.h> 10 #include <nvif/timer.h> 11 12 #include <nvhw/class/cl907d.h> 13 14 #include "nouveau_drv.h" 15 #include "core.h" 16 #include "head.h" 17 #include "wndw.h" 18 #include "handles.h" 19 #include "crc.h" 20 21 static const char * const nv50_crc_sources[] = { 22 [NV50_CRC_SOURCE_NONE] = "none", 23 [NV50_CRC_SOURCE_AUTO] = "auto", 24 [NV50_CRC_SOURCE_RG] = "rg", 25 [NV50_CRC_SOURCE_OUTP_ACTIVE] = "outp-active", 26 [NV50_CRC_SOURCE_OUTP_COMPLETE] = "outp-complete", 27 [NV50_CRC_SOURCE_OUTP_INACTIVE] = "outp-inactive", 28 }; 29 30 static int nv50_crc_parse_source(const char *buf, enum nv50_crc_source *s) 31 { 32 int i; 33 34 if (!buf) { 35 *s = NV50_CRC_SOURCE_NONE; 36 return 0; 37 } 38 39 i = match_string(nv50_crc_sources, ARRAY_SIZE(nv50_crc_sources), buf); 40 if (i < 0) 41 return i; 42 43 *s = i; 44 return 0; 45 } 46 47 int 48 nv50_crc_verify_source(struct drm_crtc *crtc, const char *source_name, 49 size_t *values_cnt) 50 { 51 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 52 enum nv50_crc_source source; 53 54 if (nv50_crc_parse_source(source_name, &source) < 0) { 55 NV_DEBUG(drm, "unknown source %s\n", source_name); 56 return -EINVAL; 57 } 58 59 *values_cnt = 1; 60 return 0; 61 } 62 63 const char *const *nv50_crc_get_sources(struct drm_crtc *crtc, size_t *count) 64 { 65 *count = ARRAY_SIZE(nv50_crc_sources); 66 return nv50_crc_sources; 67 } 68 69 static void 70 nv50_crc_program_ctx(struct nv50_head *head, 71 struct nv50_crc_notifier_ctx *ctx) 72 { 73 struct nv50_disp *disp = nv50_disp(head->base.base.dev); 74 struct nv50_core *core = disp->core; 75 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = { 0 }; 76 77 core->func->crc->set_ctx(head, ctx); 78 core->func->update(core, interlock, false); 79 } 80 81 static void nv50_crc_ctx_flip_work(struct kthread_work *base) 82 { 83 struct drm_vblank_work *work = to_drm_vblank_work(base); 84 struct nv50_crc *crc = container_of(work, struct nv50_crc, flip_work); 85 struct nv50_head *head = container_of(crc, struct nv50_head, crc); 86 struct drm_crtc *crtc = &head->base.base; 87 struct drm_device *dev = crtc->dev; 88 struct nv50_disp *disp = nv50_disp(dev); 89 const uint64_t start_vbl = drm_crtc_vblank_count(crtc); 90 uint64_t end_vbl; 91 u8 new_idx = crc->ctx_idx ^ 1; 92 93 /* 94 * We don't want to accidentally wait for longer then the vblank, so 95 * try again for the next vblank if we don't grab the lock 96 */ 97 if (!mutex_trylock(&disp->mutex)) { 98 drm_dbg_kms(dev, "Lock contended, delaying CRC ctx flip for %s\n", crtc->name); 99 drm_vblank_work_schedule(work, start_vbl + 1, true); 100 return; 101 } 102 103 drm_dbg_kms(dev, "Flipping notifier ctx for %s (%d -> %d)\n", 104 crtc->name, crc->ctx_idx, new_idx); 105 106 nv50_crc_program_ctx(head, NULL); 107 nv50_crc_program_ctx(head, &crc->ctx[new_idx]); 108 mutex_unlock(&disp->mutex); 109 110 end_vbl = drm_crtc_vblank_count(crtc); 111 if (unlikely(end_vbl != start_vbl)) 112 NV_ERROR(nouveau_drm(dev), 113 "Failed to flip CRC context on %s on time (%llu > %llu)\n", 114 crtc->name, end_vbl, start_vbl); 115 116 spin_lock_irq(&crc->lock); 117 crc->ctx_changed = true; 118 spin_unlock_irq(&crc->lock); 119 } 120 121 static inline void nv50_crc_reset_ctx(struct nv50_crc_notifier_ctx *ctx) 122 { 123 memset_io(ctx->mem.object.map.ptr, 0, ctx->mem.object.map.size); 124 } 125 126 static void 127 nv50_crc_get_entries(struct nv50_head *head, 128 const struct nv50_crc_func *func, 129 enum nv50_crc_source source) 130 { 131 struct drm_crtc *crtc = &head->base.base; 132 struct nv50_crc *crc = &head->crc; 133 u32 output_crc; 134 135 while (crc->entry_idx < func->num_entries) { 136 /* 137 * While Nvidia's documentation says CRCs are written on each 138 * subsequent vblank after being enabled, in practice they 139 * aren't written immediately. 140 */ 141 output_crc = func->get_entry(head, &crc->ctx[crc->ctx_idx], 142 source, crc->entry_idx); 143 if (!output_crc) 144 return; 145 146 drm_crtc_add_crc_entry(crtc, true, crc->frame, &output_crc); 147 crc->frame++; 148 crc->entry_idx++; 149 } 150 } 151 152 void nv50_crc_handle_vblank(struct nv50_head *head) 153 { 154 struct drm_crtc *crtc = &head->base.base; 155 struct nv50_crc *crc = &head->crc; 156 const struct nv50_crc_func *func = 157 nv50_disp(head->base.base.dev)->core->func->crc; 158 struct nv50_crc_notifier_ctx *ctx; 159 bool need_reschedule = false; 160 161 if (!func) 162 return; 163 164 /* 165 * We don't lose events if we aren't able to report CRCs until the 166 * next vblank, so only report CRCs if the locks we need aren't 167 * contended to prevent missing an actual vblank event 168 */ 169 if (!spin_trylock(&crc->lock)) 170 return; 171 172 if (!crc->src) 173 goto out; 174 175 ctx = &crc->ctx[crc->ctx_idx]; 176 if (crc->ctx_changed && func->ctx_finished(head, ctx)) { 177 nv50_crc_get_entries(head, func, crc->src); 178 179 crc->ctx_idx ^= 1; 180 crc->entry_idx = 0; 181 crc->ctx_changed = false; 182 183 /* 184 * Unfortunately when notifier contexts are changed during CRC 185 * capture, we will inevitably lose the CRC entry for the 186 * frame where the hardware actually latched onto the first 187 * UPDATE. According to Nvidia's hardware engineers, there's 188 * no workaround for this. 189 * 190 * Now, we could try to be smart here and calculate the number 191 * of missed CRCs based on audit timestamps, but those were 192 * removed starting with volta. Since we always flush our 193 * updates back-to-back without waiting, we'll just be 194 * optimistic and assume we always miss exactly one frame. 195 */ 196 drm_dbg_kms(head->base.base.dev, 197 "Notifier ctx flip for head-%d finished, lost CRC for frame %llu\n", 198 head->base.index, crc->frame); 199 crc->frame++; 200 201 nv50_crc_reset_ctx(ctx); 202 need_reschedule = true; 203 } 204 205 nv50_crc_get_entries(head, func, crc->src); 206 207 if (need_reschedule) 208 drm_vblank_work_schedule(&crc->flip_work, 209 drm_crtc_vblank_count(crtc) 210 + crc->flip_threshold 211 - crc->entry_idx, 212 true); 213 214 out: 215 spin_unlock(&crc->lock); 216 } 217 218 static void nv50_crc_wait_ctx_finished(struct nv50_head *head, 219 const struct nv50_crc_func *func, 220 struct nv50_crc_notifier_ctx *ctx) 221 { 222 struct drm_device *dev = head->base.base.dev; 223 struct nouveau_drm *drm = nouveau_drm(dev); 224 s64 ret; 225 226 ret = nvif_msec(&drm->client.device, 50, 227 if (func->ctx_finished(head, ctx)) break;); 228 if (ret == -ETIMEDOUT) 229 NV_ERROR(drm, 230 "CRC notifier ctx for head %d not finished after 50ms\n", 231 head->base.index); 232 else if (ret) 233 NV_ATOMIC(drm, 234 "CRC notifier ctx for head-%d finished after %lldns\n", 235 head->base.index, ret); 236 } 237 238 void nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) 239 { 240 struct drm_crtc_state *crtc_state; 241 struct drm_crtc *crtc; 242 int i; 243 244 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 245 struct nv50_head *head = nv50_head(crtc); 246 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 247 struct nv50_crc *crc = &head->crc; 248 249 if (!asyh->clr.crc) 250 continue; 251 252 spin_lock_irq(&crc->lock); 253 crc->src = NV50_CRC_SOURCE_NONE; 254 spin_unlock_irq(&crc->lock); 255 256 drm_crtc_vblank_put(crtc); 257 drm_vblank_work_cancel_sync(&crc->flip_work); 258 259 NV_ATOMIC(nouveau_drm(crtc->dev), 260 "CRC reporting on vblank for head-%d disabled\n", 261 head->base.index); 262 263 /* CRC generation is still enabled in hw, we'll just report 264 * any remaining CRC entries ourselves after it gets disabled 265 * in hardware 266 */ 267 } 268 } 269 270 void nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) 271 { 272 struct drm_crtc_state *new_crtc_state; 273 struct drm_crtc *crtc; 274 int i; 275 276 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 277 struct nv50_head *head = nv50_head(crtc); 278 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 279 struct nv50_crc *crc = &head->crc; 280 int i; 281 282 if (!asyh->set.crc) 283 continue; 284 285 crc->entry_idx = 0; 286 crc->ctx_changed = false; 287 for (i = 0; i < ARRAY_SIZE(crc->ctx); i++) 288 nv50_crc_reset_ctx(&crc->ctx[i]); 289 } 290 } 291 292 void nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) 293 { 294 const struct nv50_crc_func *func = 295 nv50_disp(state->dev)->core->func->crc; 296 struct drm_crtc_state *new_crtc_state; 297 struct drm_crtc *crtc; 298 int i; 299 300 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 301 struct nv50_head *head = nv50_head(crtc); 302 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 303 struct nv50_crc *crc = &head->crc; 304 struct nv50_crc_notifier_ctx *ctx = &crc->ctx[crc->ctx_idx]; 305 306 if (!asyh->clr.crc) 307 continue; 308 309 if (crc->ctx_changed) { 310 nv50_crc_wait_ctx_finished(head, func, ctx); 311 ctx = &crc->ctx[crc->ctx_idx ^ 1]; 312 } 313 nv50_crc_wait_ctx_finished(head, func, ctx); 314 } 315 } 316 317 void nv50_crc_atomic_start_reporting(struct drm_atomic_state *state) 318 { 319 struct drm_crtc_state *crtc_state; 320 struct drm_crtc *crtc; 321 int i; 322 323 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 324 struct nv50_head *head = nv50_head(crtc); 325 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 326 struct nv50_crc *crc = &head->crc; 327 u64 vbl_count; 328 329 if (!asyh->set.crc) 330 continue; 331 332 drm_crtc_vblank_get(crtc); 333 334 spin_lock_irq(&crc->lock); 335 vbl_count = drm_crtc_vblank_count(crtc); 336 crc->frame = vbl_count; 337 crc->src = asyh->crc.src; 338 drm_vblank_work_schedule(&crc->flip_work, 339 vbl_count + crc->flip_threshold, 340 true); 341 spin_unlock_irq(&crc->lock); 342 343 NV_ATOMIC(nouveau_drm(crtc->dev), 344 "CRC reporting on vblank for head-%d enabled\n", 345 head->base.index); 346 } 347 } 348 349 int nv50_crc_atomic_check_head(struct nv50_head *head, 350 struct nv50_head_atom *asyh, 351 struct nv50_head_atom *armh) 352 { 353 struct nv50_atom *atom = nv50_atom(asyh->state.state); 354 bool changed = armh->crc.src != asyh->crc.src; 355 356 if (!armh->crc.src && !asyh->crc.src) { 357 asyh->set.crc = false; 358 asyh->clr.crc = false; 359 return 0; 360 } 361 362 if (drm_atomic_crtc_needs_modeset(&asyh->state) || changed) { 363 asyh->clr.crc = armh->crc.src && armh->state.active; 364 asyh->set.crc = asyh->crc.src && asyh->state.active; 365 if (changed) 366 asyh->set.or |= armh->or.crc_raster != 367 asyh->or.crc_raster; 368 369 if (asyh->clr.crc && asyh->set.crc) 370 atom->flush_disable = true; 371 } else { 372 asyh->set.crc = false; 373 asyh->clr.crc = false; 374 } 375 376 return 0; 377 } 378 379 void nv50_crc_atomic_check_outp(struct nv50_atom *atom) 380 { 381 struct drm_crtc *crtc; 382 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 383 int i; 384 385 if (atom->flush_disable) 386 return; 387 388 for_each_oldnew_crtc_in_state(&atom->state, crtc, old_crtc_state, 389 new_crtc_state, i) { 390 struct nv50_head_atom *armh = nv50_head_atom(old_crtc_state); 391 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 392 struct nv50_outp_atom *outp_atom; 393 struct nouveau_encoder *outp = 394 nv50_real_outp(nv50_head_atom_get_encoder(armh)); 395 struct drm_encoder *encoder = &outp->base.base; 396 397 if (!asyh->clr.crc) 398 continue; 399 400 /* 401 * Re-programming ORs can't be done in the same flush as 402 * disabling CRCs 403 */ 404 list_for_each_entry(outp_atom, &atom->outp, head) { 405 if (outp_atom->encoder == encoder) { 406 if (outp_atom->set.mask) { 407 atom->flush_disable = true; 408 return; 409 } else { 410 break; 411 } 412 } 413 } 414 } 415 } 416 417 static enum nv50_crc_source_type 418 nv50_crc_source_type(struct nouveau_encoder *outp, 419 enum nv50_crc_source source) 420 { 421 struct dcb_output *dcbe = outp->dcb; 422 423 switch (source) { 424 case NV50_CRC_SOURCE_NONE: return NV50_CRC_SOURCE_TYPE_NONE; 425 case NV50_CRC_SOURCE_RG: return NV50_CRC_SOURCE_TYPE_RG; 426 default: break; 427 } 428 429 if (dcbe->location != DCB_LOC_ON_CHIP) 430 return NV50_CRC_SOURCE_TYPE_PIOR; 431 432 switch (dcbe->type) { 433 case DCB_OUTPUT_DP: return NV50_CRC_SOURCE_TYPE_SF; 434 case DCB_OUTPUT_ANALOG: return NV50_CRC_SOURCE_TYPE_DAC; 435 default: return NV50_CRC_SOURCE_TYPE_SOR; 436 } 437 } 438 439 void nv50_crc_atomic_set(struct nv50_head *head, 440 struct nv50_head_atom *asyh) 441 { 442 struct drm_crtc *crtc = &head->base.base; 443 struct drm_device *dev = crtc->dev; 444 struct nv50_crc *crc = &head->crc; 445 const struct nv50_crc_func *func = nv50_disp(dev)->core->func->crc; 446 struct nouveau_encoder *outp = 447 nv50_real_outp(nv50_head_atom_get_encoder(asyh)); 448 449 func->set_src(head, outp->or, nv50_crc_source_type(outp, asyh->crc.src), 450 &crc->ctx[crc->ctx_idx]); 451 } 452 453 void nv50_crc_atomic_clr(struct nv50_head *head) 454 { 455 const struct nv50_crc_func *func = 456 nv50_disp(head->base.base.dev)->core->func->crc; 457 458 func->set_src(head, 0, NV50_CRC_SOURCE_TYPE_NONE, NULL); 459 } 460 461 static inline int 462 nv50_crc_raster_type(enum nv50_crc_source source) 463 { 464 switch (source) { 465 case NV50_CRC_SOURCE_NONE: 466 case NV50_CRC_SOURCE_AUTO: 467 case NV50_CRC_SOURCE_RG: 468 case NV50_CRC_SOURCE_OUTP_ACTIVE: 469 return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER; 470 case NV50_CRC_SOURCE_OUTP_COMPLETE: 471 return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER; 472 case NV50_CRC_SOURCE_OUTP_INACTIVE: 473 return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER; 474 } 475 476 return 0; 477 } 478 479 /* We handle mapping the memory for CRC notifiers ourselves, since each 480 * notifier needs it's own handle 481 */ 482 static inline int 483 nv50_crc_ctx_init(struct nv50_head *head, struct nvif_mmu *mmu, 484 struct nv50_crc_notifier_ctx *ctx, size_t len, int idx) 485 { 486 struct nv50_core *core = nv50_disp(head->base.base.dev)->core; 487 int ret; 488 489 ret = nvif_mem_ctor_map(mmu, "kmsCrcNtfy", NVIF_MEM_VRAM, len, &ctx->mem); 490 if (ret) 491 return ret; 492 493 ret = nvif_object_ctor(&core->chan.base.user, "kmsCrcNtfyCtxDma", 494 NV50_DISP_HANDLE_CRC_CTX(head, idx), 495 NV_DMA_IN_MEMORY, 496 &(struct nv_dma_v0) { 497 .target = NV_DMA_V0_TARGET_VRAM, 498 .access = NV_DMA_V0_ACCESS_RDWR, 499 .start = ctx->mem.addr, 500 .limit = ctx->mem.addr 501 + ctx->mem.size - 1, 502 }, sizeof(struct nv_dma_v0), 503 &ctx->ntfy); 504 if (ret) 505 goto fail_fini; 506 507 return 0; 508 509 fail_fini: 510 nvif_mem_dtor(&ctx->mem); 511 return ret; 512 } 513 514 static inline void 515 nv50_crc_ctx_fini(struct nv50_crc_notifier_ctx *ctx) 516 { 517 nvif_object_dtor(&ctx->ntfy); 518 nvif_mem_dtor(&ctx->mem); 519 } 520 521 int nv50_crc_set_source(struct drm_crtc *crtc, const char *source_str) 522 { 523 struct drm_device *dev = crtc->dev; 524 struct drm_atomic_state *state; 525 struct drm_modeset_acquire_ctx ctx; 526 struct nv50_head *head = nv50_head(crtc); 527 struct nv50_crc *crc = &head->crc; 528 const struct nv50_crc_func *func = nv50_disp(dev)->core->func->crc; 529 struct nvif_mmu *mmu = &nouveau_drm(dev)->client.mmu; 530 struct nv50_head_atom *asyh; 531 struct drm_crtc_state *crtc_state; 532 enum nv50_crc_source source; 533 int ret = 0, ctx_flags = 0, i; 534 535 ret = nv50_crc_parse_source(source_str, &source); 536 if (ret) 537 return ret; 538 539 /* 540 * Since we don't want the user to accidentally interrupt us as we're 541 * disabling CRCs 542 */ 543 if (source) 544 ctx_flags |= DRM_MODESET_ACQUIRE_INTERRUPTIBLE; 545 drm_modeset_acquire_init(&ctx, ctx_flags); 546 547 state = drm_atomic_state_alloc(dev); 548 if (!state) { 549 ret = -ENOMEM; 550 goto out_acquire_fini; 551 } 552 state->acquire_ctx = &ctx; 553 554 if (source) { 555 for (i = 0; i < ARRAY_SIZE(head->crc.ctx); i++) { 556 ret = nv50_crc_ctx_init(head, mmu, &crc->ctx[i], 557 func->notifier_len, i); 558 if (ret) 559 goto out_ctx_fini; 560 } 561 } 562 563 retry: 564 crtc_state = drm_atomic_get_crtc_state(state, &head->base.base); 565 if (IS_ERR(crtc_state)) { 566 ret = PTR_ERR(crtc_state); 567 if (ret == -EDEADLK) 568 goto deadlock; 569 else if (ret) 570 goto out_drop_locks; 571 } 572 asyh = nv50_head_atom(crtc_state); 573 asyh->crc.src = source; 574 asyh->or.crc_raster = nv50_crc_raster_type(source); 575 576 ret = drm_atomic_commit(state); 577 if (ret == -EDEADLK) 578 goto deadlock; 579 else if (ret) 580 goto out_drop_locks; 581 582 if (!source) { 583 /* 584 * If the user specified a custom flip threshold through 585 * debugfs, reset it 586 */ 587 crc->flip_threshold = func->flip_threshold; 588 } 589 590 out_drop_locks: 591 drm_modeset_drop_locks(&ctx); 592 out_ctx_fini: 593 if (!source || ret) { 594 for (i = 0; i < ARRAY_SIZE(crc->ctx); i++) 595 nv50_crc_ctx_fini(&crc->ctx[i]); 596 } 597 drm_atomic_state_put(state); 598 out_acquire_fini: 599 drm_modeset_acquire_fini(&ctx); 600 return ret; 601 602 deadlock: 603 drm_atomic_state_clear(state); 604 drm_modeset_backoff(&ctx); 605 goto retry; 606 } 607 608 static int 609 nv50_crc_debugfs_flip_threshold_get(struct seq_file *m, void *data) 610 { 611 struct nv50_head *head = m->private; 612 struct drm_crtc *crtc = &head->base.base; 613 struct nv50_crc *crc = &head->crc; 614 int ret; 615 616 ret = drm_modeset_lock_single_interruptible(&crtc->mutex); 617 if (ret) 618 return ret; 619 620 seq_printf(m, "%d\n", crc->flip_threshold); 621 622 drm_modeset_unlock(&crtc->mutex); 623 return ret; 624 } 625 626 static int 627 nv50_crc_debugfs_flip_threshold_open(struct inode *inode, struct file *file) 628 { 629 return single_open(file, nv50_crc_debugfs_flip_threshold_get, 630 inode->i_private); 631 } 632 633 static ssize_t 634 nv50_crc_debugfs_flip_threshold_set(struct file *file, 635 const char __user *ubuf, size_t len, 636 loff_t *offp) 637 { 638 struct seq_file *m = file->private_data; 639 struct nv50_head *head = m->private; 640 struct nv50_head_atom *armh; 641 struct drm_crtc *crtc = &head->base.base; 642 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 643 struct nv50_crc *crc = &head->crc; 644 const struct nv50_crc_func *func = 645 nv50_disp(crtc->dev)->core->func->crc; 646 int value, ret; 647 648 ret = kstrtoint_from_user(ubuf, len, 10, &value); 649 if (ret) 650 return ret; 651 652 if (value > func->flip_threshold) 653 return -EINVAL; 654 else if (value == -1) 655 value = func->flip_threshold; 656 else if (value < -1) 657 return -EINVAL; 658 659 ret = drm_modeset_lock_single_interruptible(&crtc->mutex); 660 if (ret) 661 return ret; 662 663 armh = nv50_head_atom(crtc->state); 664 if (armh->crc.src) { 665 ret = -EBUSY; 666 goto out; 667 } 668 669 NV_DEBUG(drm, 670 "Changing CRC flip threshold for next capture on head-%d to %d\n", 671 head->base.index, value); 672 crc->flip_threshold = value; 673 ret = len; 674 675 out: 676 drm_modeset_unlock(&crtc->mutex); 677 return ret; 678 } 679 680 static const struct file_operations nv50_crc_flip_threshold_fops = { 681 .owner = THIS_MODULE, 682 .open = nv50_crc_debugfs_flip_threshold_open, 683 .read = seq_read, 684 .write = nv50_crc_debugfs_flip_threshold_set, 685 .release = single_release, 686 }; 687 688 int nv50_head_crc_late_register(struct nv50_head *head) 689 { 690 struct drm_crtc *crtc = &head->base.base; 691 const struct nv50_crc_func *func = 692 nv50_disp(crtc->dev)->core->func->crc; 693 struct dentry *root; 694 695 if (!func || !crtc->debugfs_entry) 696 return 0; 697 698 root = debugfs_create_dir("nv_crc", crtc->debugfs_entry); 699 debugfs_create_file("flip_threshold", 0644, root, head, 700 &nv50_crc_flip_threshold_fops); 701 702 return 0; 703 } 704 705 static inline void 706 nv50_crc_init_head(struct nv50_disp *disp, const struct nv50_crc_func *func, 707 struct nv50_head *head) 708 { 709 struct nv50_crc *crc = &head->crc; 710 711 crc->flip_threshold = func->flip_threshold; 712 spin_lock_init(&crc->lock); 713 drm_vblank_work_init(&crc->flip_work, &head->base.base, 714 nv50_crc_ctx_flip_work); 715 } 716 717 void nv50_crc_init(struct drm_device *dev) 718 { 719 struct nv50_disp *disp = nv50_disp(dev); 720 struct drm_crtc *crtc; 721 const struct nv50_crc_func *func = disp->core->func->crc; 722 723 if (!func) 724 return; 725 726 drm_for_each_crtc(crtc, dev) 727 nv50_crc_init_head(disp, func, nv50_head(crtc)); 728 } 729