1 /*
2  * Copyright 2018 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "core.h"
23 
24 #include <nvif/class.h>
25 
26 void
27 nv50_core_del(struct nv50_core **pcore)
28 {
29 	struct nv50_core *core = *pcore;
30 	if (core) {
31 		nv50_dmac_destroy(&core->chan);
32 		kfree(*pcore);
33 		*pcore = NULL;
34 	}
35 }
36 
37 int
38 nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
39 {
40 	struct {
41 		s32 oclass;
42 		int version;
43 		int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
44 	} cores[] = {
45 		{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
46 		{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
47 		{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
48 		{ GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
49 		{ GM200_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
50 		{ GM107_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
51 		{ GK110_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
52 		{ GK104_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
53 		{ GF110_DISP_CORE_CHANNEL_DMA, 0, core907d_new },
54 		{ GT214_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
55 		{ GT206_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
56 		{ GT200_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
57 		{   G82_DISP_CORE_CHANNEL_DMA, 0, core827d_new },
58 		{  NV50_DISP_CORE_CHANNEL_DMA, 0, core507d_new },
59 		{}
60 	};
61 	struct nv50_disp *disp = nv50_disp(drm->dev);
62 	int cid;
63 
64 	cid = nvif_mclass(&disp->disp->object, cores);
65 	if (cid < 0) {
66 		NV_ERROR(drm, "No supported core channel class\n");
67 		return cid;
68 	}
69 
70 	return cores[cid].new(drm, cores[cid].oclass, pcore);
71 }
72