1 /* 2 * Copyright (C) 2009 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #include <drm/drmP.h> 28 #include <drm/drm_crtc_helper.h> 29 #include "nouveau_drm.h" 30 #include "nouveau_reg.h" 31 #include "nouveau_encoder.h" 32 #include "nouveau_connector.h" 33 #include "nouveau_crtc.h" 34 #include "hw.h" 35 #include "tvnv17.h" 36 37 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" 38 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" 39 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" 40 "\t\tDefault: PAL\n" 41 "\t\t*NOTE* Ignored for cards with external TV encoders."); 42 static char *nouveau_tv_norm; 43 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400); 44 45 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) 46 { 47 struct drm_device *dev = encoder->dev; 48 struct nouveau_drm *drm = nouveau_drm(dev); 49 struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); 50 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); 51 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, 52 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; 53 uint32_t sample = 0; 54 int head; 55 56 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 57 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); 58 if (drm->vbios.tvdactestval) 59 testval = drm->vbios.tvdactestval; 60 61 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); 62 head = (dacclk & 0x100) >> 8; 63 64 /* Save the previous state. */ 65 gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff); 66 gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff); 67 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); 68 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); 69 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); 70 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 71 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); 72 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c); 73 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14); 74 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); 75 76 /* Prepare the DAC for load detection. */ 77 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true); 78 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true); 79 80 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); 81 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); 82 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183); 83 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, 84 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | 85 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 | 86 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | 87 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | 88 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS); 89 90 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0); 91 92 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, 93 (dacclk & ~0xff) | 0x22); 94 msleep(1); 95 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, 96 (dacclk & ~0xff) | 0x21); 97 98 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20); 99 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16); 100 101 /* Sample pin 0x4 (usually S-video luma). */ 102 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff); 103 msleep(20); 104 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) 105 & 0x4 << 28; 106 107 /* Sample the remaining pins. */ 108 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff); 109 msleep(20); 110 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) 111 & 0xa << 28; 112 113 /* Restore the previous state. */ 114 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c); 115 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14); 116 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c); 117 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk); 118 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl); 119 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control); 120 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); 121 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); 122 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); 123 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1); 124 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0); 125 126 return sample; 127 } 128 129 static bool 130 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) 131 { 132 struct nouveau_drm *drm = nouveau_drm(dev); 133 struct nvif_device *device = &drm->device; 134 135 /* Zotac FX5200 */ 136 if (nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x1035) || 137 nv_device_match(nvxx_object(device), 0x0322, 0x19da, 0x2035)) { 138 *pin_mask = 0xc; 139 return false; 140 } 141 142 /* MSI nForce2 IGP */ 143 if (nv_device_match(nvxx_object(device), 0x01f0, 0x1462, 0x5710)) { 144 *pin_mask = 0xc; 145 return false; 146 } 147 148 return true; 149 } 150 151 static enum drm_connector_status 152 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) 153 { 154 struct drm_device *dev = encoder->dev; 155 struct nouveau_drm *drm = nouveau_drm(dev); 156 struct drm_mode_config *conf = &dev->mode_config; 157 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 158 struct dcb_output *dcb = tv_enc->base.dcb; 159 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); 160 161 if (nv04_dac_in_use(encoder)) 162 return connector_status_disconnected; 163 164 if (reliable) { 165 if (drm->device.info.chipset == 0x42 || 166 drm->device.info.chipset == 0x43) 167 tv_enc->pin_mask = 168 nv42_tv_sample_load(encoder) >> 28 & 0xe; 169 else 170 tv_enc->pin_mask = 171 nv17_dac_sample_load(encoder) >> 28 & 0xe; 172 } 173 174 switch (tv_enc->pin_mask) { 175 case 0x2: 176 case 0x4: 177 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite; 178 break; 179 case 0xc: 180 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; 181 break; 182 case 0xe: 183 if (dcb->tvconf.has_component_output) 184 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; 185 else 186 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; 187 break; 188 default: 189 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 190 break; 191 } 192 193 drm_object_property_set_value(&connector->base, 194 conf->tv_subconnector_property, 195 tv_enc->subconnector); 196 197 if (!reliable) { 198 return connector_status_unknown; 199 } else if (tv_enc->subconnector) { 200 NV_INFO(drm, "Load detected on output %c\n", 201 '@' + ffs(dcb->or)); 202 return connector_status_connected; 203 } else { 204 return connector_status_disconnected; 205 } 206 } 207 208 static int nv17_tv_get_ld_modes(struct drm_encoder *encoder, 209 struct drm_connector *connector) 210 { 211 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 212 const struct drm_display_mode *tv_mode; 213 int n = 0; 214 215 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { 216 struct drm_display_mode *mode; 217 218 mode = drm_mode_duplicate(encoder->dev, tv_mode); 219 220 mode->clock = tv_norm->tv_enc_mode.vrefresh * 221 mode->htotal / 1000 * 222 mode->vtotal / 1000; 223 224 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 225 mode->clock *= 2; 226 227 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && 228 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay) 229 mode->type |= DRM_MODE_TYPE_PREFERRED; 230 231 drm_mode_probed_add(connector, mode); 232 n++; 233 } 234 235 return n; 236 } 237 238 static int nv17_tv_get_hd_modes(struct drm_encoder *encoder, 239 struct drm_connector *connector) 240 { 241 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 242 struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode; 243 struct drm_display_mode *mode; 244 const struct { 245 int hdisplay; 246 int vdisplay; 247 } modes[] = { 248 { 640, 400 }, 249 { 640, 480 }, 250 { 720, 480 }, 251 { 720, 576 }, 252 { 800, 600 }, 253 { 1024, 768 }, 254 { 1280, 720 }, 255 { 1280, 1024 }, 256 { 1920, 1080 } 257 }; 258 int i, n = 0; 259 260 for (i = 0; i < ARRAY_SIZE(modes); i++) { 261 if (modes[i].hdisplay > output_mode->hdisplay || 262 modes[i].vdisplay > output_mode->vdisplay) 263 continue; 264 265 if (modes[i].hdisplay == output_mode->hdisplay && 266 modes[i].vdisplay == output_mode->vdisplay) { 267 mode = drm_mode_duplicate(encoder->dev, output_mode); 268 mode->type |= DRM_MODE_TYPE_PREFERRED; 269 270 } else { 271 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, 272 modes[i].vdisplay, 60, false, 273 (output_mode->flags & 274 DRM_MODE_FLAG_INTERLACE), false); 275 } 276 277 /* CVT modes are sometimes unsuitable... */ 278 if (output_mode->hdisplay <= 720 279 || output_mode->hdisplay >= 1920) { 280 mode->htotal = output_mode->htotal; 281 mode->hsync_start = (mode->hdisplay + (mode->htotal 282 - mode->hdisplay) * 9 / 10) & ~7; 283 mode->hsync_end = mode->hsync_start + 8; 284 } 285 286 if (output_mode->vdisplay >= 1024) { 287 mode->vtotal = output_mode->vtotal; 288 mode->vsync_start = output_mode->vsync_start; 289 mode->vsync_end = output_mode->vsync_end; 290 } 291 292 mode->type |= DRM_MODE_TYPE_DRIVER; 293 drm_mode_probed_add(connector, mode); 294 n++; 295 } 296 297 return n; 298 } 299 300 static int nv17_tv_get_modes(struct drm_encoder *encoder, 301 struct drm_connector *connector) 302 { 303 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 304 305 if (tv_norm->kind == CTV_ENC_MODE) 306 return nv17_tv_get_hd_modes(encoder, connector); 307 else 308 return nv17_tv_get_ld_modes(encoder, connector); 309 } 310 311 static int nv17_tv_mode_valid(struct drm_encoder *encoder, 312 struct drm_display_mode *mode) 313 { 314 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 315 316 if (tv_norm->kind == CTV_ENC_MODE) { 317 struct drm_display_mode *output_mode = 318 &tv_norm->ctv_enc_mode.mode; 319 320 if (mode->clock > 400000) 321 return MODE_CLOCK_HIGH; 322 323 if (mode->hdisplay > output_mode->hdisplay || 324 mode->vdisplay > output_mode->vdisplay) 325 return MODE_BAD; 326 327 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != 328 (output_mode->flags & DRM_MODE_FLAG_INTERLACE)) 329 return MODE_NO_INTERLACE; 330 331 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 332 return MODE_NO_DBLESCAN; 333 334 } else { 335 const int vsync_tolerance = 600; 336 337 if (mode->clock > 70000) 338 return MODE_CLOCK_HIGH; 339 340 if (abs(drm_mode_vrefresh(mode) * 1000 - 341 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance) 342 return MODE_VSYNC; 343 344 /* The encoder takes care of the actual interlacing */ 345 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 346 return MODE_NO_INTERLACE; 347 } 348 349 return MODE_OK; 350 } 351 352 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, 353 const struct drm_display_mode *mode, 354 struct drm_display_mode *adjusted_mode) 355 { 356 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 357 358 if (nv04_dac_in_use(encoder)) 359 return false; 360 361 if (tv_norm->kind == CTV_ENC_MODE) 362 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock; 363 else 364 adjusted_mode->clock = 90000; 365 366 return true; 367 } 368 369 static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) 370 { 371 struct drm_device *dev = encoder->dev; 372 struct nouveau_drm *drm = nouveau_drm(dev); 373 struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); 374 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; 375 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 376 377 if (nouveau_encoder(encoder)->last_dpms == mode) 378 return; 379 nouveau_encoder(encoder)->last_dpms = mode; 380 381 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n", 382 mode, nouveau_encoder(encoder)->dcb->index); 383 384 regs->ptv_200 &= ~1; 385 386 if (tv_norm->kind == CTV_ENC_MODE) { 387 nv04_dfp_update_fp_control(encoder, mode); 388 389 } else { 390 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF); 391 392 if (mode == DRM_MODE_DPMS_ON) 393 regs->ptv_200 |= 1; 394 } 395 396 nv_load_ptv(dev, regs, 200); 397 398 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON); 399 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON); 400 401 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); 402 } 403 404 static void nv17_tv_prepare(struct drm_encoder *encoder) 405 { 406 struct drm_device *dev = encoder->dev; 407 struct nouveau_drm *drm = nouveau_drm(dev); 408 const struct drm_encoder_helper_funcs *helper = encoder->helper_private; 409 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 410 int head = nouveau_crtc(encoder->crtc)->index; 411 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ 412 NV_CIO_CRE_LCD__INDEX]; 413 uint32_t dacclk_off = NV_PRAMDAC_DACCLK + 414 nv04_dac_output_offset(encoder); 415 uint32_t dacclk; 416 417 helper->dpms(encoder, DRM_MODE_DPMS_OFF); 418 419 nv04_dfp_disable(dev, head); 420 421 /* Unbind any FP encoders from this head if we need the FP 422 * stuff enabled. */ 423 if (tv_norm->kind == CTV_ENC_MODE) { 424 struct drm_encoder *enc; 425 426 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 427 struct dcb_output *dcb = nouveau_encoder(enc)->dcb; 428 429 if ((dcb->type == DCB_OUTPUT_TMDS || 430 dcb->type == DCB_OUTPUT_LVDS) && 431 !enc->crtc && 432 nv04_dfp_get_bound_head(dev, dcb) == head) { 433 nv04_dfp_bind_head(dev, dcb, head ^ 1, 434 drm->vbios.fp.dual_link); 435 } 436 } 437 438 } 439 440 if (tv_norm->kind == CTV_ENC_MODE) 441 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8); 442 443 /* Set the DACCLK register */ 444 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; 445 446 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 447 dacclk |= 0x1a << 16; 448 449 if (tv_norm->kind == CTV_ENC_MODE) { 450 dacclk |= 0x20; 451 452 if (head) 453 dacclk |= 0x100; 454 else 455 dacclk &= ~0x100; 456 457 } else { 458 dacclk |= 0x10; 459 460 } 461 462 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk); 463 } 464 465 static void nv17_tv_mode_set(struct drm_encoder *encoder, 466 struct drm_display_mode *drm_mode, 467 struct drm_display_mode *adjusted_mode) 468 { 469 struct drm_device *dev = encoder->dev; 470 struct nouveau_drm *drm = nouveau_drm(dev); 471 int head = nouveau_crtc(encoder->crtc)->index; 472 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; 473 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state; 474 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 475 int i; 476 477 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ 478 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ 479 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */ 480 regs->tv_setup = 1; 481 regs->ramdac_8c0 = 0x0; 482 483 if (tv_norm->kind == TV_ENC_MODE) { 484 tv_regs->ptv_200 = 0x13111100; 485 if (head) 486 tv_regs->ptv_200 |= 0x10; 487 488 tv_regs->ptv_20c = 0x808010; 489 tv_regs->ptv_304 = 0x2d00000; 490 tv_regs->ptv_600 = 0x0; 491 tv_regs->ptv_60c = 0x0; 492 tv_regs->ptv_610 = 0x1e00000; 493 494 if (tv_norm->tv_enc_mode.vdisplay == 576) { 495 tv_regs->ptv_508 = 0x1200000; 496 tv_regs->ptv_614 = 0x33; 497 498 } else if (tv_norm->tv_enc_mode.vdisplay == 480) { 499 tv_regs->ptv_508 = 0xf00000; 500 tv_regs->ptv_614 = 0x13; 501 } 502 503 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) { 504 tv_regs->ptv_500 = 0xe8e0; 505 tv_regs->ptv_504 = 0x1710; 506 tv_regs->ptv_604 = 0x0; 507 tv_regs->ptv_608 = 0x0; 508 } else { 509 if (tv_norm->tv_enc_mode.vdisplay == 576) { 510 tv_regs->ptv_604 = 0x20; 511 tv_regs->ptv_608 = 0x10; 512 tv_regs->ptv_500 = 0x19710; 513 tv_regs->ptv_504 = 0x68f0; 514 515 } else if (tv_norm->tv_enc_mode.vdisplay == 480) { 516 tv_regs->ptv_604 = 0x10; 517 tv_regs->ptv_608 = 0x20; 518 tv_regs->ptv_500 = 0x4b90; 519 tv_regs->ptv_504 = 0x1b480; 520 } 521 } 522 523 for (i = 0; i < 0x40; i++) 524 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i]; 525 526 } else { 527 struct drm_display_mode *output_mode = 528 &tv_norm->ctv_enc_mode.mode; 529 530 /* The registers in PRAMDAC+0xc00 control some timings and CSC 531 * parameters for the CTV encoder (It's only used for "HD" TV 532 * modes, I don't think I have enough working to guess what 533 * they exactly mean...), it's probably connected at the 534 * output of the FP encoder, but it also needs the analog 535 * encoder in its OR enabled and routed to the head it's 536 * using. It's enabled with the DACCLK register, bits [5:4]. 537 */ 538 for (i = 0; i < 38; i++) 539 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i]; 540 541 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; 542 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; 543 regs->fp_horiz_regs[FP_SYNC_START] = 544 output_mode->hsync_start - 1; 545 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; 546 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay + 547 max((output_mode->hdisplay-600)/40 - 1, 1); 548 549 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; 550 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; 551 regs->fp_vert_regs[FP_SYNC_START] = 552 output_mode->vsync_start - 1; 553 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; 554 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; 555 556 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | 557 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | 558 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; 559 560 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) 561 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; 562 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) 563 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; 564 565 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | 566 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | 567 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | 568 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | 569 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | 570 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | 571 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; 572 573 regs->fp_debug_2 = 0; 574 575 regs->fp_margin_color = 0x801080; 576 577 } 578 } 579 580 static void nv17_tv_commit(struct drm_encoder *encoder) 581 { 582 struct drm_device *dev = encoder->dev; 583 struct nouveau_drm *drm = nouveau_drm(dev); 584 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 585 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 586 const struct drm_encoder_helper_funcs *helper = encoder->helper_private; 587 588 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) { 589 nv17_tv_update_rescaler(encoder); 590 nv17_tv_update_properties(encoder); 591 } else { 592 nv17_ctv_update_rescaler(encoder); 593 } 594 595 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); 596 597 /* This could use refinement for flatpanels, but it should work */ 598 if (drm->device.info.chipset < 0x44) 599 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 600 nv04_dac_output_offset(encoder), 601 0xf0000000); 602 else 603 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 604 nv04_dac_output_offset(encoder), 605 0x00100000); 606 607 helper->dpms(encoder, DRM_MODE_DPMS_ON); 608 609 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n", 610 nouveau_encoder_connector_get(nv_encoder)->base.name, 611 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 612 } 613 614 static void nv17_tv_save(struct drm_encoder *encoder) 615 { 616 struct drm_device *dev = encoder->dev; 617 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 618 619 nouveau_encoder(encoder)->restore.output = 620 NVReadRAMDAC(dev, 0, 621 NV_PRAMDAC_DACCLK + 622 nv04_dac_output_offset(encoder)); 623 624 nv17_tv_state_save(dev, &tv_enc->saved_state); 625 626 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200; 627 } 628 629 static void nv17_tv_restore(struct drm_encoder *encoder) 630 { 631 struct drm_device *dev = encoder->dev; 632 633 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + 634 nv04_dac_output_offset(encoder), 635 nouveau_encoder(encoder)->restore.output); 636 637 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); 638 639 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED; 640 } 641 642 static int nv17_tv_create_resources(struct drm_encoder *encoder, 643 struct drm_connector *connector) 644 { 645 struct drm_device *dev = encoder->dev; 646 struct nouveau_drm *drm = nouveau_drm(dev); 647 struct drm_mode_config *conf = &dev->mode_config; 648 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 649 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; 650 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS : 651 NUM_LD_TV_NORMS; 652 int i; 653 654 if (nouveau_tv_norm) { 655 for (i = 0; i < num_tv_norms; i++) { 656 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) { 657 tv_enc->tv_norm = i; 658 break; 659 } 660 } 661 662 if (i == num_tv_norms) 663 NV_WARN(drm, "Invalid TV norm setting \"%s\"\n", 664 nouveau_tv_norm); 665 } 666 667 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names); 668 669 drm_object_attach_property(&connector->base, 670 conf->tv_select_subconnector_property, 671 tv_enc->select_subconnector); 672 drm_object_attach_property(&connector->base, 673 conf->tv_subconnector_property, 674 tv_enc->subconnector); 675 drm_object_attach_property(&connector->base, 676 conf->tv_mode_property, 677 tv_enc->tv_norm); 678 drm_object_attach_property(&connector->base, 679 conf->tv_flicker_reduction_property, 680 tv_enc->flicker); 681 drm_object_attach_property(&connector->base, 682 conf->tv_saturation_property, 683 tv_enc->saturation); 684 drm_object_attach_property(&connector->base, 685 conf->tv_hue_property, 686 tv_enc->hue); 687 drm_object_attach_property(&connector->base, 688 conf->tv_overscan_property, 689 tv_enc->overscan); 690 691 return 0; 692 } 693 694 static int nv17_tv_set_property(struct drm_encoder *encoder, 695 struct drm_connector *connector, 696 struct drm_property *property, 697 uint64_t val) 698 { 699 struct drm_mode_config *conf = &encoder->dev->mode_config; 700 struct drm_crtc *crtc = encoder->crtc; 701 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 702 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 703 bool modes_changed = false; 704 705 if (property == conf->tv_overscan_property) { 706 tv_enc->overscan = val; 707 if (encoder->crtc) { 708 if (tv_norm->kind == CTV_ENC_MODE) 709 nv17_ctv_update_rescaler(encoder); 710 else 711 nv17_tv_update_rescaler(encoder); 712 } 713 714 } else if (property == conf->tv_saturation_property) { 715 if (tv_norm->kind != TV_ENC_MODE) 716 return -EINVAL; 717 718 tv_enc->saturation = val; 719 nv17_tv_update_properties(encoder); 720 721 } else if (property == conf->tv_hue_property) { 722 if (tv_norm->kind != TV_ENC_MODE) 723 return -EINVAL; 724 725 tv_enc->hue = val; 726 nv17_tv_update_properties(encoder); 727 728 } else if (property == conf->tv_flicker_reduction_property) { 729 if (tv_norm->kind != TV_ENC_MODE) 730 return -EINVAL; 731 732 tv_enc->flicker = val; 733 if (encoder->crtc) 734 nv17_tv_update_rescaler(encoder); 735 736 } else if (property == conf->tv_mode_property) { 737 if (connector->dpms != DRM_MODE_DPMS_OFF) 738 return -EINVAL; 739 740 tv_enc->tv_norm = val; 741 742 modes_changed = true; 743 744 } else if (property == conf->tv_select_subconnector_property) { 745 if (tv_norm->kind != TV_ENC_MODE) 746 return -EINVAL; 747 748 tv_enc->select_subconnector = val; 749 nv17_tv_update_properties(encoder); 750 751 } else { 752 return -EINVAL; 753 } 754 755 if (modes_changed) { 756 drm_helper_probe_single_connector_modes(connector, 0, 0); 757 758 /* Disable the crtc to ensure a full modeset is 759 * performed whenever it's turned on again. */ 760 if (crtc) { 761 struct drm_mode_set modeset = { 762 .crtc = crtc, 763 }; 764 765 drm_mode_set_config_internal(&modeset); 766 } 767 } 768 769 return 0; 770 } 771 772 static void nv17_tv_destroy(struct drm_encoder *encoder) 773 { 774 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 775 776 drm_encoder_cleanup(encoder); 777 kfree(tv_enc); 778 } 779 780 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = { 781 .dpms = nv17_tv_dpms, 782 .save = nv17_tv_save, 783 .restore = nv17_tv_restore, 784 .mode_fixup = nv17_tv_mode_fixup, 785 .prepare = nv17_tv_prepare, 786 .commit = nv17_tv_commit, 787 .mode_set = nv17_tv_mode_set, 788 .detect = nv17_tv_detect, 789 }; 790 791 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { 792 .get_modes = nv17_tv_get_modes, 793 .mode_valid = nv17_tv_mode_valid, 794 .create_resources = nv17_tv_create_resources, 795 .set_property = nv17_tv_set_property, 796 }; 797 798 static struct drm_encoder_funcs nv17_tv_funcs = { 799 .destroy = nv17_tv_destroy, 800 }; 801 802 int 803 nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry) 804 { 805 struct drm_device *dev = connector->dev; 806 struct drm_encoder *encoder; 807 struct nv17_tv_encoder *tv_enc = NULL; 808 809 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL); 810 if (!tv_enc) 811 return -ENOMEM; 812 813 tv_enc->overscan = 50; 814 tv_enc->flicker = 50; 815 tv_enc->saturation = 50; 816 tv_enc->hue = 0; 817 tv_enc->tv_norm = TV_NORM_PAL; 818 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 819 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic; 820 tv_enc->pin_mask = 0; 821 822 encoder = to_drm_encoder(&tv_enc->base); 823 824 tv_enc->base.dcb = entry; 825 tv_enc->base.or = ffs(entry->or) - 1; 826 827 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC); 828 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs); 829 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs; 830 831 encoder->possible_crtcs = entry->heads; 832 encoder->possible_clones = 0; 833 834 nv17_tv_create_resources(encoder, connector); 835 drm_mode_connector_attach_encoder(connector, encoder); 836 return 0; 837 } 838