1 /* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #include "nouveau_drv.h" 26 #include "hw.h" 27 28 #include <subdev/bios/pll.h> 29 30 #define CHIPSET_NFORCE 0x01a0 31 #define CHIPSET_NFORCE2 0x01f0 32 33 /* 34 * misc hw access wrappers/control functions 35 */ 36 37 void 38 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) 39 { 40 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 41 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); 42 } 43 44 uint8_t 45 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) 46 { 47 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 48 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); 49 } 50 51 void 52 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) 53 { 54 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 55 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); 56 } 57 58 uint8_t 59 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) 60 { 61 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 62 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); 63 } 64 65 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 66 * it affects only the 8 bit vga io regs, which we access using mmio at 67 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 68 * in general, the set value of cr44 does not matter: reg access works as 69 * expected and values can be set for the appropriate head by using a 0x2000 70 * offset as required 71 * however: 72 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 73 * cr44 must be set to 0 or 3 for accessing values on the correct head 74 * through the common 0xc03c* addresses 75 * b) in tied mode (4) head B is programmed to the values set on head A, and 76 * access using the head B addresses can have strange results, ergo we leave 77 * tied mode in init once we know to what cr44 should be restored on exit 78 * 79 * the owner parameter is slightly abused: 80 * 0 and 1 are treated as head values and so the set value is (owner * 3) 81 * other values are treated as literal values to set 82 */ 83 void 84 NVSetOwner(struct drm_device *dev, int owner) 85 { 86 struct nouveau_drm *drm = nouveau_drm(dev); 87 88 if (owner == 1) 89 owner *= 3; 90 91 if (drm->client.device.info.chipset == 0x11) { 92 /* This might seem stupid, but the blob does it and 93 * omitting it often locks the system up. 94 */ 95 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 96 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); 97 } 98 99 /* CR44 is always changed on CRTC0 */ 100 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 101 102 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ 103 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 105 } 106 } 107 108 void 109 NVBlankScreen(struct drm_device *dev, int head, bool blank) 110 { 111 unsigned char seq1; 112 113 if (nv_two_heads(dev)) 114 NVSetOwner(dev, head); 115 116 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 117 118 NVVgaSeqReset(dev, head, true); 119 if (blank) 120 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 121 else 122 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); 123 NVVgaSeqReset(dev, head, false); 124 } 125 126 /* 127 * PLL getting 128 */ 129 130 static void 131 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 132 uint32_t pll2, struct nvkm_pll_vals *pllvals) 133 { 134 struct nouveau_drm *drm = nouveau_drm(dev); 135 136 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 137 138 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 139 pllvals->log2P = (pll1 >> 16) & 0x7; 140 pllvals->N2 = pllvals->M2 = 1; 141 142 if (reg1 <= 0x405c) { 143 pllvals->NM1 = pll2 & 0xffff; 144 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ 145 if (!(pll1 & 0x1100)) 146 pllvals->NM2 = pll2 >> 16; 147 } else { 148 pllvals->NM1 = pll1 & 0xffff; 149 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 150 pllvals->NM2 = pll2 & 0xffff; 151 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { 152 pllvals->M1 &= 0xf; /* only 4 bits */ 153 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 154 pllvals->M2 = (pll1 >> 4) & 0x7; 155 pllvals->N2 = ((pll1 >> 21) & 0x18) | 156 ((pll1 >> 19) & 0x7); 157 } 158 } 159 } 160 } 161 162 int 163 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 164 struct nvkm_pll_vals *pllvals) 165 { 166 struct nouveau_drm *drm = nouveau_drm(dev); 167 struct nvif_object *device = &drm->client.device.object; 168 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 169 uint32_t reg1, pll1, pll2 = 0; 170 struct nvbios_pll pll_lim; 171 int ret; 172 173 ret = nvbios_pll_parse(bios, plltype, &pll_lim); 174 if (ret || !(reg1 = pll_lim.reg)) 175 return -ENOENT; 176 177 pll1 = nvif_rd32(device, reg1); 178 if (reg1 <= 0x405c) 179 pll2 = nvif_rd32(device, reg1 + 4); 180 else if (nv_two_reg_pll(dev)) { 181 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 182 183 pll2 = nvif_rd32(device, reg2); 184 } 185 186 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 187 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 188 189 /* check whether vpll has been forced into single stage mode */ 190 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { 191 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) 192 pll2 = 0; 193 } else 194 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) 195 pll2 = 0; 196 } 197 198 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 199 pllvals->refclk = pll_lim.refclk; 200 return 0; 201 } 202 203 int 204 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) 205 { 206 /* Avoid divide by zero if called at an inappropriate time */ 207 if (!pv->M1 || !pv->M2) 208 return 0; 209 210 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 211 } 212 213 int 214 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) 215 { 216 struct nvkm_pll_vals pllvals; 217 int ret; 218 int domain; 219 220 domain = pci_domain_nr(dev->pdev->bus); 221 222 if (plltype == PLL_MEMORY && 223 (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { 224 uint32_t mpllP; 225 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3), 226 0x6c, &mpllP); 227 mpllP = (mpllP >> 8) & 0xf; 228 if (!mpllP) 229 mpllP = 4; 230 231 return 400000 / mpllP; 232 } else 233 if (plltype == PLL_MEMORY && 234 (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { 235 uint32_t clock; 236 237 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5), 238 0x4c, &clock); 239 return clock / 1000; 240 } 241 242 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); 243 if (ret) 244 return ret; 245 246 return nouveau_hw_pllvals_to_clk(&pllvals); 247 } 248 249 static void 250 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) 251 { 252 /* the vpll on an unused head can come up with a random value, way 253 * beyond the pll limits. for some reason this causes the chip to 254 * lock up when reading the dac palette regs, so set a valid pll here 255 * when such a condition detected. only seen on nv11 to date 256 */ 257 258 struct nouveau_drm *drm = nouveau_drm(dev); 259 struct nvif_device *device = &drm->client.device; 260 struct nvkm_clk *clk = nvxx_clk(device); 261 struct nvkm_bios *bios = nvxx_bios(device); 262 struct nvbios_pll pll_lim; 263 struct nvkm_pll_vals pv; 264 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 265 266 if (nvbios_pll_parse(bios, pll, &pll_lim)) 267 return; 268 nouveau_hw_get_pllvals(dev, pll, &pv); 269 270 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && 271 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && 272 pv.log2P <= pll_lim.max_p) 273 return; 274 275 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); 276 277 /* set lowest clock within static limits */ 278 pv.M1 = pll_lim.vco1.max_m; 279 pv.N1 = pll_lim.vco1.min_n; 280 pv.log2P = pll_lim.max_p_usable; 281 clk->pll_prog(clk, pll_lim.reg, &pv); 282 } 283 284 /* 285 * vga font save/restore 286 */ 287 288 static void nouveau_vga_font_io(struct drm_device *dev, 289 void __iomem *iovram, 290 bool save, unsigned plane) 291 { 292 unsigned i; 293 294 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); 295 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); 296 for (i = 0; i < 16384; i++) { 297 if (save) { 298 nv04_display(dev)->saved_vga_font[plane][i] = 299 ioread32_native(iovram + i * 4); 300 } else { 301 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], 302 iovram + i * 4); 303 } 304 } 305 } 306 307 void 308 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 309 { 310 struct nouveau_drm *drm = nouveau_drm(dev); 311 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 312 bool graphicsmode; 313 unsigned plane; 314 void __iomem *iovram; 315 316 if (nv_two_heads(dev)) 317 NVSetOwner(dev, 0); 318 319 NVSetEnablePalette(dev, 0, true); 320 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; 321 NVSetEnablePalette(dev, 0, false); 322 323 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 324 return; 325 326 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 327 328 /* map first 64KiB of VRAM, holds VGA fonts etc */ 329 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); 330 if (!iovram) { 331 NV_ERROR(drm, "Failed to map VRAM, " 332 "cannot save/restore VGA fonts.\n"); 333 return; 334 } 335 336 if (nv_two_heads(dev)) 337 NVBlankScreen(dev, 1, true); 338 NVBlankScreen(dev, 0, true); 339 340 /* save control regs */ 341 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); 342 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); 343 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); 344 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); 345 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); 346 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); 347 348 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); 349 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); 350 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); 351 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); 352 353 /* store font in planes 0..3 */ 354 for (plane = 0; plane < 4; plane++) 355 nouveau_vga_font_io(dev, iovram, save, plane); 356 357 /* restore control regs */ 358 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); 359 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); 360 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); 361 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); 362 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); 363 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); 364 365 if (nv_two_heads(dev)) 366 NVBlankScreen(dev, 1, false); 367 NVBlankScreen(dev, 0, false); 368 369 iounmap(iovram); 370 } 371 372 /* 373 * mode state save/load 374 */ 375 376 static void 377 rd_cio_state(struct drm_device *dev, int head, 378 struct nv04_crtc_reg *crtcstate, int index) 379 { 380 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 381 } 382 383 static void 384 wr_cio_state(struct drm_device *dev, int head, 385 struct nv04_crtc_reg *crtcstate, int index) 386 { 387 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); 388 } 389 390 static void 391 nv_save_state_ramdac(struct drm_device *dev, int head, 392 struct nv04_mode_state *state) 393 { 394 struct nouveau_drm *drm = nouveau_drm(dev); 395 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 396 int i; 397 398 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 399 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 400 401 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); 402 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 403 if (nv_two_heads(dev)) 404 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 405 if (drm->client.device.info.chipset == 0x11) 406 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 407 408 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 409 410 if (nv_gf4_disp_arch(dev)) 411 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 412 if (drm->client.device.info.chipset >= 0x30) 413 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 414 415 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 416 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); 417 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); 418 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); 419 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); 420 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); 421 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); 422 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); 423 424 for (i = 0; i < 7; i++) { 425 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 426 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); 427 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); 428 } 429 430 if (nv_gf4_disp_arch(dev)) { 431 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); 432 for (i = 0; i < 3; i++) { 433 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); 434 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); 435 } 436 } 437 438 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 439 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); 440 if (!nv_gf4_disp_arch(dev) && head == 0) { 441 /* early chips don't allow access to PRAMDAC_TMDS_* without 442 * the head A FPCLK on (nv11 even locks up) */ 443 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & 444 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); 445 } 446 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); 447 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); 448 449 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); 450 451 if (nv_gf4_disp_arch(dev)) 452 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 453 454 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 455 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 456 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 457 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 458 459 for (i = 0; i < 38; i++) 460 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, 461 NV_PRAMDAC_CTV + 4*i); 462 } 463 } 464 465 static void 466 nv_load_state_ramdac(struct drm_device *dev, int head, 467 struct nv04_mode_state *state) 468 { 469 struct nouveau_drm *drm = nouveau_drm(dev); 470 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 471 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 472 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 473 int i; 474 475 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 476 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 477 478 clk->pll_prog(clk, pllreg, ®p->pllvals); 479 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 480 if (nv_two_heads(dev)) 481 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 482 if (drm->client.device.info.chipset == 0x11) 483 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 484 485 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 486 487 if (nv_gf4_disp_arch(dev)) 488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 489 if (drm->client.device.info.chipset >= 0x30) 490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 491 492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); 494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); 495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); 496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); 497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); 498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); 499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); 500 501 for (i = 0; i < 7; i++) { 502 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 503 504 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); 505 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); 506 } 507 508 if (nv_gf4_disp_arch(dev)) { 509 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); 510 for (i = 0; i < 3; i++) { 511 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); 512 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); 513 } 514 } 515 516 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); 517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); 518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); 519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); 520 521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); 522 523 if (nv_gf4_disp_arch(dev)) 524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 525 526 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 530 531 for (i = 0; i < 38; i++) 532 NVWriteRAMDAC(dev, head, 533 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); 534 } 535 } 536 537 static void 538 nv_save_state_vga(struct drm_device *dev, int head, 539 struct nv04_mode_state *state) 540 { 541 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 542 int i; 543 544 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); 545 546 for (i = 0; i < 25; i++) 547 rd_cio_state(dev, head, regp, i); 548 549 NVSetEnablePalette(dev, head, true); 550 for (i = 0; i < 21; i++) 551 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); 552 NVSetEnablePalette(dev, head, false); 553 554 for (i = 0; i < 9; i++) 555 regp->Graphics[i] = NVReadVgaGr(dev, head, i); 556 557 for (i = 0; i < 5; i++) 558 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); 559 } 560 561 static void 562 nv_load_state_vga(struct drm_device *dev, int head, 563 struct nv04_mode_state *state) 564 { 565 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 566 int i; 567 568 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); 569 570 for (i = 0; i < 5; i++) 571 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); 572 573 nv_lock_vga_crtc_base(dev, head, false); 574 for (i = 0; i < 25; i++) 575 wr_cio_state(dev, head, regp, i); 576 nv_lock_vga_crtc_base(dev, head, true); 577 578 for (i = 0; i < 9; i++) 579 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); 580 581 NVSetEnablePalette(dev, head, true); 582 for (i = 0; i < 21; i++) 583 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); 584 NVSetEnablePalette(dev, head, false); 585 } 586 587 static void 588 nv_save_state_ext(struct drm_device *dev, int head, 589 struct nv04_mode_state *state) 590 { 591 struct nouveau_drm *drm = nouveau_drm(dev); 592 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 593 int i; 594 595 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 596 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 597 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 598 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 599 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 600 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 601 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 602 603 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 604 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 605 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 606 607 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 608 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 609 610 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 611 rd_cio_state(dev, head, regp, 0x9f); 612 613 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 614 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 615 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 616 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 617 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 618 619 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 620 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 621 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 622 623 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 624 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 625 626 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 627 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 628 629 if (nv_two_heads(dev)) 630 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); 631 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); 632 } 633 634 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); 635 636 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 637 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 638 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 639 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 640 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 641 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 642 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 643 } 644 /* NV11 and NV20 don't have this, they stop at 0x52. */ 645 if (nv_gf4_disp_arch(dev)) { 646 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); 647 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); 648 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); 649 650 for (i = 0; i < 0x10; i++) 651 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); 652 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); 653 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); 654 655 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); 656 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); 657 } 658 659 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); 660 } 661 662 static void 663 nv_load_state_ext(struct drm_device *dev, int head, 664 struct nv04_mode_state *state) 665 { 666 struct nouveau_drm *drm = nouveau_drm(dev); 667 struct nvif_object *device = &drm->client.device.object; 668 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 669 uint32_t reg900; 670 int i; 671 672 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 673 if (nv_two_heads(dev)) 674 /* setting ENGINE_CTRL (EC) *must* come before 675 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 676 * EC that should not be overwritten by writing stale EC 677 */ 678 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 679 680 nvif_wr32(device, NV_PVIDEO_STOP, 1); 681 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); 682 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); 683 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); 684 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); 685 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); 686 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); 687 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); 688 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); 689 690 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 691 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 692 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 693 694 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 695 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 696 697 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 698 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 699 700 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 701 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) 702 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); 703 else 704 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); 705 } 706 } 707 708 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); 709 710 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 711 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 712 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 713 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 714 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 715 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 716 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 717 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 718 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 719 720 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 721 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 722 723 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 724 wr_cio_state(dev, head, regp, 0x9f); 725 726 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 727 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 730 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 731 nv_fix_nv40_hw_cursor(dev, head); 732 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 733 734 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 735 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 736 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 738 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 739 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 740 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 741 } 742 /* NV11 and NV20 stop at 0x52. */ 743 if (nv_gf4_disp_arch(dev)) { 744 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 745 /* Not waiting for vertical retrace before modifying 746 CRE_53/CRE_54 causes lockups. */ 747 nvif_msec(&drm->client.device, 650, 748 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 749 break; 750 ); 751 nvif_msec(&drm->client.device, 650, 752 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 753 break; 754 ); 755 } 756 757 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 758 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 759 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 760 761 for (i = 0; i < 0x10; i++) 762 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); 763 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); 764 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); 765 766 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); 767 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); 768 } 769 770 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); 771 } 772 773 static void 774 nv_save_state_palette(struct drm_device *dev, int head, 775 struct nv04_mode_state *state) 776 { 777 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 778 int head_offset = head * NV_PRMDIO_SIZE, i; 779 780 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 781 NV_PRMDIO_PIXEL_MASK_MASK); 782 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 783 784 for (i = 0; i < 768; i++) { 785 state->crtc_reg[head].DAC[i] = nvif_rd08(device, 786 NV_PRMDIO_PALETTE_DATA + head_offset); 787 } 788 789 NVSetEnablePalette(dev, head, false); 790 } 791 792 void 793 nouveau_hw_load_state_palette(struct drm_device *dev, int head, 794 struct nv04_mode_state *state) 795 { 796 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 797 int head_offset = head * NV_PRMDIO_SIZE, i; 798 799 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 800 NV_PRMDIO_PIXEL_MASK_MASK); 801 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 802 803 for (i = 0; i < 768; i++) { 804 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, 805 state->crtc_reg[head].DAC[i]); 806 } 807 808 NVSetEnablePalette(dev, head, false); 809 } 810 811 void nouveau_hw_save_state(struct drm_device *dev, int head, 812 struct nv04_mode_state *state) 813 { 814 struct nouveau_drm *drm = nouveau_drm(dev); 815 816 if (drm->client.device.info.chipset == 0x11) 817 /* NB: no attempt is made to restore the bad pll later on */ 818 nouveau_hw_fix_bad_vpll(dev, head); 819 nv_save_state_ramdac(dev, head, state); 820 nv_save_state_vga(dev, head, state); 821 nv_save_state_palette(dev, head, state); 822 nv_save_state_ext(dev, head, state); 823 } 824 825 void nouveau_hw_load_state(struct drm_device *dev, int head, 826 struct nv04_mode_state *state) 827 { 828 NVVgaProtect(dev, head, true); 829 nv_load_state_ramdac(dev, head, state); 830 nv_load_state_ext(dev, head, state); 831 nouveau_hw_load_state_palette(dev, head, state); 832 nv_load_state_vga(dev, head, state); 833 NVVgaProtect(dev, head, false); 834 } 835