1 /* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include "nouveau_drv.h" 27 #include "hw.h" 28 29 #include <subdev/bios/pll.h> 30 31 #define CHIPSET_NFORCE 0x01a0 32 #define CHIPSET_NFORCE2 0x01f0 33 34 /* 35 * misc hw access wrappers/control functions 36 */ 37 38 void 39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) 40 { 41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); 43 } 44 45 uint8_t 46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) 47 { 48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); 50 } 51 52 void 53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) 54 { 55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); 57 } 58 59 uint8_t 60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) 61 { 62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); 64 } 65 66 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 67 * it affects only the 8 bit vga io regs, which we access using mmio at 68 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 69 * in general, the set value of cr44 does not matter: reg access works as 70 * expected and values can be set for the appropriate head by using a 0x2000 71 * offset as required 72 * however: 73 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 74 * cr44 must be set to 0 or 3 for accessing values on the correct head 75 * through the common 0xc03c* addresses 76 * b) in tied mode (4) head B is programmed to the values set on head A, and 77 * access using the head B addresses can have strange results, ergo we leave 78 * tied mode in init once we know to what cr44 should be restored on exit 79 * 80 * the owner parameter is slightly abused: 81 * 0 and 1 are treated as head values and so the set value is (owner * 3) 82 * other values are treated as literal values to set 83 */ 84 void 85 NVSetOwner(struct drm_device *dev, int owner) 86 { 87 struct nouveau_drm *drm = nouveau_drm(dev); 88 89 if (owner == 1) 90 owner *= 3; 91 92 if (drm->client.device.info.chipset == 0x11) { 93 /* This might seem stupid, but the blob does it and 94 * omitting it often locks the system up. 95 */ 96 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 97 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); 98 } 99 100 /* CR44 is always changed on CRTC0 */ 101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 102 103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ 104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 106 } 107 } 108 109 void 110 NVBlankScreen(struct drm_device *dev, int head, bool blank) 111 { 112 unsigned char seq1; 113 114 if (nv_two_heads(dev)) 115 NVSetOwner(dev, head); 116 117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 118 119 NVVgaSeqReset(dev, head, true); 120 if (blank) 121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 122 else 123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); 124 NVVgaSeqReset(dev, head, false); 125 } 126 127 /* 128 * PLL getting 129 */ 130 131 static void 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 133 uint32_t pll2, struct nvkm_pll_vals *pllvals) 134 { 135 struct nouveau_drm *drm = nouveau_drm(dev); 136 137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 138 139 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 140 pllvals->log2P = (pll1 >> 16) & 0x7; 141 pllvals->N2 = pllvals->M2 = 1; 142 143 if (reg1 <= 0x405c) { 144 pllvals->NM1 = pll2 & 0xffff; 145 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ 146 if (!(pll1 & 0x1100)) 147 pllvals->NM2 = pll2 >> 16; 148 } else { 149 pllvals->NM1 = pll1 & 0xffff; 150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 151 pllvals->NM2 = pll2 & 0xffff; 152 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { 153 pllvals->M1 &= 0xf; /* only 4 bits */ 154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 155 pllvals->M2 = (pll1 >> 4) & 0x7; 156 pllvals->N2 = ((pll1 >> 21) & 0x18) | 157 ((pll1 >> 19) & 0x7); 158 } 159 } 160 } 161 } 162 163 int 164 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 165 struct nvkm_pll_vals *pllvals) 166 { 167 struct nouveau_drm *drm = nouveau_drm(dev); 168 struct nvif_object *device = &drm->client.device.object; 169 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 170 uint32_t reg1, pll1, pll2 = 0; 171 struct nvbios_pll pll_lim; 172 int ret; 173 174 ret = nvbios_pll_parse(bios, plltype, &pll_lim); 175 if (ret || !(reg1 = pll_lim.reg)) 176 return -ENOENT; 177 178 pll1 = nvif_rd32(device, reg1); 179 if (reg1 <= 0x405c) 180 pll2 = nvif_rd32(device, reg1 + 4); 181 else if (nv_two_reg_pll(dev)) { 182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 183 184 pll2 = nvif_rd32(device, reg2); 185 } 186 187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 188 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 189 190 /* check whether vpll has been forced into single stage mode */ 191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { 192 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) 193 pll2 = 0; 194 } else 195 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) 196 pll2 = 0; 197 } 198 199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 200 pllvals->refclk = pll_lim.refclk; 201 return 0; 202 } 203 204 int 205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) 206 { 207 /* Avoid divide by zero if called at an inappropriate time */ 208 if (!pv->M1 || !pv->M2) 209 return 0; 210 211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 212 } 213 214 int 215 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) 216 { 217 struct nvkm_pll_vals pllvals; 218 int ret; 219 220 if (plltype == PLL_MEMORY && 221 (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { 222 uint32_t mpllP; 223 224 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); 225 mpllP = (mpllP >> 8) & 0xf; 226 if (!mpllP) 227 mpllP = 4; 228 229 return 400000 / mpllP; 230 } else 231 if (plltype == PLL_MEMORY && 232 (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { 233 uint32_t clock; 234 235 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); 236 return clock / 1000; 237 } 238 239 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); 240 if (ret) 241 return ret; 242 243 return nouveau_hw_pllvals_to_clk(&pllvals); 244 } 245 246 static void 247 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) 248 { 249 /* the vpll on an unused head can come up with a random value, way 250 * beyond the pll limits. for some reason this causes the chip to 251 * lock up when reading the dac palette regs, so set a valid pll here 252 * when such a condition detected. only seen on nv11 to date 253 */ 254 255 struct nouveau_drm *drm = nouveau_drm(dev); 256 struct nvif_device *device = &drm->client.device; 257 struct nvkm_clk *clk = nvxx_clk(device); 258 struct nvkm_bios *bios = nvxx_bios(device); 259 struct nvbios_pll pll_lim; 260 struct nvkm_pll_vals pv; 261 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 262 263 if (nvbios_pll_parse(bios, pll, &pll_lim)) 264 return; 265 nouveau_hw_get_pllvals(dev, pll, &pv); 266 267 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && 268 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && 269 pv.log2P <= pll_lim.max_p) 270 return; 271 272 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); 273 274 /* set lowest clock within static limits */ 275 pv.M1 = pll_lim.vco1.max_m; 276 pv.N1 = pll_lim.vco1.min_n; 277 pv.log2P = pll_lim.max_p_usable; 278 clk->pll_prog(clk, pll_lim.reg, &pv); 279 } 280 281 /* 282 * vga font save/restore 283 */ 284 285 static void nouveau_vga_font_io(struct drm_device *dev, 286 void __iomem *iovram, 287 bool save, unsigned plane) 288 { 289 unsigned i; 290 291 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); 292 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); 293 for (i = 0; i < 16384; i++) { 294 if (save) { 295 nv04_display(dev)->saved_vga_font[plane][i] = 296 ioread32_native(iovram + i * 4); 297 } else { 298 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], 299 iovram + i * 4); 300 } 301 } 302 } 303 304 void 305 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 306 { 307 struct nouveau_drm *drm = nouveau_drm(dev); 308 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 309 bool graphicsmode; 310 unsigned plane; 311 void __iomem *iovram; 312 313 if (nv_two_heads(dev)) 314 NVSetOwner(dev, 0); 315 316 NVSetEnablePalette(dev, 0, true); 317 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; 318 NVSetEnablePalette(dev, 0, false); 319 320 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 321 return; 322 323 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 324 325 /* map first 64KiB of VRAM, holds VGA fonts etc */ 326 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); 327 if (!iovram) { 328 NV_ERROR(drm, "Failed to map VRAM, " 329 "cannot save/restore VGA fonts.\n"); 330 return; 331 } 332 333 if (nv_two_heads(dev)) 334 NVBlankScreen(dev, 1, true); 335 NVBlankScreen(dev, 0, true); 336 337 /* save control regs */ 338 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); 339 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); 340 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); 341 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); 342 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); 343 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); 344 345 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); 346 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); 347 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); 348 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); 349 350 /* store font in planes 0..3 */ 351 for (plane = 0; plane < 4; plane++) 352 nouveau_vga_font_io(dev, iovram, save, plane); 353 354 /* restore control regs */ 355 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); 356 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); 357 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); 358 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); 359 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); 360 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); 361 362 if (nv_two_heads(dev)) 363 NVBlankScreen(dev, 1, false); 364 NVBlankScreen(dev, 0, false); 365 366 iounmap(iovram); 367 } 368 369 /* 370 * mode state save/load 371 */ 372 373 static void 374 rd_cio_state(struct drm_device *dev, int head, 375 struct nv04_crtc_reg *crtcstate, int index) 376 { 377 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 378 } 379 380 static void 381 wr_cio_state(struct drm_device *dev, int head, 382 struct nv04_crtc_reg *crtcstate, int index) 383 { 384 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); 385 } 386 387 static void 388 nv_save_state_ramdac(struct drm_device *dev, int head, 389 struct nv04_mode_state *state) 390 { 391 struct nouveau_drm *drm = nouveau_drm(dev); 392 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 393 int i; 394 395 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 396 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 397 398 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); 399 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 400 if (nv_two_heads(dev)) 401 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 402 if (drm->client.device.info.chipset == 0x11) 403 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 404 405 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 406 407 if (nv_gf4_disp_arch(dev)) 408 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 409 if (drm->client.device.info.chipset >= 0x30) 410 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 411 412 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 413 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); 414 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); 415 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); 416 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); 417 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); 418 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); 419 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); 420 421 for (i = 0; i < 7; i++) { 422 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 423 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); 424 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); 425 } 426 427 if (nv_gf4_disp_arch(dev)) { 428 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); 429 for (i = 0; i < 3; i++) { 430 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); 431 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); 432 } 433 } 434 435 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 436 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); 437 if (!nv_gf4_disp_arch(dev) && head == 0) { 438 /* early chips don't allow access to PRAMDAC_TMDS_* without 439 * the head A FPCLK on (nv11 even locks up) */ 440 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & 441 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); 442 } 443 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); 444 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); 445 446 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); 447 448 if (nv_gf4_disp_arch(dev)) 449 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 450 451 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 452 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 453 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 454 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 455 456 for (i = 0; i < 38; i++) 457 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, 458 NV_PRAMDAC_CTV + 4*i); 459 } 460 } 461 462 static void 463 nv_load_state_ramdac(struct drm_device *dev, int head, 464 struct nv04_mode_state *state) 465 { 466 struct nouveau_drm *drm = nouveau_drm(dev); 467 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 468 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 469 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 470 int i; 471 472 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 473 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 474 475 clk->pll_prog(clk, pllreg, ®p->pllvals); 476 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 477 if (nv_two_heads(dev)) 478 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 479 if (drm->client.device.info.chipset == 0x11) 480 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 481 482 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 483 484 if (nv_gf4_disp_arch(dev)) 485 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 486 if (drm->client.device.info.chipset >= 0x30) 487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 488 489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); 491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); 492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); 493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); 494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); 495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); 496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); 497 498 for (i = 0; i < 7; i++) { 499 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 500 501 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); 502 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); 503 } 504 505 if (nv_gf4_disp_arch(dev)) { 506 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); 507 for (i = 0; i < 3; i++) { 508 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); 509 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); 510 } 511 } 512 513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); 514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); 515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); 516 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); 517 518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); 519 520 if (nv_gf4_disp_arch(dev)) 521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 522 523 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 525 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 527 528 for (i = 0; i < 38; i++) 529 NVWriteRAMDAC(dev, head, 530 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); 531 } 532 } 533 534 static void 535 nv_save_state_vga(struct drm_device *dev, int head, 536 struct nv04_mode_state *state) 537 { 538 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 539 int i; 540 541 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); 542 543 for (i = 0; i < 25; i++) 544 rd_cio_state(dev, head, regp, i); 545 546 NVSetEnablePalette(dev, head, true); 547 for (i = 0; i < 21; i++) 548 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); 549 NVSetEnablePalette(dev, head, false); 550 551 for (i = 0; i < 9; i++) 552 regp->Graphics[i] = NVReadVgaGr(dev, head, i); 553 554 for (i = 0; i < 5; i++) 555 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); 556 } 557 558 static void 559 nv_load_state_vga(struct drm_device *dev, int head, 560 struct nv04_mode_state *state) 561 { 562 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 563 int i; 564 565 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); 566 567 for (i = 0; i < 5; i++) 568 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); 569 570 nv_lock_vga_crtc_base(dev, head, false); 571 for (i = 0; i < 25; i++) 572 wr_cio_state(dev, head, regp, i); 573 nv_lock_vga_crtc_base(dev, head, true); 574 575 for (i = 0; i < 9; i++) 576 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); 577 578 NVSetEnablePalette(dev, head, true); 579 for (i = 0; i < 21; i++) 580 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); 581 NVSetEnablePalette(dev, head, false); 582 } 583 584 static void 585 nv_save_state_ext(struct drm_device *dev, int head, 586 struct nv04_mode_state *state) 587 { 588 struct nouveau_drm *drm = nouveau_drm(dev); 589 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 590 int i; 591 592 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 593 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 594 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 595 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 596 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 597 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 598 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 599 600 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 601 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 602 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 603 604 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 605 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 606 607 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 608 rd_cio_state(dev, head, regp, 0x9f); 609 610 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 611 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 612 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 613 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 614 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 615 616 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 617 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 618 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 619 620 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 621 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 622 623 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 624 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 625 626 if (nv_two_heads(dev)) 627 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); 628 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); 629 } 630 631 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); 632 633 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 634 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 635 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 636 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 637 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 638 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 639 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 640 } 641 /* NV11 and NV20 don't have this, they stop at 0x52. */ 642 if (nv_gf4_disp_arch(dev)) { 643 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); 644 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); 645 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); 646 647 for (i = 0; i < 0x10; i++) 648 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); 649 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); 650 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); 651 652 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); 653 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); 654 } 655 656 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); 657 } 658 659 static void 660 nv_load_state_ext(struct drm_device *dev, int head, 661 struct nv04_mode_state *state) 662 { 663 struct nouveau_drm *drm = nouveau_drm(dev); 664 struct nvif_object *device = &drm->client.device.object; 665 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 666 uint32_t reg900; 667 int i; 668 669 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 670 if (nv_two_heads(dev)) 671 /* setting ENGINE_CTRL (EC) *must* come before 672 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 673 * EC that should not be overwritten by writing stale EC 674 */ 675 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 676 677 nvif_wr32(device, NV_PVIDEO_STOP, 1); 678 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); 679 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); 680 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); 681 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); 682 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); 683 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); 684 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); 685 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); 686 687 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 688 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 689 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 690 691 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 692 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 693 694 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 695 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 696 697 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 698 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) 699 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); 700 else 701 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); 702 } 703 } 704 705 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); 706 707 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 708 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 709 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 710 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 711 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 712 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 713 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 714 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 715 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 716 717 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 718 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 719 720 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 721 wr_cio_state(dev, head, regp, 0x9f); 722 723 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 724 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 725 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 726 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 727 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 728 nv_fix_nv40_hw_cursor(dev, head); 729 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 730 731 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 732 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 733 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 734 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 735 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 736 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 738 } 739 /* NV11 and NV20 stop at 0x52. */ 740 if (nv_gf4_disp_arch(dev)) { 741 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 742 /* Not waiting for vertical retrace before modifying 743 CRE_53/CRE_54 causes lockups. */ 744 nvif_msec(&drm->client.device, 650, 745 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 746 break; 747 ); 748 nvif_msec(&drm->client.device, 650, 749 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 750 break; 751 ); 752 } 753 754 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 755 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 756 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 757 758 for (i = 0; i < 0x10; i++) 759 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); 760 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); 761 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); 762 763 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); 764 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); 765 } 766 767 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); 768 } 769 770 static void 771 nv_save_state_palette(struct drm_device *dev, int head, 772 struct nv04_mode_state *state) 773 { 774 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 775 int head_offset = head * NV_PRMDIO_SIZE, i; 776 777 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 778 NV_PRMDIO_PIXEL_MASK_MASK); 779 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 780 781 for (i = 0; i < 768; i++) { 782 state->crtc_reg[head].DAC[i] = nvif_rd08(device, 783 NV_PRMDIO_PALETTE_DATA + head_offset); 784 } 785 786 NVSetEnablePalette(dev, head, false); 787 } 788 789 void 790 nouveau_hw_load_state_palette(struct drm_device *dev, int head, 791 struct nv04_mode_state *state) 792 { 793 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 794 int head_offset = head * NV_PRMDIO_SIZE, i; 795 796 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 797 NV_PRMDIO_PIXEL_MASK_MASK); 798 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 799 800 for (i = 0; i < 768; i++) { 801 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, 802 state->crtc_reg[head].DAC[i]); 803 } 804 805 NVSetEnablePalette(dev, head, false); 806 } 807 808 void nouveau_hw_save_state(struct drm_device *dev, int head, 809 struct nv04_mode_state *state) 810 { 811 struct nouveau_drm *drm = nouveau_drm(dev); 812 813 if (drm->client.device.info.chipset == 0x11) 814 /* NB: no attempt is made to restore the bad pll later on */ 815 nouveau_hw_fix_bad_vpll(dev, head); 816 nv_save_state_ramdac(dev, head, state); 817 nv_save_state_vga(dev, head, state); 818 nv_save_state_palette(dev, head, state); 819 nv_save_state_ext(dev, head, state); 820 } 821 822 void nouveau_hw_load_state(struct drm_device *dev, int head, 823 struct nv04_mode_state *state) 824 { 825 NVVgaProtect(dev, head, true); 826 nv_load_state_ramdac(dev, head, state); 827 nv_load_state_ext(dev, head, state); 828 nouveau_hw_load_state_palette(dev, head, state); 829 nv_load_state_vga(dev, head, state); 830 NVVgaProtect(dev, head, false); 831 } 832