1 /* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include "nouveau_drm.h" 27 #include "hw.h" 28 29 #include <subdev/bios/pll.h> 30 #include <subdev/fb.h> 31 #include <subdev/clock.h> 32 #include <subdev/timer.h> 33 34 #define CHIPSET_NFORCE 0x01a0 35 #define CHIPSET_NFORCE2 0x01f0 36 37 /* 38 * misc hw access wrappers/control functions 39 */ 40 41 void 42 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) 43 { 44 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 45 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); 46 } 47 48 uint8_t 49 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) 50 { 51 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 52 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); 53 } 54 55 void 56 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) 57 { 58 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 59 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); 60 } 61 62 uint8_t 63 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) 64 { 65 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 66 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); 67 } 68 69 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 70 * it affects only the 8 bit vga io regs, which we access using mmio at 71 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 72 * in general, the set value of cr44 does not matter: reg access works as 73 * expected and values can be set for the appropriate head by using a 0x2000 74 * offset as required 75 * however: 76 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 77 * cr44 must be set to 0 or 3 for accessing values on the correct head 78 * through the common 0xc03c* addresses 79 * b) in tied mode (4) head B is programmed to the values set on head A, and 80 * access using the head B addresses can have strange results, ergo we leave 81 * tied mode in init once we know to what cr44 should be restored on exit 82 * 83 * the owner parameter is slightly abused: 84 * 0 and 1 are treated as head values and so the set value is (owner * 3) 85 * other values are treated as literal values to set 86 */ 87 void 88 NVSetOwner(struct drm_device *dev, int owner) 89 { 90 struct nouveau_drm *drm = nouveau_drm(dev); 91 92 if (owner == 1) 93 owner *= 3; 94 95 if (nv_device(drm->device)->chipset == 0x11) { 96 /* This might seem stupid, but the blob does it and 97 * omitting it often locks the system up. 98 */ 99 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 100 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); 101 } 102 103 /* CR44 is always changed on CRTC0 */ 104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 105 106 if (nv_device(drm->device)->chipset == 0x11) { /* set me harder */ 107 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 108 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 109 } 110 } 111 112 void 113 NVBlankScreen(struct drm_device *dev, int head, bool blank) 114 { 115 unsigned char seq1; 116 117 if (nv_two_heads(dev)) 118 NVSetOwner(dev, head); 119 120 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 121 122 NVVgaSeqReset(dev, head, true); 123 if (blank) 124 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 125 else 126 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); 127 NVVgaSeqReset(dev, head, false); 128 } 129 130 /* 131 * PLL getting 132 */ 133 134 static void 135 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 136 uint32_t pll2, struct nouveau_pll_vals *pllvals) 137 { 138 struct nouveau_drm *drm = nouveau_drm(dev); 139 140 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 141 142 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 143 pllvals->log2P = (pll1 >> 16) & 0x7; 144 pllvals->N2 = pllvals->M2 = 1; 145 146 if (reg1 <= 0x405c) { 147 pllvals->NM1 = pll2 & 0xffff; 148 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ 149 if (!(pll1 & 0x1100)) 150 pllvals->NM2 = pll2 >> 16; 151 } else { 152 pllvals->NM1 = pll1 & 0xffff; 153 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 154 pllvals->NM2 = pll2 & 0xffff; 155 else if (nv_device(drm->device)->chipset == 0x30 || nv_device(drm->device)->chipset == 0x35) { 156 pllvals->M1 &= 0xf; /* only 4 bits */ 157 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 158 pllvals->M2 = (pll1 >> 4) & 0x7; 159 pllvals->N2 = ((pll1 >> 21) & 0x18) | 160 ((pll1 >> 19) & 0x7); 161 } 162 } 163 } 164 } 165 166 int 167 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 168 struct nouveau_pll_vals *pllvals) 169 { 170 struct nouveau_drm *drm = nouveau_drm(dev); 171 struct nouveau_device *device = nv_device(drm->device); 172 struct nouveau_bios *bios = nouveau_bios(device); 173 uint32_t reg1, pll1, pll2 = 0; 174 struct nvbios_pll pll_lim; 175 int ret; 176 177 ret = nvbios_pll_parse(bios, plltype, &pll_lim); 178 if (ret || !(reg1 = pll_lim.reg)) 179 return -ENOENT; 180 181 pll1 = nv_rd32(device, reg1); 182 if (reg1 <= 0x405c) 183 pll2 = nv_rd32(device, reg1 + 4); 184 else if (nv_two_reg_pll(dev)) { 185 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 186 187 pll2 = nv_rd32(device, reg2); 188 } 189 190 if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 191 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 192 193 /* check whether vpll has been forced into single stage mode */ 194 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { 195 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) 196 pll2 = 0; 197 } else 198 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) 199 pll2 = 0; 200 } 201 202 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 203 pllvals->refclk = pll_lim.refclk; 204 return 0; 205 } 206 207 int 208 nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv) 209 { 210 /* Avoid divide by zero if called at an inappropriate time */ 211 if (!pv->M1 || !pv->M2) 212 return 0; 213 214 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 215 } 216 217 int 218 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) 219 { 220 struct nouveau_pll_vals pllvals; 221 int ret; 222 223 if (plltype == PLL_MEMORY && 224 (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { 225 uint32_t mpllP; 226 227 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); 228 if (!mpllP) 229 mpllP = 4; 230 231 return 400000 / mpllP; 232 } else 233 if (plltype == PLL_MEMORY && 234 (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { 235 uint32_t clock; 236 237 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); 238 return clock; 239 } 240 241 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); 242 if (ret) 243 return ret; 244 245 return nouveau_hw_pllvals_to_clk(&pllvals); 246 } 247 248 static void 249 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) 250 { 251 /* the vpll on an unused head can come up with a random value, way 252 * beyond the pll limits. for some reason this causes the chip to 253 * lock up when reading the dac palette regs, so set a valid pll here 254 * when such a condition detected. only seen on nv11 to date 255 */ 256 257 struct nouveau_drm *drm = nouveau_drm(dev); 258 struct nouveau_device *device = nv_device(drm->device); 259 struct nouveau_clock *clk = nouveau_clock(device); 260 struct nouveau_bios *bios = nouveau_bios(device); 261 struct nvbios_pll pll_lim; 262 struct nouveau_pll_vals pv; 263 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 264 265 if (nvbios_pll_parse(bios, pll, &pll_lim)) 266 return; 267 nouveau_hw_get_pllvals(dev, pll, &pv); 268 269 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && 270 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && 271 pv.log2P <= pll_lim.max_p) 272 return; 273 274 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); 275 276 /* set lowest clock within static limits */ 277 pv.M1 = pll_lim.vco1.max_m; 278 pv.N1 = pll_lim.vco1.min_n; 279 pv.log2P = pll_lim.max_p_usable; 280 clk->pll_prog(clk, pll_lim.reg, &pv); 281 } 282 283 /* 284 * vga font save/restore 285 */ 286 287 static void nouveau_vga_font_io(struct drm_device *dev, 288 void __iomem *iovram, 289 bool save, unsigned plane) 290 { 291 unsigned i; 292 293 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); 294 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); 295 for (i = 0; i < 16384; i++) { 296 if (save) { 297 nv04_display(dev)->saved_vga_font[plane][i] = 298 ioread32_native(iovram + i * 4); 299 } else { 300 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], 301 iovram + i * 4); 302 } 303 } 304 } 305 306 void 307 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 308 { 309 struct nouveau_drm *drm = nouveau_drm(dev); 310 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 311 bool graphicsmode; 312 unsigned plane; 313 void __iomem *iovram; 314 315 if (nv_two_heads(dev)) 316 NVSetOwner(dev, 0); 317 318 NVSetEnablePalette(dev, 0, true); 319 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; 320 NVSetEnablePalette(dev, 0, false); 321 322 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 323 return; 324 325 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 326 327 /* map first 64KiB of VRAM, holds VGA fonts etc */ 328 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); 329 if (!iovram) { 330 NV_ERROR(drm, "Failed to map VRAM, " 331 "cannot save/restore VGA fonts.\n"); 332 return; 333 } 334 335 if (nv_two_heads(dev)) 336 NVBlankScreen(dev, 1, true); 337 NVBlankScreen(dev, 0, true); 338 339 /* save control regs */ 340 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); 341 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); 342 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); 343 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); 344 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); 345 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); 346 347 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); 348 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); 349 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); 350 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); 351 352 /* store font in planes 0..3 */ 353 for (plane = 0; plane < 4; plane++) 354 nouveau_vga_font_io(dev, iovram, save, plane); 355 356 /* restore control regs */ 357 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); 358 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); 359 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); 360 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); 361 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); 362 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); 363 364 if (nv_two_heads(dev)) 365 NVBlankScreen(dev, 1, false); 366 NVBlankScreen(dev, 0, false); 367 368 iounmap(iovram); 369 } 370 371 /* 372 * mode state save/load 373 */ 374 375 static void 376 rd_cio_state(struct drm_device *dev, int head, 377 struct nv04_crtc_reg *crtcstate, int index) 378 { 379 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 380 } 381 382 static void 383 wr_cio_state(struct drm_device *dev, int head, 384 struct nv04_crtc_reg *crtcstate, int index) 385 { 386 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); 387 } 388 389 static void 390 nv_save_state_ramdac(struct drm_device *dev, int head, 391 struct nv04_mode_state *state) 392 { 393 struct nouveau_drm *drm = nouveau_drm(dev); 394 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 395 int i; 396 397 if (nv_device(drm->device)->card_type >= NV_10) 398 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 399 400 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); 401 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 402 if (nv_two_heads(dev)) 403 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 404 if (nv_device(drm->device)->chipset == 0x11) 405 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 406 407 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 408 409 if (nv_gf4_disp_arch(dev)) 410 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 411 if (nv_device(drm->device)->chipset >= 0x30) 412 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 413 414 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 415 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); 416 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); 417 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); 418 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); 419 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); 420 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); 421 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); 422 423 for (i = 0; i < 7; i++) { 424 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 425 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); 426 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); 427 } 428 429 if (nv_gf4_disp_arch(dev)) { 430 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); 431 for (i = 0; i < 3; i++) { 432 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); 433 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); 434 } 435 } 436 437 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 438 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); 439 if (!nv_gf4_disp_arch(dev) && head == 0) { 440 /* early chips don't allow access to PRAMDAC_TMDS_* without 441 * the head A FPCLK on (nv11 even locks up) */ 442 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & 443 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); 444 } 445 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); 446 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); 447 448 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); 449 450 if (nv_gf4_disp_arch(dev)) 451 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 452 453 if (nv_device(drm->device)->card_type == NV_40) { 454 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 455 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 456 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 457 458 for (i = 0; i < 38; i++) 459 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, 460 NV_PRAMDAC_CTV + 4*i); 461 } 462 } 463 464 static void 465 nv_load_state_ramdac(struct drm_device *dev, int head, 466 struct nv04_mode_state *state) 467 { 468 struct nouveau_drm *drm = nouveau_drm(dev); 469 struct nouveau_clock *clk = nouveau_clock(drm->device); 470 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 471 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 472 int i; 473 474 if (nv_device(drm->device)->card_type >= NV_10) 475 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 476 477 clk->pll_prog(clk, pllreg, ®p->pllvals); 478 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 479 if (nv_two_heads(dev)) 480 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 481 if (nv_device(drm->device)->chipset == 0x11) 482 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 483 484 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 485 486 if (nv_gf4_disp_arch(dev)) 487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 488 if (nv_device(drm->device)->chipset >= 0x30) 489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 490 491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); 493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); 494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); 495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); 496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); 497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); 498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); 499 500 for (i = 0; i < 7; i++) { 501 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 502 503 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); 504 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); 505 } 506 507 if (nv_gf4_disp_arch(dev)) { 508 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); 509 for (i = 0; i < 3; i++) { 510 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); 511 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); 512 } 513 } 514 515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); 516 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); 517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); 518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); 519 520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); 521 522 if (nv_gf4_disp_arch(dev)) 523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 524 525 if (nv_device(drm->device)->card_type == NV_40) { 526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 529 530 for (i = 0; i < 38; i++) 531 NVWriteRAMDAC(dev, head, 532 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); 533 } 534 } 535 536 static void 537 nv_save_state_vga(struct drm_device *dev, int head, 538 struct nv04_mode_state *state) 539 { 540 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 541 int i; 542 543 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); 544 545 for (i = 0; i < 25; i++) 546 rd_cio_state(dev, head, regp, i); 547 548 NVSetEnablePalette(dev, head, true); 549 for (i = 0; i < 21; i++) 550 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); 551 NVSetEnablePalette(dev, head, false); 552 553 for (i = 0; i < 9; i++) 554 regp->Graphics[i] = NVReadVgaGr(dev, head, i); 555 556 for (i = 0; i < 5; i++) 557 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); 558 } 559 560 static void 561 nv_load_state_vga(struct drm_device *dev, int head, 562 struct nv04_mode_state *state) 563 { 564 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 565 int i; 566 567 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); 568 569 for (i = 0; i < 5; i++) 570 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); 571 572 nv_lock_vga_crtc_base(dev, head, false); 573 for (i = 0; i < 25; i++) 574 wr_cio_state(dev, head, regp, i); 575 nv_lock_vga_crtc_base(dev, head, true); 576 577 for (i = 0; i < 9; i++) 578 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); 579 580 NVSetEnablePalette(dev, head, true); 581 for (i = 0; i < 21; i++) 582 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); 583 NVSetEnablePalette(dev, head, false); 584 } 585 586 static void 587 nv_save_state_ext(struct drm_device *dev, int head, 588 struct nv04_mode_state *state) 589 { 590 struct nouveau_drm *drm = nouveau_drm(dev); 591 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 592 int i; 593 594 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 595 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 596 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 597 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 598 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 599 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 600 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 601 602 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 603 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 604 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 605 606 if (nv_device(drm->device)->card_type >= NV_20) 607 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 608 609 if (nv_device(drm->device)->card_type >= NV_30) 610 rd_cio_state(dev, head, regp, 0x9f); 611 612 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 613 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 614 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 615 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 616 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 617 618 if (nv_device(drm->device)->card_type >= NV_10) { 619 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 620 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 621 622 if (nv_device(drm->device)->card_type >= NV_30) 623 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 624 625 if (nv_device(drm->device)->card_type == NV_40) 626 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 627 628 if (nv_two_heads(dev)) 629 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); 630 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); 631 } 632 633 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); 634 635 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 636 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 637 if (nv_device(drm->device)->card_type >= NV_10) { 638 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 639 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 640 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 641 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 642 } 643 /* NV11 and NV20 don't have this, they stop at 0x52. */ 644 if (nv_gf4_disp_arch(dev)) { 645 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); 646 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); 647 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); 648 649 for (i = 0; i < 0x10; i++) 650 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); 651 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); 652 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); 653 654 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); 655 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); 656 } 657 658 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); 659 } 660 661 static void 662 nv_load_state_ext(struct drm_device *dev, int head, 663 struct nv04_mode_state *state) 664 { 665 struct nouveau_drm *drm = nouveau_drm(dev); 666 struct nouveau_device *device = nv_device(drm->device); 667 struct nouveau_timer *ptimer = nouveau_timer(device); 668 struct nouveau_fb *pfb = nouveau_fb(device); 669 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 670 uint32_t reg900; 671 int i; 672 673 if (nv_device(drm->device)->card_type >= NV_10) { 674 if (nv_two_heads(dev)) 675 /* setting ENGINE_CTRL (EC) *must* come before 676 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 677 * EC that should not be overwritten by writing stale EC 678 */ 679 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 680 681 nv_wr32(device, NV_PVIDEO_STOP, 1); 682 nv_wr32(device, NV_PVIDEO_INTR_EN, 0); 683 nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); 684 nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); 685 nv_wr32(device, NV_PVIDEO_LIMIT(0), pfb->ram->size - 1); 686 nv_wr32(device, NV_PVIDEO_LIMIT(1), pfb->ram->size - 1); 687 nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1); 688 nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1); 689 nv_wr32(device, NV_PBUS_POWERCTRL_2, 0); 690 691 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 692 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 693 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 694 695 if (nv_device(drm->device)->card_type >= NV_30) 696 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 697 698 if (nv_device(drm->device)->card_type == NV_40) { 699 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 700 701 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 702 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) 703 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); 704 else 705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); 706 } 707 } 708 709 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); 710 711 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 712 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 713 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 714 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 716 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 717 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 718 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 720 721 if (nv_device(drm->device)->card_type >= NV_20) 722 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 723 724 if (nv_device(drm->device)->card_type >= NV_30) 725 wr_cio_state(dev, head, regp, 0x9f); 726 727 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 731 if (nv_device(drm->device)->card_type == NV_40) 732 nv_fix_nv40_hw_cursor(dev, head); 733 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 734 735 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 737 if (nv_device(drm->device)->card_type >= NV_10) { 738 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 739 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 740 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 741 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 742 } 743 /* NV11 and NV20 stop at 0x52. */ 744 if (nv_gf4_disp_arch(dev)) { 745 if (nv_device(drm->device)->card_type < NV_20) { 746 /* Not waiting for vertical retrace before modifying 747 CRE_53/CRE_54 causes lockups. */ 748 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); 749 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); 750 } 751 752 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 753 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 754 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 755 756 for (i = 0; i < 0x10; i++) 757 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); 758 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); 759 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); 760 761 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); 762 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); 763 } 764 765 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); 766 } 767 768 static void 769 nv_save_state_palette(struct drm_device *dev, int head, 770 struct nv04_mode_state *state) 771 { 772 struct nouveau_device *device = nouveau_dev(dev); 773 int head_offset = head * NV_PRMDIO_SIZE, i; 774 775 nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 776 NV_PRMDIO_PIXEL_MASK_MASK); 777 nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 778 779 for (i = 0; i < 768; i++) { 780 state->crtc_reg[head].DAC[i] = nv_rd08(device, 781 NV_PRMDIO_PALETTE_DATA + head_offset); 782 } 783 784 NVSetEnablePalette(dev, head, false); 785 } 786 787 void 788 nouveau_hw_load_state_palette(struct drm_device *dev, int head, 789 struct nv04_mode_state *state) 790 { 791 struct nouveau_device *device = nouveau_dev(dev); 792 int head_offset = head * NV_PRMDIO_SIZE, i; 793 794 nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 795 NV_PRMDIO_PIXEL_MASK_MASK); 796 nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 797 798 for (i = 0; i < 768; i++) { 799 nv_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, 800 state->crtc_reg[head].DAC[i]); 801 } 802 803 NVSetEnablePalette(dev, head, false); 804 } 805 806 void nouveau_hw_save_state(struct drm_device *dev, int head, 807 struct nv04_mode_state *state) 808 { 809 struct nouveau_drm *drm = nouveau_drm(dev); 810 811 if (nv_device(drm->device)->chipset == 0x11) 812 /* NB: no attempt is made to restore the bad pll later on */ 813 nouveau_hw_fix_bad_vpll(dev, head); 814 nv_save_state_ramdac(dev, head, state); 815 nv_save_state_vga(dev, head, state); 816 nv_save_state_palette(dev, head, state); 817 nv_save_state_ext(dev, head, state); 818 } 819 820 void nouveau_hw_load_state(struct drm_device *dev, int head, 821 struct nv04_mode_state *state) 822 { 823 NVVgaProtect(dev, head, true); 824 nv_load_state_ramdac(dev, head, state); 825 nv_load_state_ext(dev, head, state); 826 nouveau_hw_load_state_palette(dev, head, state); 827 nv_load_state_vga(dev, head, state); 828 NVVgaProtect(dev, head, false); 829 } 830