1b7019ac5SIlia Mirkin // SPDX-License-Identifier: MIT
21a646342SBen Skeggs #include <drm/drm_mode.h>
34dc28134SBen Skeggs #include "nouveau_drv.h"
41a646342SBen Skeggs #include "nouveau_reg.h"
51a646342SBen Skeggs #include "nouveau_crtc.h"
61a646342SBen Skeggs #include "hw.h"
71a646342SBen Skeggs 
81a646342SBen Skeggs static void
nv04_cursor_show(struct nouveau_crtc * nv_crtc,bool update)91a646342SBen Skeggs nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
101a646342SBen Skeggs {
111a646342SBen Skeggs 	nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
121a646342SBen Skeggs }
131a646342SBen Skeggs 
141a646342SBen Skeggs static void
nv04_cursor_hide(struct nouveau_crtc * nv_crtc,bool update)151a646342SBen Skeggs nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
161a646342SBen Skeggs {
171a646342SBen Skeggs 	nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
181a646342SBen Skeggs }
191a646342SBen Skeggs 
201a646342SBen Skeggs static void
nv04_cursor_set_pos(struct nouveau_crtc * nv_crtc,int x,int y)211a646342SBen Skeggs nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
221a646342SBen Skeggs {
231a646342SBen Skeggs 	nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
241a646342SBen Skeggs 	NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
251a646342SBen Skeggs 		      NV_PRAMDAC_CU_START_POS,
261a646342SBen Skeggs 		      XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
271a646342SBen Skeggs 		      XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
281a646342SBen Skeggs }
291a646342SBen Skeggs 
301a646342SBen Skeggs static void
crtc_wr_cio_state(struct drm_crtc * crtc,struct nv04_crtc_reg * crtcstate,int index)311a646342SBen Skeggs crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
321a646342SBen Skeggs {
331a646342SBen Skeggs 	NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
341a646342SBen Skeggs 		       crtcstate->CRTC[index]);
351a646342SBen Skeggs }
361a646342SBen Skeggs 
371a646342SBen Skeggs static void
nv04_cursor_set_offset(struct nouveau_crtc * nv_crtc,uint32_t offset)381a646342SBen Skeggs nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
391a646342SBen Skeggs {
401a646342SBen Skeggs 	struct drm_device *dev = nv_crtc->base.dev;
411a646342SBen Skeggs 	struct nouveau_drm *drm = nouveau_drm(dev);
421a646342SBen Skeggs 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
431a646342SBen Skeggs 	struct drm_crtc *crtc = &nv_crtc->base;
441a646342SBen Skeggs 
451a646342SBen Skeggs 	regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
461a646342SBen Skeggs 		MASK(NV_CIO_CRE_HCUR_ASI) |
471a646342SBen Skeggs 		XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
481a646342SBen Skeggs 	regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
491a646342SBen Skeggs 		XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
501a646342SBen Skeggs 	if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
511a646342SBen Skeggs 		regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
521a646342SBen Skeggs 			MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
531a646342SBen Skeggs 	regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
541a646342SBen Skeggs 
551a646342SBen Skeggs 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
561a646342SBen Skeggs 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
571a646342SBen Skeggs 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
581167c6bcSBen Skeggs 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
591a646342SBen Skeggs 		nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
601a646342SBen Skeggs }
611a646342SBen Skeggs 
621a646342SBen Skeggs int
nv04_cursor_init(struct nouveau_crtc * crtc)631a646342SBen Skeggs nv04_cursor_init(struct nouveau_crtc *crtc)
641a646342SBen Skeggs {
651a646342SBen Skeggs 	crtc->cursor.set_offset = nv04_cursor_set_offset;
661a646342SBen Skeggs 	crtc->cursor.set_pos = nv04_cursor_set_pos;
671a646342SBen Skeggs 	crtc->cursor.hide = nv04_cursor_hide;
681a646342SBen Skeggs 	crtc->cursor.show = nv04_cursor_show;
691a646342SBen Skeggs 	return 0;
701a646342SBen Skeggs }
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