1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "nouveau_drv.h" 31 #include "nouveau_reg.h" 32 #include "nouveau_ttm.h" 33 #include "nouveau_bo.h" 34 #include "nouveau_gem.h" 35 #include "nouveau_encoder.h" 36 #include "nouveau_connector.h" 37 #include "nouveau_crtc.h" 38 #include "hw.h" 39 #include "nvreg.h" 40 #include "disp.h" 41 #include "nouveau_dma.h" 42 43 #include <subdev/bios/pll.h> 44 #include <subdev/clk.h> 45 46 #include <nvif/push006c.h> 47 48 #include <nvif/event.h> 49 #include <nvif/cl0046.h> 50 51 static int 52 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 53 struct drm_framebuffer *old_fb); 54 55 static void 56 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 57 { 58 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 59 crtcstate->CRTC[index]); 60 } 61 62 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 63 { 64 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 65 struct drm_device *dev = crtc->dev; 66 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 67 68 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 69 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 70 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 71 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 72 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 73 } 74 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 75 } 76 77 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 78 { 79 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 80 struct drm_device *dev = crtc->dev; 81 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 82 83 nv_crtc->sharpness = level; 84 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 85 level += 0x40; 86 regp->ramdac_634 = level; 87 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 88 } 89 90 #define PLLSEL_VPLL1_MASK \ 91 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 92 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 93 #define PLLSEL_VPLL2_MASK \ 94 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 95 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 96 #define PLLSEL_TV_MASK \ 97 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 98 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 99 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 100 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 101 102 /* NV4x 0x40.. pll notes: 103 * gpu pll: 0x4000 + 0x4004 104 * ?gpu? pll: 0x4008 + 0x400c 105 * vpll1: 0x4010 + 0x4014 106 * vpll2: 0x4018 + 0x401c 107 * mpll: 0x4020 + 0x4024 108 * mpll: 0x4038 + 0x403c 109 * 110 * the first register of each pair has some unknown details: 111 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 112 * bits 20-23: (mpll) something to do with post divider? 113 * bits 28-31: related to single stage mode? (bit 8/12) 114 */ 115 116 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 117 { 118 struct drm_device *dev = crtc->dev; 119 struct nouveau_drm *drm = nouveau_drm(dev); 120 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 121 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 122 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 123 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 124 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 125 struct nvkm_pll_vals *pv = ®p->pllvals; 126 struct nvbios_pll pll_lim; 127 128 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 129 &pll_lim)) 130 return; 131 132 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 133 pv->NM2 = 0; 134 135 /* for newer nv4x the blob uses only the first stage of the vpll below a 136 * certain clock. for a certain nv4b this is 150MHz. since the max 137 * output frequency of the first stage for this card is 300MHz, it is 138 * assumed the threshold is given by vco1 maxfreq/2 139 */ 140 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 141 * not 8, others unknown), the blob always uses both plls. no problem 142 * has yet been observed in allowing the use a single stage pll on all 143 * nv43 however. the behaviour of single stage use is untested on nv40 144 */ 145 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 146 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 147 148 149 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 150 return; 151 152 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 153 154 /* The blob uses this always, so let's do the same */ 155 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 156 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 157 /* again nv40 and some nv43 act more like nv3x as described above */ 158 if (drm->client.device.info.chipset < 0x41) 159 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 160 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 161 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 162 163 if (pv->NM2) 164 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 165 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 166 else 167 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 168 pv->N1, pv->M1, pv->log2P); 169 170 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 171 } 172 173 static void 174 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 175 { 176 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 177 struct drm_device *dev = crtc->dev; 178 struct nouveau_drm *drm = nouveau_drm(dev); 179 unsigned char seq1 = 0, crtc17 = 0; 180 unsigned char crtc1A; 181 182 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 183 nv_crtc->index); 184 185 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 186 return; 187 188 nv_crtc->last_dpms = mode; 189 190 if (nv_two_heads(dev)) 191 NVSetOwner(dev, nv_crtc->index); 192 193 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 194 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 195 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 196 switch (mode) { 197 case DRM_MODE_DPMS_STANDBY: 198 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 199 seq1 = 0x20; 200 crtc17 = 0x80; 201 crtc1A |= 0x80; 202 break; 203 case DRM_MODE_DPMS_SUSPEND: 204 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 205 seq1 = 0x20; 206 crtc17 = 0x80; 207 crtc1A |= 0x40; 208 break; 209 case DRM_MODE_DPMS_OFF: 210 /* Screen: Off; HSync: Off, VSync: Off */ 211 seq1 = 0x20; 212 crtc17 = 0x00; 213 crtc1A |= 0xC0; 214 break; 215 case DRM_MODE_DPMS_ON: 216 default: 217 /* Screen: On; HSync: On, VSync: On */ 218 seq1 = 0x00; 219 crtc17 = 0x80; 220 break; 221 } 222 223 NVVgaSeqReset(dev, nv_crtc->index, true); 224 /* Each head has it's own sequencer, so we can turn it off when we want */ 225 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 226 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 227 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 228 mdelay(10); 229 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 230 NVVgaSeqReset(dev, nv_crtc->index, false); 231 232 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 233 } 234 235 static void 236 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 237 { 238 struct drm_device *dev = crtc->dev; 239 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 240 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 241 struct drm_framebuffer *fb = crtc->primary->fb; 242 243 /* Calculate our timings */ 244 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 245 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 246 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 247 int horizTotal = (mode->crtc_htotal >> 3) - 5; 248 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 249 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 250 int vertDisplay = mode->crtc_vdisplay - 1; 251 int vertStart = mode->crtc_vsync_start - 1; 252 int vertEnd = mode->crtc_vsync_end - 1; 253 int vertTotal = mode->crtc_vtotal - 2; 254 int vertBlankStart = mode->crtc_vdisplay - 1; 255 int vertBlankEnd = mode->crtc_vtotal - 1; 256 257 struct drm_encoder *encoder; 258 bool fp_output = false; 259 260 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 261 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 262 263 if (encoder->crtc == crtc && 264 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 265 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 266 fp_output = true; 267 } 268 269 if (fp_output) { 270 vertStart = vertTotal - 3; 271 vertEnd = vertTotal - 2; 272 vertBlankStart = vertStart; 273 horizStart = horizTotal - 5; 274 horizEnd = horizTotal - 2; 275 horizBlankEnd = horizTotal + 4; 276 #if 0 277 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 278 /* This reportedly works around some video overlay bandwidth problems */ 279 horizTotal += 2; 280 #endif 281 } 282 283 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 284 vertTotal |= 1; 285 286 #if 0 287 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 288 ErrorF("horizStart: 0x%X \n", horizStart); 289 ErrorF("horizEnd: 0x%X \n", horizEnd); 290 ErrorF("horizTotal: 0x%X \n", horizTotal); 291 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 292 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 293 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 294 ErrorF("vertStart: 0x%X \n", vertStart); 295 ErrorF("vertEnd: 0x%X \n", vertEnd); 296 ErrorF("vertTotal: 0x%X \n", vertTotal); 297 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 298 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 299 #endif 300 301 /* 302 * compute correct Hsync & Vsync polarity 303 */ 304 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 305 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 306 307 regp->MiscOutReg = 0x23; 308 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 309 regp->MiscOutReg |= 0x40; 310 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 311 regp->MiscOutReg |= 0x80; 312 } else { 313 int vdisplay = mode->vdisplay; 314 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 315 vdisplay *= 2; 316 if (mode->vscan > 1) 317 vdisplay *= mode->vscan; 318 if (vdisplay < 400) 319 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 320 else if (vdisplay < 480) 321 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 322 else if (vdisplay < 768) 323 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 324 else 325 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 326 } 327 328 /* 329 * Time Sequencer 330 */ 331 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 332 /* 0x20 disables the sequencer */ 333 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 334 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 335 else 336 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 337 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 338 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 339 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 340 341 /* 342 * CRTC 343 */ 344 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 345 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 346 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 347 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 348 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 349 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 350 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 351 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 352 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 353 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 354 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 355 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 356 (1 << 4) | 357 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 358 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 359 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 360 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 361 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 362 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 363 1 << 6 | 364 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 365 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 366 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 367 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 368 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 369 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 370 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 371 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 372 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 373 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 374 /* framebuffer can be larger than crtc scanout area. */ 375 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 376 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 377 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 378 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 379 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 380 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 381 382 /* 383 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 384 */ 385 386 /* framebuffer can be larger than crtc scanout area. */ 387 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 388 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 389 regp->CRTC[NV_CIO_CRE_42] = 390 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 391 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 392 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 393 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 394 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 395 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 396 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 397 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 398 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 399 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 400 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 401 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 402 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 403 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 404 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 405 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 406 407 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 408 horizTotal = (horizTotal >> 1) & ~1; 409 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 410 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 411 } else 412 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 413 414 /* 415 * Graphics Display Controller 416 */ 417 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 418 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 419 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 420 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 421 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 422 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 423 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 424 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 425 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 426 427 regp->Attribute[0] = 0x00; /* standard colormap translation */ 428 regp->Attribute[1] = 0x01; 429 regp->Attribute[2] = 0x02; 430 regp->Attribute[3] = 0x03; 431 regp->Attribute[4] = 0x04; 432 regp->Attribute[5] = 0x05; 433 regp->Attribute[6] = 0x06; 434 regp->Attribute[7] = 0x07; 435 regp->Attribute[8] = 0x08; 436 regp->Attribute[9] = 0x09; 437 regp->Attribute[10] = 0x0A; 438 regp->Attribute[11] = 0x0B; 439 regp->Attribute[12] = 0x0C; 440 regp->Attribute[13] = 0x0D; 441 regp->Attribute[14] = 0x0E; 442 regp->Attribute[15] = 0x0F; 443 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 444 /* Non-vga */ 445 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 446 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 447 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 448 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 449 } 450 451 /** 452 * Sets up registers for the given mode/adjusted_mode pair. 453 * 454 * The clocks, CRTCs and outputs attached to this CRTC must be off. 455 * 456 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 457 * be easily turned on/off after this. 458 */ 459 static void 460 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 461 { 462 struct drm_device *dev = crtc->dev; 463 struct nouveau_drm *drm = nouveau_drm(dev); 464 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 465 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 466 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 467 const struct drm_framebuffer *fb = crtc->primary->fb; 468 struct drm_encoder *encoder; 469 bool lvds_output = false, tmds_output = false, tv_output = false, 470 off_chip_digital = false; 471 472 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 473 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 474 bool digital = false; 475 476 if (encoder->crtc != crtc) 477 continue; 478 479 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 480 digital = lvds_output = true; 481 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 482 tv_output = true; 483 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 484 digital = tmds_output = true; 485 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 486 off_chip_digital = true; 487 } 488 489 /* Registers not directly related to the (s)vga mode */ 490 491 /* What is the meaning of this register? */ 492 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 493 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 494 495 regp->crtc_eng_ctrl = 0; 496 /* Except for rare conditions I2C is enabled on the primary crtc */ 497 if (nv_crtc->index == 0) 498 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 499 #if 0 500 /* Set overlay to desired crtc. */ 501 if (dev->overlayAdaptor) { 502 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 503 if (pPriv->overlayCRTC == nv_crtc->index) 504 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 505 } 506 #endif 507 508 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 509 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 510 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 511 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 512 if (drm->client.device.info.chipset >= 0x11) 513 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 514 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 515 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 516 517 /* Unblock some timings */ 518 regp->CRTC[NV_CIO_CRE_53] = 0; 519 regp->CRTC[NV_CIO_CRE_54] = 0; 520 521 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 522 if (lvds_output) 523 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 524 else if (tmds_output) 525 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 526 else 527 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 528 529 /* These values seem to vary */ 530 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 531 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 532 533 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 534 535 /* probably a scratch reg, but kept for cargo-cult purposes: 536 * bit0: crtc0?, head A 537 * bit6: lvds, head A 538 * bit7: (only in X), head A 539 */ 540 if (nv_crtc->index == 0) 541 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 542 543 /* The blob seems to take the current value from crtc 0, add 4 to that 544 * and reuse the old value for crtc 1 */ 545 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 546 if (!nv_crtc->index) 547 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 548 549 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 550 * 1 << 30 on 0x60.830), for no apparent reason */ 551 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 552 553 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 554 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 555 556 regp->crtc_830 = mode->crtc_vdisplay - 3; 557 regp->crtc_834 = mode->crtc_vdisplay - 1; 558 559 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 560 /* This is what the blob does */ 561 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 562 563 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 564 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 565 566 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 567 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 568 else 569 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 570 571 /* Some misc regs */ 572 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 573 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 574 regp->CRTC[NV_CIO_CRE_86] = 0x1; 575 } 576 577 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; 578 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 579 if (lvds_output || tmds_output || tv_output) 580 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 581 582 /* Generic PRAMDAC regs */ 583 584 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 585 /* Only bit that bios and blob set. */ 586 regp->nv10_cursync = (1 << 25); 587 588 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 589 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 590 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 591 if (fb->format->depth == 16) 592 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 593 if (drm->client.device.info.chipset >= 0x11) 594 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 595 596 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 597 regp->tv_setup = 0; 598 599 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 600 601 /* Some values the blob sets */ 602 regp->ramdac_8c0 = 0x100; 603 regp->ramdac_a20 = 0x0; 604 regp->ramdac_a24 = 0xfffff; 605 regp->ramdac_a34 = 0x1; 606 } 607 608 static int 609 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 610 { 611 struct nv04_display *disp = nv04_display(crtc->dev); 612 struct drm_framebuffer *fb = crtc->primary->fb; 613 struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]); 614 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 615 int ret; 616 617 ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, false); 618 if (ret == 0) { 619 if (disp->image[nv_crtc->index]) 620 nouveau_bo_unpin(disp->image[nv_crtc->index]); 621 nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]); 622 } 623 624 return ret; 625 } 626 627 /** 628 * Sets up registers for the given mode/adjusted_mode pair. 629 * 630 * The clocks, CRTCs and outputs attached to this CRTC must be off. 631 * 632 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 633 * be easily turned on/off after this. 634 */ 635 static int 636 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 637 struct drm_display_mode *adjusted_mode, 638 int x, int y, struct drm_framebuffer *old_fb) 639 { 640 struct drm_device *dev = crtc->dev; 641 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 642 struct nouveau_drm *drm = nouveau_drm(dev); 643 int ret; 644 645 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 646 drm_mode_debug_printmodeline(adjusted_mode); 647 648 ret = nv_crtc_swap_fbs(crtc, old_fb); 649 if (ret) 650 return ret; 651 652 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 653 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 654 655 nv_crtc_mode_set_vga(crtc, adjusted_mode); 656 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 657 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 659 nv_crtc_mode_set_regs(crtc, adjusted_mode); 660 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 661 return 0; 662 } 663 664 static void nv_crtc_save(struct drm_crtc *crtc) 665 { 666 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 667 struct drm_device *dev = crtc->dev; 668 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 669 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 670 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 671 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 672 673 if (nv_two_heads(crtc->dev)) 674 NVSetOwner(crtc->dev, nv_crtc->index); 675 676 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 677 678 /* init some state to saved value */ 679 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 680 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 681 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 682 crtc_state->gpio_ext = crtc_saved->gpio_ext; 683 } 684 685 static void nv_crtc_restore(struct drm_crtc *crtc) 686 { 687 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 688 struct drm_device *dev = crtc->dev; 689 int head = nv_crtc->index; 690 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 691 692 if (nv_two_heads(crtc->dev)) 693 NVSetOwner(crtc->dev, head); 694 695 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 696 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 697 698 nv_crtc->last_dpms = NV_DPMS_CLEARED; 699 } 700 701 static void nv_crtc_prepare(struct drm_crtc *crtc) 702 { 703 struct drm_device *dev = crtc->dev; 704 struct nouveau_drm *drm = nouveau_drm(dev); 705 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 706 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 707 708 if (nv_two_heads(dev)) 709 NVSetOwner(dev, nv_crtc->index); 710 711 drm_crtc_vblank_off(crtc); 712 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 713 714 NVBlankScreen(dev, nv_crtc->index, true); 715 716 /* Some more preparation. */ 717 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 718 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 719 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 720 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 721 } 722 } 723 724 static void nv_crtc_commit(struct drm_crtc *crtc) 725 { 726 struct drm_device *dev = crtc->dev; 727 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 728 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 729 730 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 731 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 732 733 #ifdef __BIG_ENDIAN 734 /* turn on LFB swapping */ 735 { 736 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 737 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 738 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 739 } 740 #endif 741 742 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 743 drm_crtc_vblank_on(crtc); 744 } 745 746 static void nv_crtc_destroy(struct drm_crtc *crtc) 747 { 748 struct nv04_display *disp = nv04_display(crtc->dev); 749 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 750 751 if (!nv_crtc) 752 return; 753 754 drm_crtc_cleanup(crtc); 755 756 if (disp->image[nv_crtc->index]) 757 nouveau_bo_unpin(disp->image[nv_crtc->index]); 758 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 759 760 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 761 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 762 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 763 nvif_event_dtor(&nv_crtc->vblank); 764 nvif_head_dtor(&nv_crtc->head); 765 kfree(nv_crtc); 766 } 767 768 static void 769 nv_crtc_gamma_load(struct drm_crtc *crtc) 770 { 771 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 772 struct drm_device *dev = nv_crtc->base.dev; 773 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 774 u16 *r, *g, *b; 775 int i; 776 777 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 778 r = crtc->gamma_store; 779 g = r + crtc->gamma_size; 780 b = g + crtc->gamma_size; 781 782 for (i = 0; i < 256; i++) { 783 rgbs[i].r = *r++ >> 8; 784 rgbs[i].g = *g++ >> 8; 785 rgbs[i].b = *b++ >> 8; 786 } 787 788 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 789 } 790 791 static void 792 nv_crtc_disable(struct drm_crtc *crtc) 793 { 794 struct nv04_display *disp = nv04_display(crtc->dev); 795 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 796 if (disp->image[nv_crtc->index]) 797 nouveau_bo_unpin(disp->image[nv_crtc->index]); 798 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 799 } 800 801 static int 802 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 803 uint32_t size, 804 struct drm_modeset_acquire_ctx *ctx) 805 { 806 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 807 808 /* We need to know the depth before we upload, but it's possible to 809 * get called before a framebuffer is bound. If this is the case, 810 * mark the lut values as dirty by setting depth==0, and it'll be 811 * uploaded on the first mode_set_base() 812 */ 813 if (!nv_crtc->base.primary->fb) { 814 nv_crtc->lut.depth = 0; 815 return 0; 816 } 817 818 nv_crtc_gamma_load(crtc); 819 820 return 0; 821 } 822 823 static int 824 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 825 struct drm_framebuffer *passed_fb, 826 int x, int y, bool atomic) 827 { 828 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 829 struct drm_device *dev = crtc->dev; 830 struct nouveau_drm *drm = nouveau_drm(dev); 831 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 832 struct nouveau_bo *nvbo; 833 struct drm_framebuffer *drm_fb; 834 int arb_burst, arb_lwm; 835 836 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 837 838 /* no fb bound */ 839 if (!atomic && !crtc->primary->fb) { 840 NV_DEBUG(drm, "No FB bound\n"); 841 return 0; 842 } 843 844 /* If atomic, we want to switch to the fb we were passed, so 845 * now we update pointers to do that. 846 */ 847 if (atomic) { 848 drm_fb = passed_fb; 849 } else { 850 drm_fb = crtc->primary->fb; 851 } 852 853 nvbo = nouveau_gem_object(drm_fb->obj[0]); 854 nv_crtc->fb.offset = nvbo->offset; 855 856 if (nv_crtc->lut.depth != drm_fb->format->depth) { 857 nv_crtc->lut.depth = drm_fb->format->depth; 858 nv_crtc_gamma_load(crtc); 859 } 860 861 /* Update the framebuffer format. */ 862 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 863 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; 864 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 865 if (drm_fb->format->depth == 16) 866 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 867 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 868 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 869 regp->ramdac_gen_ctrl); 870 871 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 872 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 873 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 874 regp->CRTC[NV_CIO_CRE_42] = 875 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 876 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 877 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 878 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 879 880 /* Update the framebuffer location. */ 881 regp->fb_start = nv_crtc->fb.offset & ~3; 882 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); 883 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 884 885 /* Update the arbitration parameters. */ 886 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, 887 &arb_burst, &arb_lwm); 888 889 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 890 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 891 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 893 894 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 895 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 896 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 897 } 898 899 return 0; 900 } 901 902 static int 903 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 904 struct drm_framebuffer *old_fb) 905 { 906 int ret = nv_crtc_swap_fbs(crtc, old_fb); 907 if (ret) 908 return ret; 909 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 910 } 911 912 static int 913 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 914 struct drm_framebuffer *fb, 915 int x, int y, enum mode_set_atomic state) 916 { 917 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 918 } 919 920 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 921 struct nouveau_bo *dst) 922 { 923 int width = nv_cursor_width(dev); 924 uint32_t pixel; 925 int i, j; 926 927 for (i = 0; i < width; i++) { 928 for (j = 0; j < width; j++) { 929 pixel = nouveau_bo_rd32(src, i*64 + j); 930 931 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 932 | (pixel & 0xf80000) >> 9 933 | (pixel & 0xf800) >> 6 934 | (pixel & 0xf8) >> 3); 935 } 936 } 937 } 938 939 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 940 struct nouveau_bo *dst) 941 { 942 uint32_t pixel; 943 int alpha, i; 944 945 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 946 * cursors (though NPM in combination with fp dithering may not work on 947 * nv11, from "nv" driver history) 948 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 949 * blob uses, however we get given PM cursors so we use PM mode 950 */ 951 for (i = 0; i < 64 * 64; i++) { 952 pixel = nouveau_bo_rd32(src, i); 953 954 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 955 * than" shouldn't happen; fix "equal to" case by adding one to 956 * alpha channel (slightly inaccurate, but so is attempting to 957 * get back to NPM images, due to limits of integer precision) 958 */ 959 alpha = pixel >> 24; 960 if (alpha > 0 && alpha < 255) 961 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 962 963 #ifdef __BIG_ENDIAN 964 { 965 struct nouveau_drm *drm = nouveau_drm(dev); 966 967 if (drm->client.device.info.chipset == 0x11) { 968 pixel = ((pixel & 0x000000ff) << 24) | 969 ((pixel & 0x0000ff00) << 8) | 970 ((pixel & 0x00ff0000) >> 8) | 971 ((pixel & 0xff000000) >> 24); 972 } 973 } 974 #endif 975 976 nouveau_bo_wr32(dst, i, pixel); 977 } 978 } 979 980 static int 981 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 982 uint32_t buffer_handle, uint32_t width, uint32_t height) 983 { 984 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 985 struct drm_device *dev = drm->dev; 986 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 987 struct nouveau_bo *cursor = NULL; 988 struct drm_gem_object *gem; 989 int ret = 0; 990 991 if (!buffer_handle) { 992 nv_crtc->cursor.hide(nv_crtc, true); 993 return 0; 994 } 995 996 if (width != 64 || height != 64) 997 return -EINVAL; 998 999 gem = drm_gem_object_lookup(file_priv, buffer_handle); 1000 if (!gem) 1001 return -ENOENT; 1002 cursor = nouveau_gem_object(gem); 1003 1004 ret = nouveau_bo_map(cursor); 1005 if (ret) 1006 goto out; 1007 1008 if (drm->client.device.info.chipset >= 0x11) 1009 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1010 else 1011 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1012 1013 nouveau_bo_unmap(cursor); 1014 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset; 1015 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1016 nv_crtc->cursor.show(nv_crtc, true); 1017 out: 1018 drm_gem_object_put(gem); 1019 return ret; 1020 } 1021 1022 static int 1023 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1024 { 1025 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1026 1027 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1028 return 0; 1029 } 1030 1031 struct nv04_page_flip_state { 1032 struct list_head head; 1033 struct drm_pending_vblank_event *event; 1034 struct drm_crtc *crtc; 1035 int bpp, pitch; 1036 u64 offset; 1037 }; 1038 1039 static int 1040 nv04_finish_page_flip(struct nouveau_channel *chan, 1041 struct nv04_page_flip_state *ps) 1042 { 1043 struct nouveau_fence_chan *fctx = chan->fence; 1044 struct nouveau_drm *drm = chan->drm; 1045 struct drm_device *dev = drm->dev; 1046 struct nv04_page_flip_state *s; 1047 unsigned long flags; 1048 1049 spin_lock_irqsave(&dev->event_lock, flags); 1050 1051 if (list_empty(&fctx->flip)) { 1052 NV_ERROR(drm, "unexpected pageflip\n"); 1053 spin_unlock_irqrestore(&dev->event_lock, flags); 1054 return -EINVAL; 1055 } 1056 1057 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head); 1058 if (s->event) { 1059 drm_crtc_arm_vblank_event(s->crtc, s->event); 1060 } else { 1061 /* Give up ownership of vblank for page-flipped crtc */ 1062 drm_crtc_vblank_put(s->crtc); 1063 } 1064 1065 list_del(&s->head); 1066 if (ps) 1067 *ps = *s; 1068 kfree(s); 1069 1070 spin_unlock_irqrestore(&dev->event_lock, flags); 1071 return 0; 1072 } 1073 1074 int 1075 nv04_flip_complete(struct nvif_event *event, void *argv, u32 argc) 1076 { 1077 struct nv04_display *disp = container_of(event, typeof(*disp), flip); 1078 struct nouveau_drm *drm = disp->drm; 1079 struct nouveau_channel *chan = drm->channel; 1080 struct nv04_page_flip_state state; 1081 1082 if (!nv04_finish_page_flip(chan, &state)) { 1083 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), 1084 state.offset + state.crtc->y * 1085 state.pitch + state.crtc->x * 1086 state.bpp / 8); 1087 } 1088 1089 return NVIF_EVENT_KEEP; 1090 } 1091 1092 static int 1093 nv04_page_flip_emit(struct nouveau_channel *chan, 1094 struct nouveau_bo *old_bo, 1095 struct nouveau_bo *new_bo, 1096 struct nv04_page_flip_state *s, 1097 struct nouveau_fence **pfence) 1098 { 1099 struct nouveau_fence_chan *fctx = chan->fence; 1100 struct nouveau_drm *drm = chan->drm; 1101 struct drm_device *dev = drm->dev; 1102 struct nvif_push *push = chan->chan.push; 1103 unsigned long flags; 1104 int ret; 1105 1106 /* Queue it to the pending list */ 1107 spin_lock_irqsave(&dev->event_lock, flags); 1108 list_add_tail(&s->head, &fctx->flip); 1109 spin_unlock_irqrestore(&dev->event_lock, flags); 1110 1111 /* Synchronize with the old framebuffer */ 1112 ret = nouveau_fence_sync(old_bo, chan, false, false); 1113 if (ret) 1114 goto fail; 1115 1116 /* Emit the pageflip */ 1117 ret = PUSH_WAIT(push, 2); 1118 if (ret) 1119 goto fail; 1120 1121 PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000); 1122 PUSH_KICK(push); 1123 1124 ret = nouveau_fence_new(chan, false, pfence); 1125 if (ret) 1126 goto fail; 1127 1128 return 0; 1129 fail: 1130 spin_lock_irqsave(&dev->event_lock, flags); 1131 list_del(&s->head); 1132 spin_unlock_irqrestore(&dev->event_lock, flags); 1133 return ret; 1134 } 1135 1136 static int 1137 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1138 struct drm_pending_vblank_event *event, u32 flags, 1139 struct drm_modeset_acquire_ctx *ctx) 1140 { 1141 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; 1142 struct drm_device *dev = crtc->dev; 1143 struct nouveau_drm *drm = nouveau_drm(dev); 1144 struct drm_framebuffer *old_fb = crtc->primary->fb; 1145 struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]); 1146 struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]); 1147 struct nv04_page_flip_state *s; 1148 struct nouveau_channel *chan; 1149 struct nouveau_cli *cli; 1150 struct nouveau_fence *fence; 1151 struct nv04_display *dispnv04 = nv04_display(dev); 1152 struct nvif_push *push; 1153 int head = nouveau_crtc(crtc)->index; 1154 int ret; 1155 1156 chan = drm->channel; 1157 if (!chan) 1158 return -ENODEV; 1159 cli = (void *)chan->user.client; 1160 push = chan->chan.push; 1161 1162 s = kzalloc(sizeof(*s), GFP_KERNEL); 1163 if (!s) 1164 return -ENOMEM; 1165 1166 if (new_bo != old_bo) { 1167 ret = nouveau_bo_pin(new_bo, NOUVEAU_GEM_DOMAIN_VRAM, true); 1168 if (ret) 1169 goto fail_free; 1170 } 1171 1172 mutex_lock(&cli->mutex); 1173 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL); 1174 if (ret) 1175 goto fail_unpin; 1176 1177 /* synchronise rendering channel with the kernel's channel */ 1178 ret = nouveau_fence_sync(new_bo, chan, false, true); 1179 if (ret) { 1180 ttm_bo_unreserve(&new_bo->bo); 1181 goto fail_unpin; 1182 } 1183 1184 if (new_bo != old_bo) { 1185 ttm_bo_unreserve(&new_bo->bo); 1186 1187 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL); 1188 if (ret) 1189 goto fail_unpin; 1190 } 1191 1192 /* Initialize a page flip struct */ 1193 *s = (struct nv04_page_flip_state) 1194 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], 1195 new_bo->offset }; 1196 1197 /* Keep vblanks on during flip, for the target crtc of this flip */ 1198 drm_crtc_vblank_get(crtc); 1199 1200 /* Emit a page flip */ 1201 if (swap_interval) { 1202 ret = PUSH_WAIT(push, 8); 1203 if (ret) 1204 goto fail_unreserve; 1205 1206 PUSH_NVSQ(push, NV05F, 0x012c, 0); 1207 PUSH_NVSQ(push, NV05F, 0x0134, head); 1208 PUSH_NVSQ(push, NV05F, 0x0100, 0); 1209 PUSH_NVSQ(push, NV05F, 0x0130, 0); 1210 } 1211 1212 nouveau_bo_ref(new_bo, &dispnv04->image[head]); 1213 1214 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence); 1215 if (ret) 1216 goto fail_unreserve; 1217 mutex_unlock(&cli->mutex); 1218 1219 /* Update the crtc struct and cleanup */ 1220 crtc->primary->fb = fb; 1221 1222 nouveau_bo_fence(old_bo, fence, false); 1223 ttm_bo_unreserve(&old_bo->bo); 1224 if (old_bo != new_bo) 1225 nouveau_bo_unpin(old_bo); 1226 nouveau_fence_unref(&fence); 1227 return 0; 1228 1229 fail_unreserve: 1230 drm_crtc_vblank_put(crtc); 1231 ttm_bo_unreserve(&old_bo->bo); 1232 fail_unpin: 1233 mutex_unlock(&cli->mutex); 1234 if (old_bo != new_bo) 1235 nouveau_bo_unpin(new_bo); 1236 fail_free: 1237 kfree(s); 1238 return ret; 1239 } 1240 1241 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1242 .cursor_set = nv04_crtc_cursor_set, 1243 .cursor_move = nv04_crtc_cursor_move, 1244 .gamma_set = nv_crtc_gamma_set, 1245 .set_config = drm_crtc_helper_set_config, 1246 .page_flip = nv04_crtc_page_flip, 1247 .destroy = nv_crtc_destroy, 1248 .enable_vblank = nouveau_display_vblank_enable, 1249 .disable_vblank = nouveau_display_vblank_disable, 1250 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1251 }; 1252 1253 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1254 .dpms = nv_crtc_dpms, 1255 .prepare = nv_crtc_prepare, 1256 .commit = nv_crtc_commit, 1257 .mode_set = nv_crtc_mode_set, 1258 .mode_set_base = nv04_crtc_mode_set_base, 1259 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1260 .disable = nv_crtc_disable, 1261 .get_scanout_position = nouveau_display_scanoutpos, 1262 }; 1263 1264 static const uint32_t modeset_formats[] = { 1265 DRM_FORMAT_XRGB8888, 1266 DRM_FORMAT_RGB565, 1267 DRM_FORMAT_XRGB1555, 1268 }; 1269 1270 static const struct drm_plane_funcs nv04_primary_plane_funcs = { 1271 DRM_PLANE_NON_ATOMIC_FUNCS, 1272 }; 1273 1274 static int 1275 nv04_crtc_vblank_handler(struct nvif_event *event, void *repv, u32 repc) 1276 { 1277 struct nouveau_crtc *nv_crtc = container_of(event, struct nouveau_crtc, vblank); 1278 1279 drm_crtc_handle_vblank(&nv_crtc->base); 1280 return NVIF_EVENT_KEEP; 1281 } 1282 1283 int 1284 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1285 { 1286 struct nouveau_display *disp = nouveau_display(dev); 1287 struct nouveau_crtc *nv_crtc; 1288 struct drm_plane *primary; 1289 int ret; 1290 1291 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1292 if (!nv_crtc) 1293 return -ENOMEM; 1294 1295 nv_crtc->lut.depth = 0; 1296 1297 nv_crtc->index = crtc_num; 1298 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1299 1300 nv_crtc->save = nv_crtc_save; 1301 nv_crtc->restore = nv_crtc_restore; 1302 1303 primary = __drm_universal_plane_alloc(dev, sizeof(*primary), 0, 0, 1304 &nv04_primary_plane_funcs, 1305 modeset_formats, 1306 ARRAY_SIZE(modeset_formats), NULL, 1307 DRM_PLANE_TYPE_PRIMARY, NULL); 1308 if (IS_ERR(primary)) { 1309 ret = PTR_ERR(primary); 1310 kfree(nv_crtc); 1311 return ret; 1312 } 1313 1314 drm_crtc_init_with_planes(dev, &nv_crtc->base, primary, NULL, 1315 &nv04_crtc_funcs, NULL); 1316 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1317 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1318 1319 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, 1320 NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL, 1321 &nv_crtc->cursor.nvbo); 1322 if (!ret) { 1323 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, 1324 NOUVEAU_GEM_DOMAIN_VRAM, false); 1325 if (!ret) { 1326 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1327 if (ret) 1328 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1329 } 1330 if (ret) 1331 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1332 } 1333 1334 nv04_cursor_init(nv_crtc); 1335 1336 ret = nvif_head_ctor(&disp->disp, nv_crtc->base.name, nv_crtc->index, &nv_crtc->head); 1337 if (ret) 1338 return ret; 1339 1340 return nvif_head_vblank_event_ctor(&nv_crtc->head, "kmsVbl", nv04_crtc_vblank_handler, 1341 false, &nv_crtc->vblank); 1342 } 1343