1 /*
2  * Copyright 1993-2003 NVIDIA, Corporation
3  * Copyright 2006 Dave Airlie
4  * Copyright 2007 Maarten Maathuis
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  */
25 #include <drm/drm_crtc_helper.h>
26 #include <drm/drm_fourcc.h>
27 #include <drm/drm_plane_helper.h>
28 #include <drm/drm_vblank.h>
29 
30 #include "nouveau_drv.h"
31 #include "nouveau_reg.h"
32 #include "nouveau_ttm.h"
33 #include "nouveau_bo.h"
34 #include "nouveau_gem.h"
35 #include "nouveau_encoder.h"
36 #include "nouveau_connector.h"
37 #include "nouveau_crtc.h"
38 #include "hw.h"
39 #include "nvreg.h"
40 #include "nouveau_fbcon.h"
41 #include "disp.h"
42 #include "nouveau_dma.h"
43 
44 #include <subdev/bios/pll.h>
45 #include <subdev/clk.h>
46 
47 static int
48 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
49 			struct drm_framebuffer *old_fb);
50 
51 static void
52 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
53 {
54 	NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
55 		       crtcstate->CRTC[index]);
56 }
57 
58 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
59 {
60 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
61 	struct drm_device *dev = crtc->dev;
62 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
63 
64 	regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
65 	if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
66 		regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
67 		regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
68 		crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
69 	}
70 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
71 }
72 
73 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
74 {
75 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
76 	struct drm_device *dev = crtc->dev;
77 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
78 
79 	nv_crtc->sharpness = level;
80 	if (level < 0)	/* blur is in hw range 0x3f -> 0x20 */
81 		level += 0x40;
82 	regp->ramdac_634 = level;
83 	NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
84 }
85 
86 #define PLLSEL_VPLL1_MASK				\
87 	(NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL	\
88 	 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
89 #define PLLSEL_VPLL2_MASK				\
90 	(NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2		\
91 	 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
92 #define PLLSEL_TV_MASK					\
93 	(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1		\
94 	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1		\
95 	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2	\
96 	 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
97 
98 /* NV4x 0x40.. pll notes:
99  * gpu pll: 0x4000 + 0x4004
100  * ?gpu? pll: 0x4008 + 0x400c
101  * vpll1: 0x4010 + 0x4014
102  * vpll2: 0x4018 + 0x401c
103  * mpll: 0x4020 + 0x4024
104  * mpll: 0x4038 + 0x403c
105  *
106  * the first register of each pair has some unknown details:
107  * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
108  * bits 20-23: (mpll) something to do with post divider?
109  * bits 28-31: related to single stage mode? (bit 8/12)
110  */
111 
112 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
113 {
114 	struct drm_device *dev = crtc->dev;
115 	struct nouveau_drm *drm = nouveau_drm(dev);
116 	struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
117 	struct nvkm_clk *clk = nvxx_clk(&drm->client.device);
118 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
119 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
120 	struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
121 	struct nvkm_pll_vals *pv = &regp->pllvals;
122 	struct nvbios_pll pll_lim;
123 
124 	if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
125 			    &pll_lim))
126 		return;
127 
128 	/* NM2 == 0 is used to determine single stage mode on two stage plls */
129 	pv->NM2 = 0;
130 
131 	/* for newer nv4x the blob uses only the first stage of the vpll below a
132 	 * certain clock.  for a certain nv4b this is 150MHz.  since the max
133 	 * output frequency of the first stage for this card is 300MHz, it is
134 	 * assumed the threshold is given by vco1 maxfreq/2
135 	 */
136 	/* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
137 	 * not 8, others unknown), the blob always uses both plls.  no problem
138 	 * has yet been observed in allowing the use a single stage pll on all
139 	 * nv43 however.  the behaviour of single stage use is untested on nv40
140 	 */
141 	if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
142 		memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
143 
144 
145 	if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
146 		return;
147 
148 	state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
149 
150 	/* The blob uses this always, so let's do the same */
151 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
152 		state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
153 	/* again nv40 and some nv43 act more like nv3x as described above */
154 	if (drm->client.device.info.chipset < 0x41)
155 		state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
156 				 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
157 	state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
158 
159 	if (pv->NM2)
160 		NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
161 			 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
162 	else
163 		NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
164 			 pv->N1, pv->M1, pv->log2P);
165 
166 	nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
167 }
168 
169 static void
170 nv_crtc_dpms(struct drm_crtc *crtc, int mode)
171 {
172 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
173 	struct drm_device *dev = crtc->dev;
174 	struct nouveau_drm *drm = nouveau_drm(dev);
175 	unsigned char seq1 = 0, crtc17 = 0;
176 	unsigned char crtc1A;
177 
178 	NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
179 							nv_crtc->index);
180 
181 	if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
182 		return;
183 
184 	nv_crtc->last_dpms = mode;
185 
186 	if (nv_two_heads(dev))
187 		NVSetOwner(dev, nv_crtc->index);
188 
189 	/* nv4ref indicates these two RPC1 bits inhibit h/v sync */
190 	crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
191 					NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
192 	switch (mode) {
193 	case DRM_MODE_DPMS_STANDBY:
194 		/* Screen: Off; HSync: Off, VSync: On -- Not Supported */
195 		seq1 = 0x20;
196 		crtc17 = 0x80;
197 		crtc1A |= 0x80;
198 		break;
199 	case DRM_MODE_DPMS_SUSPEND:
200 		/* Screen: Off; HSync: On, VSync: Off -- Not Supported */
201 		seq1 = 0x20;
202 		crtc17 = 0x80;
203 		crtc1A |= 0x40;
204 		break;
205 	case DRM_MODE_DPMS_OFF:
206 		/* Screen: Off; HSync: Off, VSync: Off */
207 		seq1 = 0x20;
208 		crtc17 = 0x00;
209 		crtc1A |= 0xC0;
210 		break;
211 	case DRM_MODE_DPMS_ON:
212 	default:
213 		/* Screen: On; HSync: On, VSync: On */
214 		seq1 = 0x00;
215 		crtc17 = 0x80;
216 		break;
217 	}
218 
219 	NVVgaSeqReset(dev, nv_crtc->index, true);
220 	/* Each head has it's own sequencer, so we can turn it off when we want */
221 	seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
222 	NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
223 	crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
224 	mdelay(10);
225 	NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
226 	NVVgaSeqReset(dev, nv_crtc->index, false);
227 
228 	NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
229 }
230 
231 static void
232 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
233 {
234 	struct drm_device *dev = crtc->dev;
235 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
236 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
237 	struct drm_framebuffer *fb = crtc->primary->fb;
238 
239 	/* Calculate our timings */
240 	int horizDisplay	= (mode->crtc_hdisplay >> 3)		- 1;
241 	int horizStart		= (mode->crtc_hsync_start >> 3) 	+ 1;
242 	int horizEnd		= (mode->crtc_hsync_end >> 3)		+ 1;
243 	int horizTotal		= (mode->crtc_htotal >> 3)		- 5;
244 	int horizBlankStart	= (mode->crtc_hdisplay >> 3)		- 1;
245 	int horizBlankEnd	= (mode->crtc_htotal >> 3)		- 1;
246 	int vertDisplay		= mode->crtc_vdisplay			- 1;
247 	int vertStart		= mode->crtc_vsync_start 		- 1;
248 	int vertEnd		= mode->crtc_vsync_end			- 1;
249 	int vertTotal		= mode->crtc_vtotal 			- 2;
250 	int vertBlankStart	= mode->crtc_vdisplay 			- 1;
251 	int vertBlankEnd	= mode->crtc_vtotal			- 1;
252 
253 	struct drm_encoder *encoder;
254 	bool fp_output = false;
255 
256 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
257 		struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
258 
259 		if (encoder->crtc == crtc &&
260 		    (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
261 		     nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
262 			fp_output = true;
263 	}
264 
265 	if (fp_output) {
266 		vertStart = vertTotal - 3;
267 		vertEnd = vertTotal - 2;
268 		vertBlankStart = vertStart;
269 		horizStart = horizTotal - 5;
270 		horizEnd = horizTotal - 2;
271 		horizBlankEnd = horizTotal + 4;
272 #if 0
273 		if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
274 			/* This reportedly works around some video overlay bandwidth problems */
275 			horizTotal += 2;
276 #endif
277 	}
278 
279 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
280 		vertTotal |= 1;
281 
282 #if 0
283 	ErrorF("horizDisplay: 0x%X \n", horizDisplay);
284 	ErrorF("horizStart: 0x%X \n", horizStart);
285 	ErrorF("horizEnd: 0x%X \n", horizEnd);
286 	ErrorF("horizTotal: 0x%X \n", horizTotal);
287 	ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
288 	ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
289 	ErrorF("vertDisplay: 0x%X \n", vertDisplay);
290 	ErrorF("vertStart: 0x%X \n", vertStart);
291 	ErrorF("vertEnd: 0x%X \n", vertEnd);
292 	ErrorF("vertTotal: 0x%X \n", vertTotal);
293 	ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
294 	ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
295 #endif
296 
297 	/*
298 	* compute correct Hsync & Vsync polarity
299 	*/
300 	if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
301 		&& (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
302 
303 		regp->MiscOutReg = 0x23;
304 		if (mode->flags & DRM_MODE_FLAG_NHSYNC)
305 			regp->MiscOutReg |= 0x40;
306 		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
307 			regp->MiscOutReg |= 0x80;
308 	} else {
309 		int vdisplay = mode->vdisplay;
310 		if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
311 			vdisplay *= 2;
312 		if (mode->vscan > 1)
313 			vdisplay *= mode->vscan;
314 		if (vdisplay < 400)
315 			regp->MiscOutReg = 0xA3;	/* +hsync -vsync */
316 		else if (vdisplay < 480)
317 			regp->MiscOutReg = 0x63;	/* -hsync +vsync */
318 		else if (vdisplay < 768)
319 			regp->MiscOutReg = 0xE3;	/* -hsync -vsync */
320 		else
321 			regp->MiscOutReg = 0x23;	/* +hsync +vsync */
322 	}
323 
324 	/*
325 	 * Time Sequencer
326 	 */
327 	regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
328 	/* 0x20 disables the sequencer */
329 	if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
330 		regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
331 	else
332 		regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
333 	regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
334 	regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
335 	regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
336 
337 	/*
338 	 * CRTC
339 	 */
340 	regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
341 	regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
342 	regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
343 	regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
344 					  XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
345 	regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
346 	regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
347 					  XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
348 	regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
349 	regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
350 					  XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
351 					  XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
352 					  (1 << 4) |
353 					  XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
354 					  XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
355 					  XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
356 					  XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
357 	regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
358 	regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
359 					      1 << 6 |
360 					      XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
361 	regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
362 	regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
363 	regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
364 	regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
365 	regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
366 	regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
367 	regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
368 	regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
369 	regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
370 	/* framebuffer can be larger than crtc scanout area. */
371 	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
372 	regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
373 	regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
374 	regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
375 	regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
376 	regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
377 
378 	/*
379 	 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
380 	 */
381 
382 	/* framebuffer can be larger than crtc scanout area. */
383 	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
384 		XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
385 	regp->CRTC[NV_CIO_CRE_42] =
386 		XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
387 	regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
388 					    MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
389 	regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
390 					   XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
391 					   XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
392 					   XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
393 					   XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
394 	regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
395 					    XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
396 					    XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
397 					    XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
398 	regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
399 					   XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
400 					   XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
401 					   XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
402 
403 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
404 		horizTotal = (horizTotal >> 1) & ~1;
405 		regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
406 		regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
407 	} else
408 		regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;  /* interlace off */
409 
410 	/*
411 	* Graphics Display Controller
412 	*/
413 	regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
414 	regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
415 	regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
416 	regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
417 	regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
418 	regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
419 	regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
420 	regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
421 	regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
422 
423 	regp->Attribute[0]  = 0x00; /* standard colormap translation */
424 	regp->Attribute[1]  = 0x01;
425 	regp->Attribute[2]  = 0x02;
426 	regp->Attribute[3]  = 0x03;
427 	regp->Attribute[4]  = 0x04;
428 	regp->Attribute[5]  = 0x05;
429 	regp->Attribute[6]  = 0x06;
430 	regp->Attribute[7]  = 0x07;
431 	regp->Attribute[8]  = 0x08;
432 	regp->Attribute[9]  = 0x09;
433 	regp->Attribute[10] = 0x0A;
434 	regp->Attribute[11] = 0x0B;
435 	regp->Attribute[12] = 0x0C;
436 	regp->Attribute[13] = 0x0D;
437 	regp->Attribute[14] = 0x0E;
438 	regp->Attribute[15] = 0x0F;
439 	regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
440 	/* Non-vga */
441 	regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
442 	regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
443 	regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
444 	regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
445 }
446 
447 /**
448  * Sets up registers for the given mode/adjusted_mode pair.
449  *
450  * The clocks, CRTCs and outputs attached to this CRTC must be off.
451  *
452  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
453  * be easily turned on/off after this.
454  */
455 static void
456 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
457 {
458 	struct drm_device *dev = crtc->dev;
459 	struct nouveau_drm *drm = nouveau_drm(dev);
460 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
461 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
462 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
463 	const struct drm_framebuffer *fb = crtc->primary->fb;
464 	struct drm_encoder *encoder;
465 	bool lvds_output = false, tmds_output = false, tv_output = false,
466 		off_chip_digital = false;
467 
468 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
469 		struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
470 		bool digital = false;
471 
472 		if (encoder->crtc != crtc)
473 			continue;
474 
475 		if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
476 			digital = lvds_output = true;
477 		if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
478 			tv_output = true;
479 		if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
480 			digital = tmds_output = true;
481 		if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
482 			off_chip_digital = true;
483 	}
484 
485 	/* Registers not directly related to the (s)vga mode */
486 
487 	/* What is the meaning of this register? */
488 	/* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
489 	regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
490 
491 	regp->crtc_eng_ctrl = 0;
492 	/* Except for rare conditions I2C is enabled on the primary crtc */
493 	if (nv_crtc->index == 0)
494 		regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
495 #if 0
496 	/* Set overlay to desired crtc. */
497 	if (dev->overlayAdaptor) {
498 		NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
499 		if (pPriv->overlayCRTC == nv_crtc->index)
500 			regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
501 	}
502 #endif
503 
504 	/* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
505 	regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
506 			     NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
507 			     NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
508 	if (drm->client.device.info.chipset >= 0x11)
509 		regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
510 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
511 		regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
512 
513 	/* Unblock some timings */
514 	regp->CRTC[NV_CIO_CRE_53] = 0;
515 	regp->CRTC[NV_CIO_CRE_54] = 0;
516 
517 	/* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
518 	if (lvds_output)
519 		regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
520 	else if (tmds_output)
521 		regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
522 	else
523 		regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
524 
525 	/* These values seem to vary */
526 	/* This register seems to be used by the bios to make certain decisions on some G70 cards? */
527 	regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
528 
529 	nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
530 
531 	/* probably a scratch reg, but kept for cargo-cult purposes:
532 	 * bit0: crtc0?, head A
533 	 * bit6: lvds, head A
534 	 * bit7: (only in X), head A
535 	 */
536 	if (nv_crtc->index == 0)
537 		regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
538 
539 	/* The blob seems to take the current value from crtc 0, add 4 to that
540 	 * and reuse the old value for crtc 1 */
541 	regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
542 	if (!nv_crtc->index)
543 		regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
544 
545 	/* the blob sometimes sets |= 0x10 (which is the same as setting |=
546 	 * 1 << 30 on 0x60.830), for no apparent reason */
547 	regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
548 
549 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
550 		regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
551 
552 	regp->crtc_830 = mode->crtc_vdisplay - 3;
553 	regp->crtc_834 = mode->crtc_vdisplay - 1;
554 
555 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
556 		/* This is what the blob does */
557 		regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
558 
559 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
560 		regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
561 
562 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
563 		regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
564 	else
565 		regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
566 
567 	/* Some misc regs */
568 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
569 		regp->CRTC[NV_CIO_CRE_85] = 0xFF;
570 		regp->CRTC[NV_CIO_CRE_86] = 0x1;
571 	}
572 
573 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
574 	/* Enable slaved mode (called MODE_TV in nv4ref.h) */
575 	if (lvds_output || tmds_output || tv_output)
576 		regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
577 
578 	/* Generic PRAMDAC regs */
579 
580 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
581 		/* Only bit that bios and blob set. */
582 		regp->nv10_cursync = (1 << 25);
583 
584 	regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
585 				NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
586 				NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
587 	if (fb->format->depth == 16)
588 		regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
589 	if (drm->client.device.info.chipset >= 0x11)
590 		regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
591 
592 	regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
593 	regp->tv_setup = 0;
594 
595 	nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
596 
597 	/* Some values the blob sets */
598 	regp->ramdac_8c0 = 0x100;
599 	regp->ramdac_a20 = 0x0;
600 	regp->ramdac_a24 = 0xfffff;
601 	regp->ramdac_a34 = 0x1;
602 }
603 
604 static int
605 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
606 {
607 	struct nv04_display *disp = nv04_display(crtc->dev);
608 	struct drm_framebuffer *fb = crtc->primary->fb;
609 	struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]);
610 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
611 	int ret;
612 
613 	ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, false);
614 	if (ret == 0) {
615 		if (disp->image[nv_crtc->index])
616 			nouveau_bo_unpin(disp->image[nv_crtc->index]);
617 		nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]);
618 	}
619 
620 	return ret;
621 }
622 
623 /**
624  * Sets up registers for the given mode/adjusted_mode pair.
625  *
626  * The clocks, CRTCs and outputs attached to this CRTC must be off.
627  *
628  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
629  * be easily turned on/off after this.
630  */
631 static int
632 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
633 		 struct drm_display_mode *adjusted_mode,
634 		 int x, int y, struct drm_framebuffer *old_fb)
635 {
636 	struct drm_device *dev = crtc->dev;
637 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
638 	struct nouveau_drm *drm = nouveau_drm(dev);
639 	int ret;
640 
641 	NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
642 	drm_mode_debug_printmodeline(adjusted_mode);
643 
644 	ret = nv_crtc_swap_fbs(crtc, old_fb);
645 	if (ret)
646 		return ret;
647 
648 	/* unlock must come after turning off FP_TG_CONTROL in output_prepare */
649 	nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
650 
651 	nv_crtc_mode_set_vga(crtc, adjusted_mode);
652 	/* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
653 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
654 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
655 	nv_crtc_mode_set_regs(crtc, adjusted_mode);
656 	nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
657 	return 0;
658 }
659 
660 static void nv_crtc_save(struct drm_crtc *crtc)
661 {
662 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
663 	struct drm_device *dev = crtc->dev;
664 	struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
665 	struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
666 	struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
667 	struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
668 
669 	if (nv_two_heads(crtc->dev))
670 		NVSetOwner(crtc->dev, nv_crtc->index);
671 
672 	nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
673 
674 	/* init some state to saved value */
675 	state->sel_clk = saved->sel_clk & ~(0x5 << 16);
676 	crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
677 	state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
678 	crtc_state->gpio_ext = crtc_saved->gpio_ext;
679 }
680 
681 static void nv_crtc_restore(struct drm_crtc *crtc)
682 {
683 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
684 	struct drm_device *dev = crtc->dev;
685 	int head = nv_crtc->index;
686 	uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
687 
688 	if (nv_two_heads(crtc->dev))
689 		NVSetOwner(crtc->dev, head);
690 
691 	nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
692 	nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
693 
694 	nv_crtc->last_dpms = NV_DPMS_CLEARED;
695 }
696 
697 static void nv_crtc_prepare(struct drm_crtc *crtc)
698 {
699 	struct drm_device *dev = crtc->dev;
700 	struct nouveau_drm *drm = nouveau_drm(dev);
701 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
702 	const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
703 
704 	if (nv_two_heads(dev))
705 		NVSetOwner(dev, nv_crtc->index);
706 
707 	drm_crtc_vblank_off(crtc);
708 	funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
709 
710 	NVBlankScreen(dev, nv_crtc->index, true);
711 
712 	/* Some more preparation. */
713 	NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
714 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
715 		uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
716 		NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
717 	}
718 }
719 
720 static void nv_crtc_commit(struct drm_crtc *crtc)
721 {
722 	struct drm_device *dev = crtc->dev;
723 	const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
724 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
725 
726 	nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
727 	nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
728 
729 #ifdef __BIG_ENDIAN
730 	/* turn on LFB swapping */
731 	{
732 		uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
733 		tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
734 		NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
735 	}
736 #endif
737 
738 	funcs->dpms(crtc, DRM_MODE_DPMS_ON);
739 	drm_crtc_vblank_on(crtc);
740 }
741 
742 static void nv_crtc_destroy(struct drm_crtc *crtc)
743 {
744 	struct nv04_display *disp = nv04_display(crtc->dev);
745 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
746 
747 	if (!nv_crtc)
748 		return;
749 
750 	drm_crtc_cleanup(crtc);
751 
752 	if (disp->image[nv_crtc->index])
753 		nouveau_bo_unpin(disp->image[nv_crtc->index]);
754 	nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
755 
756 	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
757 	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
758 	nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
759 	kfree(nv_crtc);
760 }
761 
762 static void
763 nv_crtc_gamma_load(struct drm_crtc *crtc)
764 {
765 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
766 	struct drm_device *dev = nv_crtc->base.dev;
767 	struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
768 	u16 *r, *g, *b;
769 	int i;
770 
771 	rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
772 	r = crtc->gamma_store;
773 	g = r + crtc->gamma_size;
774 	b = g + crtc->gamma_size;
775 
776 	for (i = 0; i < 256; i++) {
777 		rgbs[i].r = *r++ >> 8;
778 		rgbs[i].g = *g++ >> 8;
779 		rgbs[i].b = *b++ >> 8;
780 	}
781 
782 	nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
783 }
784 
785 static void
786 nv_crtc_disable(struct drm_crtc *crtc)
787 {
788 	struct nv04_display *disp = nv04_display(crtc->dev);
789 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
790 	if (disp->image[nv_crtc->index])
791 		nouveau_bo_unpin(disp->image[nv_crtc->index]);
792 	nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
793 }
794 
795 static int
796 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
797 		  uint32_t size,
798 		  struct drm_modeset_acquire_ctx *ctx)
799 {
800 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
801 
802 	/* We need to know the depth before we upload, but it's possible to
803 	 * get called before a framebuffer is bound.  If this is the case,
804 	 * mark the lut values as dirty by setting depth==0, and it'll be
805 	 * uploaded on the first mode_set_base()
806 	 */
807 	if (!nv_crtc->base.primary->fb) {
808 		nv_crtc->lut.depth = 0;
809 		return 0;
810 	}
811 
812 	nv_crtc_gamma_load(crtc);
813 
814 	return 0;
815 }
816 
817 static int
818 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
819 			   struct drm_framebuffer *passed_fb,
820 			   int x, int y, bool atomic)
821 {
822 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
823 	struct drm_device *dev = crtc->dev;
824 	struct nouveau_drm *drm = nouveau_drm(dev);
825 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
826 	struct nouveau_bo *nvbo;
827 	struct drm_framebuffer *drm_fb;
828 	int arb_burst, arb_lwm;
829 
830 	NV_DEBUG(drm, "index %d\n", nv_crtc->index);
831 
832 	/* no fb bound */
833 	if (!atomic && !crtc->primary->fb) {
834 		NV_DEBUG(drm, "No FB bound\n");
835 		return 0;
836 	}
837 
838 	/* If atomic, we want to switch to the fb we were passed, so
839 	 * now we update pointers to do that.
840 	 */
841 	if (atomic) {
842 		drm_fb = passed_fb;
843 	} else {
844 		drm_fb = crtc->primary->fb;
845 	}
846 
847 	nvbo = nouveau_gem_object(drm_fb->obj[0]);
848 	nv_crtc->fb.offset = nvbo->bo.offset;
849 
850 	if (nv_crtc->lut.depth != drm_fb->format->depth) {
851 		nv_crtc->lut.depth = drm_fb->format->depth;
852 		nv_crtc_gamma_load(crtc);
853 	}
854 
855 	/* Update the framebuffer format. */
856 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
857 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8;
858 	regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
859 	if (drm_fb->format->depth == 16)
860 		regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
861 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
862 	NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
863 		      regp->ramdac_gen_ctrl);
864 
865 	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
866 	regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
867 		XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
868 	regp->CRTC[NV_CIO_CRE_42] =
869 		XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
870 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
871 	crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
872 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
873 
874 	/* Update the framebuffer location. */
875 	regp->fb_start = nv_crtc->fb.offset & ~3;
876 	regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
877 	nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
878 
879 	/* Update the arbitration parameters. */
880 	nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
881 			 &arb_burst, &arb_lwm);
882 
883 	regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
884 	regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
885 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
886 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
887 
888 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
889 		regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
890 		crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
891 	}
892 
893 	return 0;
894 }
895 
896 static int
897 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
898 			struct drm_framebuffer *old_fb)
899 {
900 	int ret = nv_crtc_swap_fbs(crtc, old_fb);
901 	if (ret)
902 		return ret;
903 	return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
904 }
905 
906 static int
907 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
908 			       struct drm_framebuffer *fb,
909 			       int x, int y, enum mode_set_atomic state)
910 {
911 	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
912 	struct drm_device *dev = drm->dev;
913 
914 	if (state == ENTER_ATOMIC_MODE_SET)
915 		nouveau_fbcon_accel_save_disable(dev);
916 	else
917 		nouveau_fbcon_accel_restore(dev);
918 
919 	return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
920 }
921 
922 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
923 			       struct nouveau_bo *dst)
924 {
925 	int width = nv_cursor_width(dev);
926 	uint32_t pixel;
927 	int i, j;
928 
929 	for (i = 0; i < width; i++) {
930 		for (j = 0; j < width; j++) {
931 			pixel = nouveau_bo_rd32(src, i*64 + j);
932 
933 			nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
934 				     | (pixel & 0xf80000) >> 9
935 				     | (pixel & 0xf800) >> 6
936 				     | (pixel & 0xf8) >> 3);
937 		}
938 	}
939 }
940 
941 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
942 			       struct nouveau_bo *dst)
943 {
944 	uint32_t pixel;
945 	int alpha, i;
946 
947 	/* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
948 	 * cursors (though NPM in combination with fp dithering may not work on
949 	 * nv11, from "nv" driver history)
950 	 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
951 	 * blob uses, however we get given PM cursors so we use PM mode
952 	 */
953 	for (i = 0; i < 64 * 64; i++) {
954 		pixel = nouveau_bo_rd32(src, i);
955 
956 		/* hw gets unhappy if alpha <= rgb values.  for a PM image "less
957 		 * than" shouldn't happen; fix "equal to" case by adding one to
958 		 * alpha channel (slightly inaccurate, but so is attempting to
959 		 * get back to NPM images, due to limits of integer precision)
960 		 */
961 		alpha = pixel >> 24;
962 		if (alpha > 0 && alpha < 255)
963 			pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
964 
965 #ifdef __BIG_ENDIAN
966 		{
967 			struct nouveau_drm *drm = nouveau_drm(dev);
968 
969 			if (drm->client.device.info.chipset == 0x11) {
970 				pixel = ((pixel & 0x000000ff) << 24) |
971 					((pixel & 0x0000ff00) << 8) |
972 					((pixel & 0x00ff0000) >> 8) |
973 					((pixel & 0xff000000) >> 24);
974 			}
975 		}
976 #endif
977 
978 		nouveau_bo_wr32(dst, i, pixel);
979 	}
980 }
981 
982 static int
983 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
984 		     uint32_t buffer_handle, uint32_t width, uint32_t height)
985 {
986 	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
987 	struct drm_device *dev = drm->dev;
988 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
989 	struct nouveau_bo *cursor = NULL;
990 	struct drm_gem_object *gem;
991 	int ret = 0;
992 
993 	if (!buffer_handle) {
994 		nv_crtc->cursor.hide(nv_crtc, true);
995 		return 0;
996 	}
997 
998 	if (width != 64 || height != 64)
999 		return -EINVAL;
1000 
1001 	gem = drm_gem_object_lookup(file_priv, buffer_handle);
1002 	if (!gem)
1003 		return -ENOENT;
1004 	cursor = nouveau_gem_object(gem);
1005 
1006 	ret = nouveau_bo_map(cursor);
1007 	if (ret)
1008 		goto out;
1009 
1010 	if (drm->client.device.info.chipset >= 0x11)
1011 		nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1012 	else
1013 		nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1014 
1015 	nouveau_bo_unmap(cursor);
1016 	nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
1017 	nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1018 	nv_crtc->cursor.show(nv_crtc, true);
1019 out:
1020 	drm_gem_object_put_unlocked(gem);
1021 	return ret;
1022 }
1023 
1024 static int
1025 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1026 {
1027 	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1028 
1029 	nv_crtc->cursor.set_pos(nv_crtc, x, y);
1030 	return 0;
1031 }
1032 
1033 struct nv04_page_flip_state {
1034 	struct list_head head;
1035 	struct drm_pending_vblank_event *event;
1036 	struct drm_crtc *crtc;
1037 	int bpp, pitch;
1038 	u64 offset;
1039 };
1040 
1041 static int
1042 nv04_finish_page_flip(struct nouveau_channel *chan,
1043 		      struct nv04_page_flip_state *ps)
1044 {
1045 	struct nouveau_fence_chan *fctx = chan->fence;
1046 	struct nouveau_drm *drm = chan->drm;
1047 	struct drm_device *dev = drm->dev;
1048 	struct nv04_page_flip_state *s;
1049 	unsigned long flags;
1050 
1051 	spin_lock_irqsave(&dev->event_lock, flags);
1052 
1053 	if (list_empty(&fctx->flip)) {
1054 		NV_ERROR(drm, "unexpected pageflip\n");
1055 		spin_unlock_irqrestore(&dev->event_lock, flags);
1056 		return -EINVAL;
1057 	}
1058 
1059 	s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head);
1060 	if (s->event) {
1061 		drm_crtc_arm_vblank_event(s->crtc, s->event);
1062 	} else {
1063 		/* Give up ownership of vblank for page-flipped crtc */
1064 		drm_crtc_vblank_put(s->crtc);
1065 	}
1066 
1067 	list_del(&s->head);
1068 	if (ps)
1069 		*ps = *s;
1070 	kfree(s);
1071 
1072 	spin_unlock_irqrestore(&dev->event_lock, flags);
1073 	return 0;
1074 }
1075 
1076 int
1077 nv04_flip_complete(struct nvif_notify *notify)
1078 {
1079 	struct nouveau_cli *cli = (void *)notify->object->client;
1080 	struct nouveau_drm *drm = cli->drm;
1081 	struct nouveau_channel *chan = drm->channel;
1082 	struct nv04_page_flip_state state;
1083 
1084 	if (!nv04_finish_page_flip(chan, &state)) {
1085 		nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc),
1086 				 state.offset + state.crtc->y *
1087 				 state.pitch + state.crtc->x *
1088 				 state.bpp / 8);
1089 	}
1090 
1091 	return NVIF_NOTIFY_KEEP;
1092 }
1093 
1094 static int
1095 nv04_page_flip_emit(struct nouveau_channel *chan,
1096 		    struct nouveau_bo *old_bo,
1097 		    struct nouveau_bo *new_bo,
1098 		    struct nv04_page_flip_state *s,
1099 		    struct nouveau_fence **pfence)
1100 {
1101 	struct nouveau_fence_chan *fctx = chan->fence;
1102 	struct nouveau_drm *drm = chan->drm;
1103 	struct drm_device *dev = drm->dev;
1104 	unsigned long flags;
1105 	int ret;
1106 
1107 	/* Queue it to the pending list */
1108 	spin_lock_irqsave(&dev->event_lock, flags);
1109 	list_add_tail(&s->head, &fctx->flip);
1110 	spin_unlock_irqrestore(&dev->event_lock, flags);
1111 
1112 	/* Synchronize with the old framebuffer */
1113 	ret = nouveau_fence_sync(old_bo, chan, false, false);
1114 	if (ret)
1115 		goto fail;
1116 
1117 	/* Emit the pageflip */
1118 	ret = RING_SPACE(chan, 2);
1119 	if (ret)
1120 		goto fail;
1121 
1122 	BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
1123 	OUT_RING  (chan, 0x00000000);
1124 	FIRE_RING (chan);
1125 
1126 	ret = nouveau_fence_new(chan, false, pfence);
1127 	if (ret)
1128 		goto fail;
1129 
1130 	return 0;
1131 fail:
1132 	spin_lock_irqsave(&dev->event_lock, flags);
1133 	list_del(&s->head);
1134 	spin_unlock_irqrestore(&dev->event_lock, flags);
1135 	return ret;
1136 }
1137 
1138 static int
1139 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1140 		    struct drm_pending_vblank_event *event, u32 flags,
1141 		    struct drm_modeset_acquire_ctx *ctx)
1142 {
1143 	const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
1144 	struct drm_device *dev = crtc->dev;
1145 	struct nouveau_drm *drm = nouveau_drm(dev);
1146 	struct drm_framebuffer *old_fb = crtc->primary->fb;
1147 	struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]);
1148 	struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]);
1149 	struct nv04_page_flip_state *s;
1150 	struct nouveau_channel *chan;
1151 	struct nouveau_cli *cli;
1152 	struct nouveau_fence *fence;
1153 	struct nv04_display *dispnv04 = nv04_display(dev);
1154 	int head = nouveau_crtc(crtc)->index;
1155 	int ret;
1156 
1157 	chan = drm->channel;
1158 	if (!chan)
1159 		return -ENODEV;
1160 	cli = (void *)chan->user.client;
1161 
1162 	s = kzalloc(sizeof(*s), GFP_KERNEL);
1163 	if (!s)
1164 		return -ENOMEM;
1165 
1166 	if (new_bo != old_bo) {
1167 		ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM, true);
1168 		if (ret)
1169 			goto fail_free;
1170 	}
1171 
1172 	mutex_lock(&cli->mutex);
1173 	ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL);
1174 	if (ret)
1175 		goto fail_unpin;
1176 
1177 	/* synchronise rendering channel with the kernel's channel */
1178 	ret = nouveau_fence_sync(new_bo, chan, false, true);
1179 	if (ret) {
1180 		ttm_bo_unreserve(&new_bo->bo);
1181 		goto fail_unpin;
1182 	}
1183 
1184 	if (new_bo != old_bo) {
1185 		ttm_bo_unreserve(&new_bo->bo);
1186 
1187 		ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL);
1188 		if (ret)
1189 			goto fail_unpin;
1190 	}
1191 
1192 	/* Initialize a page flip struct */
1193 	*s = (struct nv04_page_flip_state)
1194 		{ { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
1195 		  new_bo->bo.offset };
1196 
1197 	/* Keep vblanks on during flip, for the target crtc of this flip */
1198 	drm_crtc_vblank_get(crtc);
1199 
1200 	/* Emit a page flip */
1201 	if (swap_interval) {
1202 		ret = RING_SPACE(chan, 8);
1203 		if (ret)
1204 			goto fail_unreserve;
1205 
1206 		BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1);
1207 		OUT_RING  (chan, 0);
1208 		BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1);
1209 		OUT_RING  (chan, head);
1210 		BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1);
1211 		OUT_RING  (chan, 0);
1212 		BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1);
1213 		OUT_RING  (chan, 0);
1214 	}
1215 
1216 	nouveau_bo_ref(new_bo, &dispnv04->image[head]);
1217 
1218 	ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence);
1219 	if (ret)
1220 		goto fail_unreserve;
1221 	mutex_unlock(&cli->mutex);
1222 
1223 	/* Update the crtc struct and cleanup */
1224 	crtc->primary->fb = fb;
1225 
1226 	nouveau_bo_fence(old_bo, fence, false);
1227 	ttm_bo_unreserve(&old_bo->bo);
1228 	if (old_bo != new_bo)
1229 		nouveau_bo_unpin(old_bo);
1230 	nouveau_fence_unref(&fence);
1231 	return 0;
1232 
1233 fail_unreserve:
1234 	drm_crtc_vblank_put(crtc);
1235 	ttm_bo_unreserve(&old_bo->bo);
1236 fail_unpin:
1237 	mutex_unlock(&cli->mutex);
1238 	if (old_bo != new_bo)
1239 		nouveau_bo_unpin(new_bo);
1240 fail_free:
1241 	kfree(s);
1242 	return ret;
1243 }
1244 
1245 static const struct drm_crtc_funcs nv04_crtc_funcs = {
1246 	.cursor_set = nv04_crtc_cursor_set,
1247 	.cursor_move = nv04_crtc_cursor_move,
1248 	.gamma_set = nv_crtc_gamma_set,
1249 	.set_config = drm_crtc_helper_set_config,
1250 	.page_flip = nv04_crtc_page_flip,
1251 	.destroy = nv_crtc_destroy,
1252 	.enable_vblank = nouveau_display_vblank_enable,
1253 	.disable_vblank = nouveau_display_vblank_disable,
1254 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1255 };
1256 
1257 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1258 	.dpms = nv_crtc_dpms,
1259 	.prepare = nv_crtc_prepare,
1260 	.commit = nv_crtc_commit,
1261 	.mode_set = nv_crtc_mode_set,
1262 	.mode_set_base = nv04_crtc_mode_set_base,
1263 	.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1264 	.disable = nv_crtc_disable,
1265 	.get_scanout_position = nouveau_display_scanoutpos,
1266 };
1267 
1268 static const uint32_t modeset_formats[] = {
1269         DRM_FORMAT_XRGB8888,
1270         DRM_FORMAT_RGB565,
1271         DRM_FORMAT_XRGB1555,
1272 };
1273 
1274 static struct drm_plane *
1275 create_primary_plane(struct drm_device *dev)
1276 {
1277         struct drm_plane *primary;
1278         int ret;
1279 
1280         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1281         if (primary == NULL) {
1282                 DRM_DEBUG_KMS("Failed to allocate primary plane\n");
1283                 return NULL;
1284         }
1285 
1286         /* possible_crtc's will be filled in later by crtc_init */
1287         ret = drm_universal_plane_init(dev, primary, 0,
1288                                        &drm_primary_helper_funcs,
1289                                        modeset_formats,
1290                                        ARRAY_SIZE(modeset_formats), NULL,
1291                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1292         if (ret) {
1293                 kfree(primary);
1294                 primary = NULL;
1295         }
1296 
1297         return primary;
1298 }
1299 
1300 int
1301 nv04_crtc_create(struct drm_device *dev, int crtc_num)
1302 {
1303 	struct nouveau_crtc *nv_crtc;
1304 	int ret;
1305 
1306 	nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1307 	if (!nv_crtc)
1308 		return -ENOMEM;
1309 
1310 	nv_crtc->lut.depth = 0;
1311 
1312 	nv_crtc->index = crtc_num;
1313 	nv_crtc->last_dpms = NV_DPMS_CLEARED;
1314 
1315 	nv_crtc->save = nv_crtc_save;
1316 	nv_crtc->restore = nv_crtc_restore;
1317 
1318 	drm_crtc_init_with_planes(dev, &nv_crtc->base,
1319                                   create_primary_plane(dev), NULL,
1320                                   &nv04_crtc_funcs, NULL);
1321 	drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1322 	drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1323 
1324 	ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100,
1325 			     TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL,
1326 			     &nv_crtc->cursor.nvbo);
1327 	if (!ret) {
1328 		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false);
1329 		if (!ret) {
1330 			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1331 			if (ret)
1332 				nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1333 		}
1334 		if (ret)
1335 			nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1336 	}
1337 
1338 	nv04_cursor_init(nv_crtc);
1339 
1340 	return 0;
1341 }
1342