1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <linux/pm_runtime.h> 26 27 #include <drm/drmP.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_plane_helper.h> 30 31 #include "nouveau_drm.h" 32 #include "nouveau_reg.h" 33 #include "nouveau_bo.h" 34 #include "nouveau_gem.h" 35 #include "nouveau_encoder.h" 36 #include "nouveau_connector.h" 37 #include "nouveau_crtc.h" 38 #include "hw.h" 39 #include "nvreg.h" 40 #include "nouveau_fbcon.h" 41 #include "disp.h" 42 43 #include <subdev/bios/pll.h> 44 #include <subdev/clk.h> 45 46 static int 47 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 48 struct drm_framebuffer *old_fb); 49 50 static void 51 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 52 { 53 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 54 crtcstate->CRTC[index]); 55 } 56 57 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 58 { 59 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 60 struct drm_device *dev = crtc->dev; 61 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 62 63 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 64 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 65 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 66 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 67 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 68 } 69 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 70 } 71 72 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 73 { 74 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 75 struct drm_device *dev = crtc->dev; 76 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 77 78 nv_crtc->sharpness = level; 79 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 80 level += 0x40; 81 regp->ramdac_634 = level; 82 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 83 } 84 85 #define PLLSEL_VPLL1_MASK \ 86 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 87 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 88 #define PLLSEL_VPLL2_MASK \ 89 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 90 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 91 #define PLLSEL_TV_MASK \ 92 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 93 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 95 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 96 97 /* NV4x 0x40.. pll notes: 98 * gpu pll: 0x4000 + 0x4004 99 * ?gpu? pll: 0x4008 + 0x400c 100 * vpll1: 0x4010 + 0x4014 101 * vpll2: 0x4018 + 0x401c 102 * mpll: 0x4020 + 0x4024 103 * mpll: 0x4038 + 0x403c 104 * 105 * the first register of each pair has some unknown details: 106 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 107 * bits 20-23: (mpll) something to do with post divider? 108 * bits 28-31: related to single stage mode? (bit 8/12) 109 */ 110 111 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 112 { 113 struct drm_device *dev = crtc->dev; 114 struct nouveau_drm *drm = nouveau_drm(dev); 115 struct nvkm_bios *bios = nvxx_bios(&drm->device); 116 struct nvkm_clk *clk = nvxx_clk(&drm->device); 117 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 118 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 119 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 120 struct nvkm_pll_vals *pv = ®p->pllvals; 121 struct nvbios_pll pll_lim; 122 123 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 124 &pll_lim)) 125 return; 126 127 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 128 pv->NM2 = 0; 129 130 /* for newer nv4x the blob uses only the first stage of the vpll below a 131 * certain clock. for a certain nv4b this is 150MHz. since the max 132 * output frequency of the first stage for this card is 300MHz, it is 133 * assumed the threshold is given by vco1 maxfreq/2 134 */ 135 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 136 * not 8, others unknown), the blob always uses both plls. no problem 137 * has yet been observed in allowing the use a single stage pll on all 138 * nv43 however. the behaviour of single stage use is untested on nv40 139 */ 140 if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 141 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 142 143 144 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 145 return; 146 147 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 148 149 /* The blob uses this always, so let's do the same */ 150 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 151 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 152 /* again nv40 and some nv43 act more like nv3x as described above */ 153 if (drm->device.info.chipset < 0x41) 154 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 155 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 156 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 157 158 if (pv->NM2) 159 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 160 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 161 else 162 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 163 pv->N1, pv->M1, pv->log2P); 164 165 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 166 } 167 168 static void 169 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 170 { 171 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 172 struct drm_device *dev = crtc->dev; 173 struct nouveau_drm *drm = nouveau_drm(dev); 174 unsigned char seq1 = 0, crtc17 = 0; 175 unsigned char crtc1A; 176 177 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 178 nv_crtc->index); 179 180 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 181 return; 182 183 nv_crtc->last_dpms = mode; 184 185 if (nv_two_heads(dev)) 186 NVSetOwner(dev, nv_crtc->index); 187 188 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 189 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 190 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 191 switch (mode) { 192 case DRM_MODE_DPMS_STANDBY: 193 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 194 seq1 = 0x20; 195 crtc17 = 0x80; 196 crtc1A |= 0x80; 197 break; 198 case DRM_MODE_DPMS_SUSPEND: 199 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 200 seq1 = 0x20; 201 crtc17 = 0x80; 202 crtc1A |= 0x40; 203 break; 204 case DRM_MODE_DPMS_OFF: 205 /* Screen: Off; HSync: Off, VSync: Off */ 206 seq1 = 0x20; 207 crtc17 = 0x00; 208 crtc1A |= 0xC0; 209 break; 210 case DRM_MODE_DPMS_ON: 211 default: 212 /* Screen: On; HSync: On, VSync: On */ 213 seq1 = 0x00; 214 crtc17 = 0x80; 215 break; 216 } 217 218 NVVgaSeqReset(dev, nv_crtc->index, true); 219 /* Each head has it's own sequencer, so we can turn it off when we want */ 220 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 221 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 222 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 223 mdelay(10); 224 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 225 NVVgaSeqReset(dev, nv_crtc->index, false); 226 227 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 228 } 229 230 static void 231 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 232 { 233 struct drm_device *dev = crtc->dev; 234 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 235 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 236 struct drm_framebuffer *fb = crtc->primary->fb; 237 238 /* Calculate our timings */ 239 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 240 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 241 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 242 int horizTotal = (mode->crtc_htotal >> 3) - 5; 243 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 244 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 245 int vertDisplay = mode->crtc_vdisplay - 1; 246 int vertStart = mode->crtc_vsync_start - 1; 247 int vertEnd = mode->crtc_vsync_end - 1; 248 int vertTotal = mode->crtc_vtotal - 2; 249 int vertBlankStart = mode->crtc_vdisplay - 1; 250 int vertBlankEnd = mode->crtc_vtotal - 1; 251 252 struct drm_encoder *encoder; 253 bool fp_output = false; 254 255 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 256 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 257 258 if (encoder->crtc == crtc && 259 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 260 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 261 fp_output = true; 262 } 263 264 if (fp_output) { 265 vertStart = vertTotal - 3; 266 vertEnd = vertTotal - 2; 267 vertBlankStart = vertStart; 268 horizStart = horizTotal - 5; 269 horizEnd = horizTotal - 2; 270 horizBlankEnd = horizTotal + 4; 271 #if 0 272 if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 273 /* This reportedly works around some video overlay bandwidth problems */ 274 horizTotal += 2; 275 #endif 276 } 277 278 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 279 vertTotal |= 1; 280 281 #if 0 282 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 283 ErrorF("horizStart: 0x%X \n", horizStart); 284 ErrorF("horizEnd: 0x%X \n", horizEnd); 285 ErrorF("horizTotal: 0x%X \n", horizTotal); 286 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 287 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 288 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 289 ErrorF("vertStart: 0x%X \n", vertStart); 290 ErrorF("vertEnd: 0x%X \n", vertEnd); 291 ErrorF("vertTotal: 0x%X \n", vertTotal); 292 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 293 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 294 #endif 295 296 /* 297 * compute correct Hsync & Vsync polarity 298 */ 299 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 300 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 301 302 regp->MiscOutReg = 0x23; 303 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 304 regp->MiscOutReg |= 0x40; 305 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 306 regp->MiscOutReg |= 0x80; 307 } else { 308 int vdisplay = mode->vdisplay; 309 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 310 vdisplay *= 2; 311 if (mode->vscan > 1) 312 vdisplay *= mode->vscan; 313 if (vdisplay < 400) 314 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 315 else if (vdisplay < 480) 316 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 317 else if (vdisplay < 768) 318 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 319 else 320 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 321 } 322 323 /* 324 * Time Sequencer 325 */ 326 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 327 /* 0x20 disables the sequencer */ 328 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 329 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 330 else 331 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 332 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 333 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 334 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 335 336 /* 337 * CRTC 338 */ 339 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 340 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 341 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 342 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 343 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 344 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 345 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 346 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 347 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 348 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 349 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 350 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 351 (1 << 4) | 352 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 353 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 354 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 355 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 356 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 357 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 358 1 << 6 | 359 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 360 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 361 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 362 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 363 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 364 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 365 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 366 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 367 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 368 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 369 /* framebuffer can be larger than crtc scanout area. */ 370 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 371 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 372 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 373 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 374 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 375 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 376 377 /* 378 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 379 */ 380 381 /* framebuffer can be larger than crtc scanout area. */ 382 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 383 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 384 regp->CRTC[NV_CIO_CRE_42] = 385 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 386 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 387 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 388 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 389 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 390 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 391 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 392 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 393 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 394 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 395 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 396 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 397 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 398 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 399 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 400 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 401 402 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 403 horizTotal = (horizTotal >> 1) & ~1; 404 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 405 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 406 } else 407 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 408 409 /* 410 * Graphics Display Controller 411 */ 412 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 413 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 414 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 415 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 416 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 417 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 418 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 419 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 420 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 421 422 regp->Attribute[0] = 0x00; /* standard colormap translation */ 423 regp->Attribute[1] = 0x01; 424 regp->Attribute[2] = 0x02; 425 regp->Attribute[3] = 0x03; 426 regp->Attribute[4] = 0x04; 427 regp->Attribute[5] = 0x05; 428 regp->Attribute[6] = 0x06; 429 regp->Attribute[7] = 0x07; 430 regp->Attribute[8] = 0x08; 431 regp->Attribute[9] = 0x09; 432 regp->Attribute[10] = 0x0A; 433 regp->Attribute[11] = 0x0B; 434 regp->Attribute[12] = 0x0C; 435 regp->Attribute[13] = 0x0D; 436 regp->Attribute[14] = 0x0E; 437 regp->Attribute[15] = 0x0F; 438 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 439 /* Non-vga */ 440 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 441 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 442 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 443 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 444 } 445 446 /** 447 * Sets up registers for the given mode/adjusted_mode pair. 448 * 449 * The clocks, CRTCs and outputs attached to this CRTC must be off. 450 * 451 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 452 * be easily turned on/off after this. 453 */ 454 static void 455 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 456 { 457 struct drm_device *dev = crtc->dev; 458 struct nouveau_drm *drm = nouveau_drm(dev); 459 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 460 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 461 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 462 struct drm_encoder *encoder; 463 bool lvds_output = false, tmds_output = false, tv_output = false, 464 off_chip_digital = false; 465 466 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 468 bool digital = false; 469 470 if (encoder->crtc != crtc) 471 continue; 472 473 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 474 digital = lvds_output = true; 475 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 476 tv_output = true; 477 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 478 digital = tmds_output = true; 479 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 480 off_chip_digital = true; 481 } 482 483 /* Registers not directly related to the (s)vga mode */ 484 485 /* What is the meaning of this register? */ 486 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 487 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 488 489 regp->crtc_eng_ctrl = 0; 490 /* Except for rare conditions I2C is enabled on the primary crtc */ 491 if (nv_crtc->index == 0) 492 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 493 #if 0 494 /* Set overlay to desired crtc. */ 495 if (dev->overlayAdaptor) { 496 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 497 if (pPriv->overlayCRTC == nv_crtc->index) 498 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 499 } 500 #endif 501 502 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 503 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 504 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 505 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 506 if (drm->device.info.chipset >= 0x11) 507 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 508 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 509 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 510 511 /* Unblock some timings */ 512 regp->CRTC[NV_CIO_CRE_53] = 0; 513 regp->CRTC[NV_CIO_CRE_54] = 0; 514 515 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 516 if (lvds_output) 517 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 518 else if (tmds_output) 519 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 520 else 521 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 522 523 /* These values seem to vary */ 524 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 525 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 526 527 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 528 529 /* probably a scratch reg, but kept for cargo-cult purposes: 530 * bit0: crtc0?, head A 531 * bit6: lvds, head A 532 * bit7: (only in X), head A 533 */ 534 if (nv_crtc->index == 0) 535 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 536 537 /* The blob seems to take the current value from crtc 0, add 4 to that 538 * and reuse the old value for crtc 1 */ 539 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 540 if (!nv_crtc->index) 541 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 542 543 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 544 * 1 << 30 on 0x60.830), for no apparent reason */ 545 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 546 547 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 548 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 549 550 regp->crtc_830 = mode->crtc_vdisplay - 3; 551 regp->crtc_834 = mode->crtc_vdisplay - 1; 552 553 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 554 /* This is what the blob does */ 555 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 556 557 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 558 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 559 560 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 561 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 562 else 563 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 564 565 /* Some misc regs */ 566 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { 567 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 568 regp->CRTC[NV_CIO_CRE_86] = 0x1; 569 } 570 571 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; 572 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 573 if (lvds_output || tmds_output || tv_output) 574 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 575 576 /* Generic PRAMDAC regs */ 577 578 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 579 /* Only bit that bios and blob set. */ 580 regp->nv10_cursync = (1 << 25); 581 582 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 583 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 584 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 585 if (crtc->primary->fb->depth == 16) 586 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 587 if (drm->device.info.chipset >= 0x11) 588 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 589 590 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 591 regp->tv_setup = 0; 592 593 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 594 595 /* Some values the blob sets */ 596 regp->ramdac_8c0 = 0x100; 597 regp->ramdac_a20 = 0x0; 598 regp->ramdac_a24 = 0xfffff; 599 regp->ramdac_a34 = 0x1; 600 } 601 602 static int 603 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 604 { 605 struct nv04_display *disp = nv04_display(crtc->dev); 606 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); 607 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 608 int ret; 609 610 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false); 611 if (ret == 0) { 612 if (disp->image[nv_crtc->index]) 613 nouveau_bo_unpin(disp->image[nv_crtc->index]); 614 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); 615 } 616 617 return ret; 618 } 619 620 /** 621 * Sets up registers for the given mode/adjusted_mode pair. 622 * 623 * The clocks, CRTCs and outputs attached to this CRTC must be off. 624 * 625 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 626 * be easily turned on/off after this. 627 */ 628 static int 629 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 630 struct drm_display_mode *adjusted_mode, 631 int x, int y, struct drm_framebuffer *old_fb) 632 { 633 struct drm_device *dev = crtc->dev; 634 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 635 struct nouveau_drm *drm = nouveau_drm(dev); 636 int ret; 637 638 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 639 drm_mode_debug_printmodeline(adjusted_mode); 640 641 ret = nv_crtc_swap_fbs(crtc, old_fb); 642 if (ret) 643 return ret; 644 645 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 646 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 647 648 nv_crtc_mode_set_vga(crtc, adjusted_mode); 649 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 650 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 651 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 652 nv_crtc_mode_set_regs(crtc, adjusted_mode); 653 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 654 return 0; 655 } 656 657 static void nv_crtc_save(struct drm_crtc *crtc) 658 { 659 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 660 struct drm_device *dev = crtc->dev; 661 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 662 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 663 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 664 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 665 666 if (nv_two_heads(crtc->dev)) 667 NVSetOwner(crtc->dev, nv_crtc->index); 668 669 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 670 671 /* init some state to saved value */ 672 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 673 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 674 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 675 crtc_state->gpio_ext = crtc_saved->gpio_ext; 676 } 677 678 static void nv_crtc_restore(struct drm_crtc *crtc) 679 { 680 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 681 struct drm_device *dev = crtc->dev; 682 int head = nv_crtc->index; 683 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 684 685 if (nv_two_heads(crtc->dev)) 686 NVSetOwner(crtc->dev, head); 687 688 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 689 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 690 691 nv_crtc->last_dpms = NV_DPMS_CLEARED; 692 } 693 694 static void nv_crtc_prepare(struct drm_crtc *crtc) 695 { 696 struct drm_device *dev = crtc->dev; 697 struct nouveau_drm *drm = nouveau_drm(dev); 698 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 699 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 700 701 if (nv_two_heads(dev)) 702 NVSetOwner(dev, nv_crtc->index); 703 704 drm_vblank_pre_modeset(dev, nv_crtc->index); 705 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 706 707 NVBlankScreen(dev, nv_crtc->index, true); 708 709 /* Some more preparation. */ 710 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 711 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { 712 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 713 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 714 } 715 } 716 717 static void nv_crtc_commit(struct drm_crtc *crtc) 718 { 719 struct drm_device *dev = crtc->dev; 720 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 721 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 722 723 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 724 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 725 726 #ifdef __BIG_ENDIAN 727 /* turn on LFB swapping */ 728 { 729 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 730 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 731 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 732 } 733 #endif 734 735 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 736 drm_vblank_post_modeset(dev, nv_crtc->index); 737 } 738 739 static void nv_crtc_destroy(struct drm_crtc *crtc) 740 { 741 struct nv04_display *disp = nv04_display(crtc->dev); 742 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 743 744 if (!nv_crtc) 745 return; 746 747 drm_crtc_cleanup(crtc); 748 749 if (disp->image[nv_crtc->index]) 750 nouveau_bo_unpin(disp->image[nv_crtc->index]); 751 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 752 753 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 754 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 755 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 756 kfree(nv_crtc); 757 } 758 759 static void 760 nv_crtc_gamma_load(struct drm_crtc *crtc) 761 { 762 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 763 struct drm_device *dev = nv_crtc->base.dev; 764 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 765 int i; 766 767 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 768 for (i = 0; i < 256; i++) { 769 rgbs[i].r = nv_crtc->lut.r[i] >> 8; 770 rgbs[i].g = nv_crtc->lut.g[i] >> 8; 771 rgbs[i].b = nv_crtc->lut.b[i] >> 8; 772 } 773 774 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 775 } 776 777 static void 778 nv_crtc_disable(struct drm_crtc *crtc) 779 { 780 struct nv04_display *disp = nv04_display(crtc->dev); 781 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 782 if (disp->image[nv_crtc->index]) 783 nouveau_bo_unpin(disp->image[nv_crtc->index]); 784 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 785 } 786 787 static void 788 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, 789 uint32_t size) 790 { 791 int end = (start + size > 256) ? 256 : start + size, i; 792 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 793 794 for (i = start; i < end; i++) { 795 nv_crtc->lut.r[i] = r[i]; 796 nv_crtc->lut.g[i] = g[i]; 797 nv_crtc->lut.b[i] = b[i]; 798 } 799 800 /* We need to know the depth before we upload, but it's possible to 801 * get called before a framebuffer is bound. If this is the case, 802 * mark the lut values as dirty by setting depth==0, and it'll be 803 * uploaded on the first mode_set_base() 804 */ 805 if (!nv_crtc->base.primary->fb) { 806 nv_crtc->lut.depth = 0; 807 return; 808 } 809 810 nv_crtc_gamma_load(crtc); 811 } 812 813 static int 814 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 815 struct drm_framebuffer *passed_fb, 816 int x, int y, bool atomic) 817 { 818 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 819 struct drm_device *dev = crtc->dev; 820 struct nouveau_drm *drm = nouveau_drm(dev); 821 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 822 struct drm_framebuffer *drm_fb; 823 struct nouveau_framebuffer *fb; 824 int arb_burst, arb_lwm; 825 826 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 827 828 /* no fb bound */ 829 if (!atomic && !crtc->primary->fb) { 830 NV_DEBUG(drm, "No FB bound\n"); 831 return 0; 832 } 833 834 /* If atomic, we want to switch to the fb we were passed, so 835 * now we update pointers to do that. 836 */ 837 if (atomic) { 838 drm_fb = passed_fb; 839 fb = nouveau_framebuffer(passed_fb); 840 } else { 841 drm_fb = crtc->primary->fb; 842 fb = nouveau_framebuffer(crtc->primary->fb); 843 } 844 845 nv_crtc->fb.offset = fb->nvbo->bo.offset; 846 847 if (nv_crtc->lut.depth != drm_fb->depth) { 848 nv_crtc->lut.depth = drm_fb->depth; 849 nv_crtc_gamma_load(crtc); 850 } 851 852 /* Update the framebuffer format. */ 853 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 854 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; 855 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 856 if (crtc->primary->fb->depth == 16) 857 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 858 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 859 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 860 regp->ramdac_gen_ctrl); 861 862 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 863 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 864 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 865 regp->CRTC[NV_CIO_CRE_42] = 866 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 867 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 868 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 869 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 870 871 /* Update the framebuffer location. */ 872 regp->fb_start = nv_crtc->fb.offset & ~3; 873 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); 874 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 875 876 /* Update the arbitration parameters. */ 877 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, 878 &arb_burst, &arb_lwm); 879 880 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 881 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 882 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 883 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 884 885 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 886 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 887 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 888 } 889 890 return 0; 891 } 892 893 static int 894 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 895 struct drm_framebuffer *old_fb) 896 { 897 int ret = nv_crtc_swap_fbs(crtc, old_fb); 898 if (ret) 899 return ret; 900 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 901 } 902 903 static int 904 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 905 struct drm_framebuffer *fb, 906 int x, int y, enum mode_set_atomic state) 907 { 908 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 909 struct drm_device *dev = drm->dev; 910 911 if (state == ENTER_ATOMIC_MODE_SET) 912 nouveau_fbcon_accel_save_disable(dev); 913 else 914 nouveau_fbcon_accel_restore(dev); 915 916 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 917 } 918 919 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 920 struct nouveau_bo *dst) 921 { 922 int width = nv_cursor_width(dev); 923 uint32_t pixel; 924 int i, j; 925 926 for (i = 0; i < width; i++) { 927 for (j = 0; j < width; j++) { 928 pixel = nouveau_bo_rd32(src, i*64 + j); 929 930 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 931 | (pixel & 0xf80000) >> 9 932 | (pixel & 0xf800) >> 6 933 | (pixel & 0xf8) >> 3); 934 } 935 } 936 } 937 938 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 939 struct nouveau_bo *dst) 940 { 941 uint32_t pixel; 942 int alpha, i; 943 944 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 945 * cursors (though NPM in combination with fp dithering may not work on 946 * nv11, from "nv" driver history) 947 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 948 * blob uses, however we get given PM cursors so we use PM mode 949 */ 950 for (i = 0; i < 64 * 64; i++) { 951 pixel = nouveau_bo_rd32(src, i); 952 953 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 954 * than" shouldn't happen; fix "equal to" case by adding one to 955 * alpha channel (slightly inaccurate, but so is attempting to 956 * get back to NPM images, due to limits of integer precision) 957 */ 958 alpha = pixel >> 24; 959 if (alpha > 0 && alpha < 255) 960 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 961 962 #ifdef __BIG_ENDIAN 963 { 964 struct nouveau_drm *drm = nouveau_drm(dev); 965 966 if (drm->device.info.chipset == 0x11) { 967 pixel = ((pixel & 0x000000ff) << 24) | 968 ((pixel & 0x0000ff00) << 8) | 969 ((pixel & 0x00ff0000) >> 8) | 970 ((pixel & 0xff000000) >> 24); 971 } 972 } 973 #endif 974 975 nouveau_bo_wr32(dst, i, pixel); 976 } 977 } 978 979 static int 980 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 981 uint32_t buffer_handle, uint32_t width, uint32_t height) 982 { 983 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 984 struct drm_device *dev = drm->dev; 985 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 986 struct nouveau_bo *cursor = NULL; 987 struct drm_gem_object *gem; 988 int ret = 0; 989 990 if (!buffer_handle) { 991 nv_crtc->cursor.hide(nv_crtc, true); 992 return 0; 993 } 994 995 if (width != 64 || height != 64) 996 return -EINVAL; 997 998 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 999 if (!gem) 1000 return -ENOENT; 1001 cursor = nouveau_gem_object(gem); 1002 1003 ret = nouveau_bo_map(cursor); 1004 if (ret) 1005 goto out; 1006 1007 if (drm->device.info.chipset >= 0x11) 1008 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1009 else 1010 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1011 1012 nouveau_bo_unmap(cursor); 1013 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 1014 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1015 nv_crtc->cursor.show(nv_crtc, true); 1016 out: 1017 drm_gem_object_unreference_unlocked(gem); 1018 return ret; 1019 } 1020 1021 static int 1022 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1023 { 1024 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1025 1026 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1027 return 0; 1028 } 1029 1030 int 1031 nouveau_crtc_set_config(struct drm_mode_set *set) 1032 { 1033 struct drm_device *dev; 1034 struct nouveau_drm *drm; 1035 int ret; 1036 struct drm_crtc *crtc; 1037 bool active = false; 1038 if (!set || !set->crtc) 1039 return -EINVAL; 1040 1041 dev = set->crtc->dev; 1042 1043 /* get a pm reference here */ 1044 ret = pm_runtime_get_sync(dev->dev); 1045 if (ret < 0 && ret != -EACCES) 1046 return ret; 1047 1048 ret = drm_crtc_helper_set_config(set); 1049 1050 drm = nouveau_drm(dev); 1051 1052 /* if we get here with no crtcs active then we can drop a reference */ 1053 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1054 if (crtc->enabled) 1055 active = true; 1056 } 1057 1058 pm_runtime_mark_last_busy(dev->dev); 1059 /* if we have active crtcs and we don't have a power ref, 1060 take the current one */ 1061 if (active && !drm->have_disp_power_ref) { 1062 drm->have_disp_power_ref = true; 1063 return ret; 1064 } 1065 /* if we have no active crtcs, then drop the power ref 1066 we got before */ 1067 if (!active && drm->have_disp_power_ref) { 1068 pm_runtime_put_autosuspend(dev->dev); 1069 drm->have_disp_power_ref = false; 1070 } 1071 /* drop the power reference we got coming in here */ 1072 pm_runtime_put_autosuspend(dev->dev); 1073 return ret; 1074 } 1075 1076 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1077 .cursor_set = nv04_crtc_cursor_set, 1078 .cursor_move = nv04_crtc_cursor_move, 1079 .gamma_set = nv_crtc_gamma_set, 1080 .set_config = nouveau_crtc_set_config, 1081 .page_flip = nouveau_crtc_page_flip, 1082 .destroy = nv_crtc_destroy, 1083 }; 1084 1085 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1086 .dpms = nv_crtc_dpms, 1087 .prepare = nv_crtc_prepare, 1088 .commit = nv_crtc_commit, 1089 .mode_set = nv_crtc_mode_set, 1090 .mode_set_base = nv04_crtc_mode_set_base, 1091 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1092 .load_lut = nv_crtc_gamma_load, 1093 .disable = nv_crtc_disable, 1094 }; 1095 1096 int 1097 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1098 { 1099 struct nouveau_crtc *nv_crtc; 1100 int ret, i; 1101 1102 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1103 if (!nv_crtc) 1104 return -ENOMEM; 1105 1106 for (i = 0; i < 256; i++) { 1107 nv_crtc->lut.r[i] = i << 8; 1108 nv_crtc->lut.g[i] = i << 8; 1109 nv_crtc->lut.b[i] = i << 8; 1110 } 1111 nv_crtc->lut.depth = 0; 1112 1113 nv_crtc->index = crtc_num; 1114 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1115 1116 nv_crtc->save = nv_crtc_save; 1117 nv_crtc->restore = nv_crtc_restore; 1118 1119 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); 1120 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1121 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1122 1123 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, 1124 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo); 1125 if (!ret) { 1126 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); 1127 if (!ret) { 1128 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1129 if (ret) 1130 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1131 } 1132 if (ret) 1133 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1134 } 1135 1136 nv04_cursor_init(nv_crtc); 1137 1138 return 0; 1139 } 1140