1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "nouveau_drv.h" 31 #include "nouveau_reg.h" 32 #include "nouveau_ttm.h" 33 #include "nouveau_bo.h" 34 #include "nouveau_gem.h" 35 #include "nouveau_encoder.h" 36 #include "nouveau_connector.h" 37 #include "nouveau_crtc.h" 38 #include "hw.h" 39 #include "nvreg.h" 40 #include "nouveau_fbcon.h" 41 #include "disp.h" 42 #include "nouveau_dma.h" 43 44 #include <subdev/bios/pll.h> 45 #include <subdev/clk.h> 46 47 static int 48 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 49 struct drm_framebuffer *old_fb); 50 51 static void 52 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 53 { 54 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 55 crtcstate->CRTC[index]); 56 } 57 58 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 59 { 60 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 61 struct drm_device *dev = crtc->dev; 62 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 63 64 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 65 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 66 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 67 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 69 } 70 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 71 } 72 73 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 74 { 75 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 76 struct drm_device *dev = crtc->dev; 77 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 78 79 nv_crtc->sharpness = level; 80 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 81 level += 0x40; 82 regp->ramdac_634 = level; 83 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 84 } 85 86 #define PLLSEL_VPLL1_MASK \ 87 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 88 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 89 #define PLLSEL_VPLL2_MASK \ 90 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 91 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 92 #define PLLSEL_TV_MASK \ 93 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 95 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 96 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 97 98 /* NV4x 0x40.. pll notes: 99 * gpu pll: 0x4000 + 0x4004 100 * ?gpu? pll: 0x4008 + 0x400c 101 * vpll1: 0x4010 + 0x4014 102 * vpll2: 0x4018 + 0x401c 103 * mpll: 0x4020 + 0x4024 104 * mpll: 0x4038 + 0x403c 105 * 106 * the first register of each pair has some unknown details: 107 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 108 * bits 20-23: (mpll) something to do with post divider? 109 * bits 28-31: related to single stage mode? (bit 8/12) 110 */ 111 112 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 113 { 114 struct drm_device *dev = crtc->dev; 115 struct nouveau_drm *drm = nouveau_drm(dev); 116 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 117 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 118 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 119 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 120 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 121 struct nvkm_pll_vals *pv = ®p->pllvals; 122 struct nvbios_pll pll_lim; 123 124 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 125 &pll_lim)) 126 return; 127 128 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 129 pv->NM2 = 0; 130 131 /* for newer nv4x the blob uses only the first stage of the vpll below a 132 * certain clock. for a certain nv4b this is 150MHz. since the max 133 * output frequency of the first stage for this card is 300MHz, it is 134 * assumed the threshold is given by vco1 maxfreq/2 135 */ 136 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 137 * not 8, others unknown), the blob always uses both plls. no problem 138 * has yet been observed in allowing the use a single stage pll on all 139 * nv43 however. the behaviour of single stage use is untested on nv40 140 */ 141 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 142 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 143 144 145 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 146 return; 147 148 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 149 150 /* The blob uses this always, so let's do the same */ 151 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 152 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 153 /* again nv40 and some nv43 act more like nv3x as described above */ 154 if (drm->client.device.info.chipset < 0x41) 155 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 156 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 157 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 158 159 if (pv->NM2) 160 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 161 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 162 else 163 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 164 pv->N1, pv->M1, pv->log2P); 165 166 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 167 } 168 169 static void 170 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 171 { 172 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 173 struct drm_device *dev = crtc->dev; 174 struct nouveau_drm *drm = nouveau_drm(dev); 175 unsigned char seq1 = 0, crtc17 = 0; 176 unsigned char crtc1A; 177 178 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 179 nv_crtc->index); 180 181 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 182 return; 183 184 nv_crtc->last_dpms = mode; 185 186 if (nv_two_heads(dev)) 187 NVSetOwner(dev, nv_crtc->index); 188 189 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 190 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 191 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 192 switch (mode) { 193 case DRM_MODE_DPMS_STANDBY: 194 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 195 seq1 = 0x20; 196 crtc17 = 0x80; 197 crtc1A |= 0x80; 198 break; 199 case DRM_MODE_DPMS_SUSPEND: 200 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 201 seq1 = 0x20; 202 crtc17 = 0x80; 203 crtc1A |= 0x40; 204 break; 205 case DRM_MODE_DPMS_OFF: 206 /* Screen: Off; HSync: Off, VSync: Off */ 207 seq1 = 0x20; 208 crtc17 = 0x00; 209 crtc1A |= 0xC0; 210 break; 211 case DRM_MODE_DPMS_ON: 212 default: 213 /* Screen: On; HSync: On, VSync: On */ 214 seq1 = 0x00; 215 crtc17 = 0x80; 216 break; 217 } 218 219 NVVgaSeqReset(dev, nv_crtc->index, true); 220 /* Each head has it's own sequencer, so we can turn it off when we want */ 221 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 222 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 223 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 224 mdelay(10); 225 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 226 NVVgaSeqReset(dev, nv_crtc->index, false); 227 228 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 229 } 230 231 static void 232 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 233 { 234 struct drm_device *dev = crtc->dev; 235 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 236 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 237 struct drm_framebuffer *fb = crtc->primary->fb; 238 239 /* Calculate our timings */ 240 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 241 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 242 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 243 int horizTotal = (mode->crtc_htotal >> 3) - 5; 244 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 245 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 246 int vertDisplay = mode->crtc_vdisplay - 1; 247 int vertStart = mode->crtc_vsync_start - 1; 248 int vertEnd = mode->crtc_vsync_end - 1; 249 int vertTotal = mode->crtc_vtotal - 2; 250 int vertBlankStart = mode->crtc_vdisplay - 1; 251 int vertBlankEnd = mode->crtc_vtotal - 1; 252 253 struct drm_encoder *encoder; 254 bool fp_output = false; 255 256 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 257 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 258 259 if (encoder->crtc == crtc && 260 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 261 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 262 fp_output = true; 263 } 264 265 if (fp_output) { 266 vertStart = vertTotal - 3; 267 vertEnd = vertTotal - 2; 268 vertBlankStart = vertStart; 269 horizStart = horizTotal - 5; 270 horizEnd = horizTotal - 2; 271 horizBlankEnd = horizTotal + 4; 272 #if 0 273 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 274 /* This reportedly works around some video overlay bandwidth problems */ 275 horizTotal += 2; 276 #endif 277 } 278 279 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 280 vertTotal |= 1; 281 282 #if 0 283 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 284 ErrorF("horizStart: 0x%X \n", horizStart); 285 ErrorF("horizEnd: 0x%X \n", horizEnd); 286 ErrorF("horizTotal: 0x%X \n", horizTotal); 287 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 288 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 289 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 290 ErrorF("vertStart: 0x%X \n", vertStart); 291 ErrorF("vertEnd: 0x%X \n", vertEnd); 292 ErrorF("vertTotal: 0x%X \n", vertTotal); 293 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 294 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 295 #endif 296 297 /* 298 * compute correct Hsync & Vsync polarity 299 */ 300 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 301 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 302 303 regp->MiscOutReg = 0x23; 304 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 305 regp->MiscOutReg |= 0x40; 306 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 307 regp->MiscOutReg |= 0x80; 308 } else { 309 int vdisplay = mode->vdisplay; 310 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 311 vdisplay *= 2; 312 if (mode->vscan > 1) 313 vdisplay *= mode->vscan; 314 if (vdisplay < 400) 315 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 316 else if (vdisplay < 480) 317 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 318 else if (vdisplay < 768) 319 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 320 else 321 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 322 } 323 324 /* 325 * Time Sequencer 326 */ 327 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 328 /* 0x20 disables the sequencer */ 329 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 330 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 331 else 332 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 333 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 334 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 335 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 336 337 /* 338 * CRTC 339 */ 340 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 341 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 342 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 343 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 344 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 345 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 346 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 347 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 348 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 349 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 350 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 351 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 352 (1 << 4) | 353 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 354 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 355 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 356 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 357 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 358 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 359 1 << 6 | 360 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 361 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 362 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 363 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 364 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 365 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 366 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 367 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 368 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 369 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 370 /* framebuffer can be larger than crtc scanout area. */ 371 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 372 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 373 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 374 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 375 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 376 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 377 378 /* 379 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 380 */ 381 382 /* framebuffer can be larger than crtc scanout area. */ 383 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 384 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 385 regp->CRTC[NV_CIO_CRE_42] = 386 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 387 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 388 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 389 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 390 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 391 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 392 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 393 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 394 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 395 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 396 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 397 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 398 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 399 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 400 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 401 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 402 403 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 404 horizTotal = (horizTotal >> 1) & ~1; 405 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 406 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 407 } else 408 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 409 410 /* 411 * Graphics Display Controller 412 */ 413 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 414 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 415 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 416 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 417 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 418 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 419 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 420 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 421 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 422 423 regp->Attribute[0] = 0x00; /* standard colormap translation */ 424 regp->Attribute[1] = 0x01; 425 regp->Attribute[2] = 0x02; 426 regp->Attribute[3] = 0x03; 427 regp->Attribute[4] = 0x04; 428 regp->Attribute[5] = 0x05; 429 regp->Attribute[6] = 0x06; 430 regp->Attribute[7] = 0x07; 431 regp->Attribute[8] = 0x08; 432 regp->Attribute[9] = 0x09; 433 regp->Attribute[10] = 0x0A; 434 regp->Attribute[11] = 0x0B; 435 regp->Attribute[12] = 0x0C; 436 regp->Attribute[13] = 0x0D; 437 regp->Attribute[14] = 0x0E; 438 regp->Attribute[15] = 0x0F; 439 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 440 /* Non-vga */ 441 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 442 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 443 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 444 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 445 } 446 447 /** 448 * Sets up registers for the given mode/adjusted_mode pair. 449 * 450 * The clocks, CRTCs and outputs attached to this CRTC must be off. 451 * 452 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 453 * be easily turned on/off after this. 454 */ 455 static void 456 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 457 { 458 struct drm_device *dev = crtc->dev; 459 struct nouveau_drm *drm = nouveau_drm(dev); 460 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 461 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 462 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 463 const struct drm_framebuffer *fb = crtc->primary->fb; 464 struct drm_encoder *encoder; 465 bool lvds_output = false, tmds_output = false, tv_output = false, 466 off_chip_digital = false; 467 468 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 469 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 470 bool digital = false; 471 472 if (encoder->crtc != crtc) 473 continue; 474 475 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 476 digital = lvds_output = true; 477 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 478 tv_output = true; 479 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 480 digital = tmds_output = true; 481 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 482 off_chip_digital = true; 483 } 484 485 /* Registers not directly related to the (s)vga mode */ 486 487 /* What is the meaning of this register? */ 488 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 489 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 490 491 regp->crtc_eng_ctrl = 0; 492 /* Except for rare conditions I2C is enabled on the primary crtc */ 493 if (nv_crtc->index == 0) 494 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 495 #if 0 496 /* Set overlay to desired crtc. */ 497 if (dev->overlayAdaptor) { 498 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 499 if (pPriv->overlayCRTC == nv_crtc->index) 500 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 501 } 502 #endif 503 504 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 505 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 506 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 507 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 508 if (drm->client.device.info.chipset >= 0x11) 509 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 510 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 511 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 512 513 /* Unblock some timings */ 514 regp->CRTC[NV_CIO_CRE_53] = 0; 515 regp->CRTC[NV_CIO_CRE_54] = 0; 516 517 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 518 if (lvds_output) 519 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 520 else if (tmds_output) 521 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 522 else 523 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 524 525 /* These values seem to vary */ 526 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 527 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 528 529 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 530 531 /* probably a scratch reg, but kept for cargo-cult purposes: 532 * bit0: crtc0?, head A 533 * bit6: lvds, head A 534 * bit7: (only in X), head A 535 */ 536 if (nv_crtc->index == 0) 537 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 538 539 /* The blob seems to take the current value from crtc 0, add 4 to that 540 * and reuse the old value for crtc 1 */ 541 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 542 if (!nv_crtc->index) 543 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 544 545 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 546 * 1 << 30 on 0x60.830), for no apparent reason */ 547 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 548 549 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 550 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 551 552 regp->crtc_830 = mode->crtc_vdisplay - 3; 553 regp->crtc_834 = mode->crtc_vdisplay - 1; 554 555 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 556 /* This is what the blob does */ 557 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 558 559 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 560 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 561 562 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 563 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 564 else 565 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 566 567 /* Some misc regs */ 568 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 569 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 570 regp->CRTC[NV_CIO_CRE_86] = 0x1; 571 } 572 573 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; 574 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 575 if (lvds_output || tmds_output || tv_output) 576 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 577 578 /* Generic PRAMDAC regs */ 579 580 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 581 /* Only bit that bios and blob set. */ 582 regp->nv10_cursync = (1 << 25); 583 584 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 585 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 586 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 587 if (fb->format->depth == 16) 588 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 589 if (drm->client.device.info.chipset >= 0x11) 590 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 591 592 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 593 regp->tv_setup = 0; 594 595 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 596 597 /* Some values the blob sets */ 598 regp->ramdac_8c0 = 0x100; 599 regp->ramdac_a20 = 0x0; 600 regp->ramdac_a24 = 0xfffff; 601 regp->ramdac_a34 = 0x1; 602 } 603 604 static int 605 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 606 { 607 struct nv04_display *disp = nv04_display(crtc->dev); 608 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); 609 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 610 int ret; 611 612 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false); 613 if (ret == 0) { 614 if (disp->image[nv_crtc->index]) 615 nouveau_bo_unpin(disp->image[nv_crtc->index]); 616 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); 617 } 618 619 return ret; 620 } 621 622 /** 623 * Sets up registers for the given mode/adjusted_mode pair. 624 * 625 * The clocks, CRTCs and outputs attached to this CRTC must be off. 626 * 627 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 628 * be easily turned on/off after this. 629 */ 630 static int 631 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 632 struct drm_display_mode *adjusted_mode, 633 int x, int y, struct drm_framebuffer *old_fb) 634 { 635 struct drm_device *dev = crtc->dev; 636 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 637 struct nouveau_drm *drm = nouveau_drm(dev); 638 int ret; 639 640 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 641 drm_mode_debug_printmodeline(adjusted_mode); 642 643 ret = nv_crtc_swap_fbs(crtc, old_fb); 644 if (ret) 645 return ret; 646 647 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 648 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 649 650 nv_crtc_mode_set_vga(crtc, adjusted_mode); 651 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 652 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 653 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 654 nv_crtc_mode_set_regs(crtc, adjusted_mode); 655 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 656 return 0; 657 } 658 659 static void nv_crtc_save(struct drm_crtc *crtc) 660 { 661 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 662 struct drm_device *dev = crtc->dev; 663 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 664 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 665 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 666 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 667 668 if (nv_two_heads(crtc->dev)) 669 NVSetOwner(crtc->dev, nv_crtc->index); 670 671 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 672 673 /* init some state to saved value */ 674 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 675 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 676 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 677 crtc_state->gpio_ext = crtc_saved->gpio_ext; 678 } 679 680 static void nv_crtc_restore(struct drm_crtc *crtc) 681 { 682 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 683 struct drm_device *dev = crtc->dev; 684 int head = nv_crtc->index; 685 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 686 687 if (nv_two_heads(crtc->dev)) 688 NVSetOwner(crtc->dev, head); 689 690 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 691 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 692 693 nv_crtc->last_dpms = NV_DPMS_CLEARED; 694 } 695 696 static void nv_crtc_prepare(struct drm_crtc *crtc) 697 { 698 struct drm_device *dev = crtc->dev; 699 struct nouveau_drm *drm = nouveau_drm(dev); 700 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 701 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 702 703 if (nv_two_heads(dev)) 704 NVSetOwner(dev, nv_crtc->index); 705 706 drm_crtc_vblank_off(crtc); 707 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 708 709 NVBlankScreen(dev, nv_crtc->index, true); 710 711 /* Some more preparation. */ 712 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 713 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 714 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 715 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 716 } 717 } 718 719 static void nv_crtc_commit(struct drm_crtc *crtc) 720 { 721 struct drm_device *dev = crtc->dev; 722 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 723 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 724 725 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 726 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 727 728 #ifdef __BIG_ENDIAN 729 /* turn on LFB swapping */ 730 { 731 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 732 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 733 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 734 } 735 #endif 736 737 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 738 drm_crtc_vblank_on(crtc); 739 } 740 741 static void nv_crtc_destroy(struct drm_crtc *crtc) 742 { 743 struct nv04_display *disp = nv04_display(crtc->dev); 744 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 745 746 if (!nv_crtc) 747 return; 748 749 drm_crtc_cleanup(crtc); 750 751 if (disp->image[nv_crtc->index]) 752 nouveau_bo_unpin(disp->image[nv_crtc->index]); 753 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 754 755 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 756 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 757 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 758 kfree(nv_crtc); 759 } 760 761 static void 762 nv_crtc_gamma_load(struct drm_crtc *crtc) 763 { 764 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 765 struct drm_device *dev = nv_crtc->base.dev; 766 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 767 u16 *r, *g, *b; 768 int i; 769 770 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 771 r = crtc->gamma_store; 772 g = r + crtc->gamma_size; 773 b = g + crtc->gamma_size; 774 775 for (i = 0; i < 256; i++) { 776 rgbs[i].r = *r++ >> 8; 777 rgbs[i].g = *g++ >> 8; 778 rgbs[i].b = *b++ >> 8; 779 } 780 781 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 782 } 783 784 static void 785 nv_crtc_disable(struct drm_crtc *crtc) 786 { 787 struct nv04_display *disp = nv04_display(crtc->dev); 788 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 789 if (disp->image[nv_crtc->index]) 790 nouveau_bo_unpin(disp->image[nv_crtc->index]); 791 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 792 } 793 794 static int 795 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 796 uint32_t size, 797 struct drm_modeset_acquire_ctx *ctx) 798 { 799 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 800 801 /* We need to know the depth before we upload, but it's possible to 802 * get called before a framebuffer is bound. If this is the case, 803 * mark the lut values as dirty by setting depth==0, and it'll be 804 * uploaded on the first mode_set_base() 805 */ 806 if (!nv_crtc->base.primary->fb) { 807 nv_crtc->lut.depth = 0; 808 return 0; 809 } 810 811 nv_crtc_gamma_load(crtc); 812 813 return 0; 814 } 815 816 static int 817 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 818 struct drm_framebuffer *passed_fb, 819 int x, int y, bool atomic) 820 { 821 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 822 struct drm_device *dev = crtc->dev; 823 struct nouveau_drm *drm = nouveau_drm(dev); 824 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 825 struct drm_framebuffer *drm_fb; 826 struct nouveau_framebuffer *fb; 827 int arb_burst, arb_lwm; 828 829 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 830 831 /* no fb bound */ 832 if (!atomic && !crtc->primary->fb) { 833 NV_DEBUG(drm, "No FB bound\n"); 834 return 0; 835 } 836 837 /* If atomic, we want to switch to the fb we were passed, so 838 * now we update pointers to do that. 839 */ 840 if (atomic) { 841 drm_fb = passed_fb; 842 fb = nouveau_framebuffer(passed_fb); 843 } else { 844 drm_fb = crtc->primary->fb; 845 fb = nouveau_framebuffer(crtc->primary->fb); 846 } 847 848 nv_crtc->fb.offset = fb->nvbo->bo.offset; 849 850 if (nv_crtc->lut.depth != drm_fb->format->depth) { 851 nv_crtc->lut.depth = drm_fb->format->depth; 852 nv_crtc_gamma_load(crtc); 853 } 854 855 /* Update the framebuffer format. */ 856 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 857 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; 858 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 859 if (drm_fb->format->depth == 16) 860 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 861 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 862 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 863 regp->ramdac_gen_ctrl); 864 865 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 866 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 867 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 868 regp->CRTC[NV_CIO_CRE_42] = 869 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 870 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 871 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 872 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 873 874 /* Update the framebuffer location. */ 875 regp->fb_start = nv_crtc->fb.offset & ~3; 876 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); 877 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 878 879 /* Update the arbitration parameters. */ 880 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, 881 &arb_burst, &arb_lwm); 882 883 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 884 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 885 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 886 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 887 888 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 889 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 891 } 892 893 return 0; 894 } 895 896 static int 897 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 898 struct drm_framebuffer *old_fb) 899 { 900 int ret = nv_crtc_swap_fbs(crtc, old_fb); 901 if (ret) 902 return ret; 903 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 904 } 905 906 static int 907 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 908 struct drm_framebuffer *fb, 909 int x, int y, enum mode_set_atomic state) 910 { 911 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 912 struct drm_device *dev = drm->dev; 913 914 if (state == ENTER_ATOMIC_MODE_SET) 915 nouveau_fbcon_accel_save_disable(dev); 916 else 917 nouveau_fbcon_accel_restore(dev); 918 919 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 920 } 921 922 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 923 struct nouveau_bo *dst) 924 { 925 int width = nv_cursor_width(dev); 926 uint32_t pixel; 927 int i, j; 928 929 for (i = 0; i < width; i++) { 930 for (j = 0; j < width; j++) { 931 pixel = nouveau_bo_rd32(src, i*64 + j); 932 933 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 934 | (pixel & 0xf80000) >> 9 935 | (pixel & 0xf800) >> 6 936 | (pixel & 0xf8) >> 3); 937 } 938 } 939 } 940 941 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 942 struct nouveau_bo *dst) 943 { 944 uint32_t pixel; 945 int alpha, i; 946 947 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 948 * cursors (though NPM in combination with fp dithering may not work on 949 * nv11, from "nv" driver history) 950 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 951 * blob uses, however we get given PM cursors so we use PM mode 952 */ 953 for (i = 0; i < 64 * 64; i++) { 954 pixel = nouveau_bo_rd32(src, i); 955 956 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 957 * than" shouldn't happen; fix "equal to" case by adding one to 958 * alpha channel (slightly inaccurate, but so is attempting to 959 * get back to NPM images, due to limits of integer precision) 960 */ 961 alpha = pixel >> 24; 962 if (alpha > 0 && alpha < 255) 963 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 964 965 #ifdef __BIG_ENDIAN 966 { 967 struct nouveau_drm *drm = nouveau_drm(dev); 968 969 if (drm->client.device.info.chipset == 0x11) { 970 pixel = ((pixel & 0x000000ff) << 24) | 971 ((pixel & 0x0000ff00) << 8) | 972 ((pixel & 0x00ff0000) >> 8) | 973 ((pixel & 0xff000000) >> 24); 974 } 975 } 976 #endif 977 978 nouveau_bo_wr32(dst, i, pixel); 979 } 980 } 981 982 static int 983 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 984 uint32_t buffer_handle, uint32_t width, uint32_t height) 985 { 986 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 987 struct drm_device *dev = drm->dev; 988 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 989 struct nouveau_bo *cursor = NULL; 990 struct drm_gem_object *gem; 991 int ret = 0; 992 993 if (!buffer_handle) { 994 nv_crtc->cursor.hide(nv_crtc, true); 995 return 0; 996 } 997 998 if (width != 64 || height != 64) 999 return -EINVAL; 1000 1001 gem = drm_gem_object_lookup(file_priv, buffer_handle); 1002 if (!gem) 1003 return -ENOENT; 1004 cursor = nouveau_gem_object(gem); 1005 1006 ret = nouveau_bo_map(cursor); 1007 if (ret) 1008 goto out; 1009 1010 if (drm->client.device.info.chipset >= 0x11) 1011 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1012 else 1013 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1014 1015 nouveau_bo_unmap(cursor); 1016 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 1017 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1018 nv_crtc->cursor.show(nv_crtc, true); 1019 out: 1020 drm_gem_object_put_unlocked(gem); 1021 return ret; 1022 } 1023 1024 static int 1025 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1026 { 1027 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1028 1029 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1030 return 0; 1031 } 1032 1033 struct nv04_page_flip_state { 1034 struct list_head head; 1035 struct drm_pending_vblank_event *event; 1036 struct drm_crtc *crtc; 1037 int bpp, pitch; 1038 u64 offset; 1039 }; 1040 1041 static int 1042 nv04_finish_page_flip(struct nouveau_channel *chan, 1043 struct nv04_page_flip_state *ps) 1044 { 1045 struct nouveau_fence_chan *fctx = chan->fence; 1046 struct nouveau_drm *drm = chan->drm; 1047 struct drm_device *dev = drm->dev; 1048 struct nv04_page_flip_state *s; 1049 unsigned long flags; 1050 1051 spin_lock_irqsave(&dev->event_lock, flags); 1052 1053 if (list_empty(&fctx->flip)) { 1054 NV_ERROR(drm, "unexpected pageflip\n"); 1055 spin_unlock_irqrestore(&dev->event_lock, flags); 1056 return -EINVAL; 1057 } 1058 1059 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head); 1060 if (s->event) { 1061 drm_crtc_arm_vblank_event(s->crtc, s->event); 1062 } else { 1063 /* Give up ownership of vblank for page-flipped crtc */ 1064 drm_crtc_vblank_put(s->crtc); 1065 } 1066 1067 list_del(&s->head); 1068 if (ps) 1069 *ps = *s; 1070 kfree(s); 1071 1072 spin_unlock_irqrestore(&dev->event_lock, flags); 1073 return 0; 1074 } 1075 1076 int 1077 nv04_flip_complete(struct nvif_notify *notify) 1078 { 1079 struct nouveau_cli *cli = (void *)notify->object->client; 1080 struct nouveau_drm *drm = cli->drm; 1081 struct nouveau_channel *chan = drm->channel; 1082 struct nv04_page_flip_state state; 1083 1084 if (!nv04_finish_page_flip(chan, &state)) { 1085 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), 1086 state.offset + state.crtc->y * 1087 state.pitch + state.crtc->x * 1088 state.bpp / 8); 1089 } 1090 1091 return NVIF_NOTIFY_KEEP; 1092 } 1093 1094 static int 1095 nv04_page_flip_emit(struct nouveau_channel *chan, 1096 struct nouveau_bo *old_bo, 1097 struct nouveau_bo *new_bo, 1098 struct nv04_page_flip_state *s, 1099 struct nouveau_fence **pfence) 1100 { 1101 struct nouveau_fence_chan *fctx = chan->fence; 1102 struct nouveau_drm *drm = chan->drm; 1103 struct drm_device *dev = drm->dev; 1104 unsigned long flags; 1105 int ret; 1106 1107 /* Queue it to the pending list */ 1108 spin_lock_irqsave(&dev->event_lock, flags); 1109 list_add_tail(&s->head, &fctx->flip); 1110 spin_unlock_irqrestore(&dev->event_lock, flags); 1111 1112 /* Synchronize with the old framebuffer */ 1113 ret = nouveau_fence_sync(old_bo, chan, false, false); 1114 if (ret) 1115 goto fail; 1116 1117 /* Emit the pageflip */ 1118 ret = RING_SPACE(chan, 2); 1119 if (ret) 1120 goto fail; 1121 1122 BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); 1123 OUT_RING (chan, 0x00000000); 1124 FIRE_RING (chan); 1125 1126 ret = nouveau_fence_new(chan, false, pfence); 1127 if (ret) 1128 goto fail; 1129 1130 return 0; 1131 fail: 1132 spin_lock_irqsave(&dev->event_lock, flags); 1133 list_del(&s->head); 1134 spin_unlock_irqrestore(&dev->event_lock, flags); 1135 return ret; 1136 } 1137 1138 static int 1139 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1140 struct drm_pending_vblank_event *event, u32 flags, 1141 struct drm_modeset_acquire_ctx *ctx) 1142 { 1143 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; 1144 struct drm_device *dev = crtc->dev; 1145 struct nouveau_drm *drm = nouveau_drm(dev); 1146 struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo; 1147 struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; 1148 struct nv04_page_flip_state *s; 1149 struct nouveau_channel *chan; 1150 struct nouveau_cli *cli; 1151 struct nouveau_fence *fence; 1152 struct nv04_display *dispnv04 = nv04_display(dev); 1153 int head = nouveau_crtc(crtc)->index; 1154 int ret; 1155 1156 chan = drm->channel; 1157 if (!chan) 1158 return -ENODEV; 1159 cli = (void *)chan->user.client; 1160 1161 s = kzalloc(sizeof(*s), GFP_KERNEL); 1162 if (!s) 1163 return -ENOMEM; 1164 1165 if (new_bo != old_bo) { 1166 ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM, true); 1167 if (ret) 1168 goto fail_free; 1169 } 1170 1171 mutex_lock(&cli->mutex); 1172 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL); 1173 if (ret) 1174 goto fail_unpin; 1175 1176 /* synchronise rendering channel with the kernel's channel */ 1177 ret = nouveau_fence_sync(new_bo, chan, false, true); 1178 if (ret) { 1179 ttm_bo_unreserve(&new_bo->bo); 1180 goto fail_unpin; 1181 } 1182 1183 if (new_bo != old_bo) { 1184 ttm_bo_unreserve(&new_bo->bo); 1185 1186 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL); 1187 if (ret) 1188 goto fail_unpin; 1189 } 1190 1191 /* Initialize a page flip struct */ 1192 *s = (struct nv04_page_flip_state) 1193 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], 1194 new_bo->bo.offset }; 1195 1196 /* Keep vblanks on during flip, for the target crtc of this flip */ 1197 drm_crtc_vblank_get(crtc); 1198 1199 /* Emit a page flip */ 1200 if (swap_interval) { 1201 ret = RING_SPACE(chan, 8); 1202 if (ret) 1203 goto fail_unreserve; 1204 1205 BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); 1206 OUT_RING (chan, 0); 1207 BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); 1208 OUT_RING (chan, head); 1209 BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); 1210 OUT_RING (chan, 0); 1211 BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); 1212 OUT_RING (chan, 0); 1213 } 1214 1215 nouveau_bo_ref(new_bo, &dispnv04->image[head]); 1216 1217 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence); 1218 if (ret) 1219 goto fail_unreserve; 1220 mutex_unlock(&cli->mutex); 1221 1222 /* Update the crtc struct and cleanup */ 1223 crtc->primary->fb = fb; 1224 1225 nouveau_bo_fence(old_bo, fence, false); 1226 ttm_bo_unreserve(&old_bo->bo); 1227 if (old_bo != new_bo) 1228 nouveau_bo_unpin(old_bo); 1229 nouveau_fence_unref(&fence); 1230 return 0; 1231 1232 fail_unreserve: 1233 drm_crtc_vblank_put(crtc); 1234 ttm_bo_unreserve(&old_bo->bo); 1235 fail_unpin: 1236 mutex_unlock(&cli->mutex); 1237 if (old_bo != new_bo) 1238 nouveau_bo_unpin(new_bo); 1239 fail_free: 1240 kfree(s); 1241 return ret; 1242 } 1243 1244 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1245 .cursor_set = nv04_crtc_cursor_set, 1246 .cursor_move = nv04_crtc_cursor_move, 1247 .gamma_set = nv_crtc_gamma_set, 1248 .set_config = drm_crtc_helper_set_config, 1249 .page_flip = nv04_crtc_page_flip, 1250 .destroy = nv_crtc_destroy, 1251 }; 1252 1253 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1254 .dpms = nv_crtc_dpms, 1255 .prepare = nv_crtc_prepare, 1256 .commit = nv_crtc_commit, 1257 .mode_set = nv_crtc_mode_set, 1258 .mode_set_base = nv04_crtc_mode_set_base, 1259 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1260 .disable = nv_crtc_disable, 1261 }; 1262 1263 static const uint32_t modeset_formats[] = { 1264 DRM_FORMAT_XRGB8888, 1265 DRM_FORMAT_RGB565, 1266 DRM_FORMAT_XRGB1555, 1267 }; 1268 1269 static struct drm_plane * 1270 create_primary_plane(struct drm_device *dev) 1271 { 1272 struct drm_plane *primary; 1273 int ret; 1274 1275 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 1276 if (primary == NULL) { 1277 DRM_DEBUG_KMS("Failed to allocate primary plane\n"); 1278 return NULL; 1279 } 1280 1281 /* possible_crtc's will be filled in later by crtc_init */ 1282 ret = drm_universal_plane_init(dev, primary, 0, 1283 &drm_primary_helper_funcs, 1284 modeset_formats, 1285 ARRAY_SIZE(modeset_formats), NULL, 1286 DRM_PLANE_TYPE_PRIMARY, NULL); 1287 if (ret) { 1288 kfree(primary); 1289 primary = NULL; 1290 } 1291 1292 return primary; 1293 } 1294 1295 int 1296 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1297 { 1298 struct nouveau_crtc *nv_crtc; 1299 int ret; 1300 1301 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1302 if (!nv_crtc) 1303 return -ENOMEM; 1304 1305 nv_crtc->lut.depth = 0; 1306 1307 nv_crtc->index = crtc_num; 1308 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1309 1310 nv_crtc->save = nv_crtc_save; 1311 nv_crtc->restore = nv_crtc_restore; 1312 1313 drm_crtc_init_with_planes(dev, &nv_crtc->base, 1314 create_primary_plane(dev), NULL, 1315 &nv04_crtc_funcs, NULL); 1316 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1317 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1318 1319 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, 1320 TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, 1321 &nv_crtc->cursor.nvbo); 1322 if (!ret) { 1323 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); 1324 if (!ret) { 1325 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1326 if (ret) 1327 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1328 } 1329 if (ret) 1330 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1331 } 1332 1333 nv04_cursor_init(nv_crtc); 1334 1335 return 0; 1336 } 1337