1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "nouveau_drv.h" 31 #include "nouveau_reg.h" 32 #include "nouveau_ttm.h" 33 #include "nouveau_bo.h" 34 #include "nouveau_gem.h" 35 #include "nouveau_encoder.h" 36 #include "nouveau_connector.h" 37 #include "nouveau_crtc.h" 38 #include "hw.h" 39 #include "nvreg.h" 40 #include "nouveau_fbcon.h" 41 #include "disp.h" 42 #include "nouveau_dma.h" 43 44 #include <subdev/bios/pll.h> 45 #include <subdev/clk.h> 46 47 #include <nvif/event.h> 48 #include <nvif/cl0046.h> 49 50 static int 51 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 52 struct drm_framebuffer *old_fb); 53 54 static void 55 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 56 { 57 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 58 crtcstate->CRTC[index]); 59 } 60 61 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 62 { 63 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 64 struct drm_device *dev = crtc->dev; 65 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 66 67 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 68 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 69 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 70 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 71 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 72 } 73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 74 } 75 76 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 77 { 78 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 79 struct drm_device *dev = crtc->dev; 80 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 81 82 nv_crtc->sharpness = level; 83 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 84 level += 0x40; 85 regp->ramdac_634 = level; 86 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 87 } 88 89 #define PLLSEL_VPLL1_MASK \ 90 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 91 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 92 #define PLLSEL_VPLL2_MASK \ 93 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 94 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 95 #define PLLSEL_TV_MASK \ 96 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 97 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 98 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 99 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 100 101 /* NV4x 0x40.. pll notes: 102 * gpu pll: 0x4000 + 0x4004 103 * ?gpu? pll: 0x4008 + 0x400c 104 * vpll1: 0x4010 + 0x4014 105 * vpll2: 0x4018 + 0x401c 106 * mpll: 0x4020 + 0x4024 107 * mpll: 0x4038 + 0x403c 108 * 109 * the first register of each pair has some unknown details: 110 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 111 * bits 20-23: (mpll) something to do with post divider? 112 * bits 28-31: related to single stage mode? (bit 8/12) 113 */ 114 115 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 116 { 117 struct drm_device *dev = crtc->dev; 118 struct nouveau_drm *drm = nouveau_drm(dev); 119 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 120 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 121 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 122 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 123 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 124 struct nvkm_pll_vals *pv = ®p->pllvals; 125 struct nvbios_pll pll_lim; 126 127 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 128 &pll_lim)) 129 return; 130 131 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 132 pv->NM2 = 0; 133 134 /* for newer nv4x the blob uses only the first stage of the vpll below a 135 * certain clock. for a certain nv4b this is 150MHz. since the max 136 * output frequency of the first stage for this card is 300MHz, it is 137 * assumed the threshold is given by vco1 maxfreq/2 138 */ 139 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 140 * not 8, others unknown), the blob always uses both plls. no problem 141 * has yet been observed in allowing the use a single stage pll on all 142 * nv43 however. the behaviour of single stage use is untested on nv40 143 */ 144 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 145 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 146 147 148 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 149 return; 150 151 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 152 153 /* The blob uses this always, so let's do the same */ 154 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 155 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 156 /* again nv40 and some nv43 act more like nv3x as described above */ 157 if (drm->client.device.info.chipset < 0x41) 158 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 159 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 160 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 161 162 if (pv->NM2) 163 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 164 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 165 else 166 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 167 pv->N1, pv->M1, pv->log2P); 168 169 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 170 } 171 172 static void 173 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 174 { 175 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 176 struct drm_device *dev = crtc->dev; 177 struct nouveau_drm *drm = nouveau_drm(dev); 178 unsigned char seq1 = 0, crtc17 = 0; 179 unsigned char crtc1A; 180 181 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 182 nv_crtc->index); 183 184 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 185 return; 186 187 nv_crtc->last_dpms = mode; 188 189 if (nv_two_heads(dev)) 190 NVSetOwner(dev, nv_crtc->index); 191 192 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 193 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 194 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 195 switch (mode) { 196 case DRM_MODE_DPMS_STANDBY: 197 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 198 seq1 = 0x20; 199 crtc17 = 0x80; 200 crtc1A |= 0x80; 201 break; 202 case DRM_MODE_DPMS_SUSPEND: 203 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 204 seq1 = 0x20; 205 crtc17 = 0x80; 206 crtc1A |= 0x40; 207 break; 208 case DRM_MODE_DPMS_OFF: 209 /* Screen: Off; HSync: Off, VSync: Off */ 210 seq1 = 0x20; 211 crtc17 = 0x00; 212 crtc1A |= 0xC0; 213 break; 214 case DRM_MODE_DPMS_ON: 215 default: 216 /* Screen: On; HSync: On, VSync: On */ 217 seq1 = 0x00; 218 crtc17 = 0x80; 219 break; 220 } 221 222 NVVgaSeqReset(dev, nv_crtc->index, true); 223 /* Each head has it's own sequencer, so we can turn it off when we want */ 224 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 225 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 226 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 227 mdelay(10); 228 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 229 NVVgaSeqReset(dev, nv_crtc->index, false); 230 231 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 232 } 233 234 static void 235 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 236 { 237 struct drm_device *dev = crtc->dev; 238 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 239 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 240 struct drm_framebuffer *fb = crtc->primary->fb; 241 242 /* Calculate our timings */ 243 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 244 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 245 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 246 int horizTotal = (mode->crtc_htotal >> 3) - 5; 247 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 248 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 249 int vertDisplay = mode->crtc_vdisplay - 1; 250 int vertStart = mode->crtc_vsync_start - 1; 251 int vertEnd = mode->crtc_vsync_end - 1; 252 int vertTotal = mode->crtc_vtotal - 2; 253 int vertBlankStart = mode->crtc_vdisplay - 1; 254 int vertBlankEnd = mode->crtc_vtotal - 1; 255 256 struct drm_encoder *encoder; 257 bool fp_output = false; 258 259 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 260 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 261 262 if (encoder->crtc == crtc && 263 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 264 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 265 fp_output = true; 266 } 267 268 if (fp_output) { 269 vertStart = vertTotal - 3; 270 vertEnd = vertTotal - 2; 271 vertBlankStart = vertStart; 272 horizStart = horizTotal - 5; 273 horizEnd = horizTotal - 2; 274 horizBlankEnd = horizTotal + 4; 275 #if 0 276 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 277 /* This reportedly works around some video overlay bandwidth problems */ 278 horizTotal += 2; 279 #endif 280 } 281 282 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 283 vertTotal |= 1; 284 285 #if 0 286 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 287 ErrorF("horizStart: 0x%X \n", horizStart); 288 ErrorF("horizEnd: 0x%X \n", horizEnd); 289 ErrorF("horizTotal: 0x%X \n", horizTotal); 290 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 291 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 292 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 293 ErrorF("vertStart: 0x%X \n", vertStart); 294 ErrorF("vertEnd: 0x%X \n", vertEnd); 295 ErrorF("vertTotal: 0x%X \n", vertTotal); 296 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 297 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 298 #endif 299 300 /* 301 * compute correct Hsync & Vsync polarity 302 */ 303 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 304 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 305 306 regp->MiscOutReg = 0x23; 307 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 308 regp->MiscOutReg |= 0x40; 309 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 310 regp->MiscOutReg |= 0x80; 311 } else { 312 int vdisplay = mode->vdisplay; 313 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 314 vdisplay *= 2; 315 if (mode->vscan > 1) 316 vdisplay *= mode->vscan; 317 if (vdisplay < 400) 318 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 319 else if (vdisplay < 480) 320 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 321 else if (vdisplay < 768) 322 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 323 else 324 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 325 } 326 327 /* 328 * Time Sequencer 329 */ 330 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 331 /* 0x20 disables the sequencer */ 332 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 333 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 334 else 335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 336 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 337 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 338 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 339 340 /* 341 * CRTC 342 */ 343 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 344 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 345 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 346 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 347 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 348 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 349 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 350 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 351 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 352 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 353 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 354 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 355 (1 << 4) | 356 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 357 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 358 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 359 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 360 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 361 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 362 1 << 6 | 363 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 364 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 365 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 366 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 367 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 368 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 369 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 370 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 371 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 372 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 373 /* framebuffer can be larger than crtc scanout area. */ 374 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 375 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 376 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 377 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 378 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 379 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 380 381 /* 382 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 383 */ 384 385 /* framebuffer can be larger than crtc scanout area. */ 386 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 387 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 388 regp->CRTC[NV_CIO_CRE_42] = 389 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 390 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 391 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 392 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 393 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 394 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 395 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 396 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 397 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 398 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 399 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 400 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 401 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 402 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 403 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 404 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 405 406 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 407 horizTotal = (horizTotal >> 1) & ~1; 408 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 409 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 410 } else 411 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 412 413 /* 414 * Graphics Display Controller 415 */ 416 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 417 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 418 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 419 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 420 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 421 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 422 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 423 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 424 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 425 426 regp->Attribute[0] = 0x00; /* standard colormap translation */ 427 regp->Attribute[1] = 0x01; 428 regp->Attribute[2] = 0x02; 429 regp->Attribute[3] = 0x03; 430 regp->Attribute[4] = 0x04; 431 regp->Attribute[5] = 0x05; 432 regp->Attribute[6] = 0x06; 433 regp->Attribute[7] = 0x07; 434 regp->Attribute[8] = 0x08; 435 regp->Attribute[9] = 0x09; 436 regp->Attribute[10] = 0x0A; 437 regp->Attribute[11] = 0x0B; 438 regp->Attribute[12] = 0x0C; 439 regp->Attribute[13] = 0x0D; 440 regp->Attribute[14] = 0x0E; 441 regp->Attribute[15] = 0x0F; 442 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 443 /* Non-vga */ 444 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 445 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 446 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 447 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 448 } 449 450 /** 451 * Sets up registers for the given mode/adjusted_mode pair. 452 * 453 * The clocks, CRTCs and outputs attached to this CRTC must be off. 454 * 455 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 456 * be easily turned on/off after this. 457 */ 458 static void 459 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 460 { 461 struct drm_device *dev = crtc->dev; 462 struct nouveau_drm *drm = nouveau_drm(dev); 463 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 464 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 465 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 466 const struct drm_framebuffer *fb = crtc->primary->fb; 467 struct drm_encoder *encoder; 468 bool lvds_output = false, tmds_output = false, tv_output = false, 469 off_chip_digital = false; 470 471 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 472 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 473 bool digital = false; 474 475 if (encoder->crtc != crtc) 476 continue; 477 478 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 479 digital = lvds_output = true; 480 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 481 tv_output = true; 482 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 483 digital = tmds_output = true; 484 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 485 off_chip_digital = true; 486 } 487 488 /* Registers not directly related to the (s)vga mode */ 489 490 /* What is the meaning of this register? */ 491 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 492 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 493 494 regp->crtc_eng_ctrl = 0; 495 /* Except for rare conditions I2C is enabled on the primary crtc */ 496 if (nv_crtc->index == 0) 497 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 498 #if 0 499 /* Set overlay to desired crtc. */ 500 if (dev->overlayAdaptor) { 501 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 502 if (pPriv->overlayCRTC == nv_crtc->index) 503 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 504 } 505 #endif 506 507 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 508 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 509 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 510 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 511 if (drm->client.device.info.chipset >= 0x11) 512 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 513 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 515 516 /* Unblock some timings */ 517 regp->CRTC[NV_CIO_CRE_53] = 0; 518 regp->CRTC[NV_CIO_CRE_54] = 0; 519 520 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 521 if (lvds_output) 522 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 523 else if (tmds_output) 524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 525 else 526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 527 528 /* These values seem to vary */ 529 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 530 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 531 532 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 533 534 /* probably a scratch reg, but kept for cargo-cult purposes: 535 * bit0: crtc0?, head A 536 * bit6: lvds, head A 537 * bit7: (only in X), head A 538 */ 539 if (nv_crtc->index == 0) 540 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 541 542 /* The blob seems to take the current value from crtc 0, add 4 to that 543 * and reuse the old value for crtc 1 */ 544 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 545 if (!nv_crtc->index) 546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 547 548 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 549 * 1 << 30 on 0x60.830), for no apparent reason */ 550 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 551 552 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 553 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 554 555 regp->crtc_830 = mode->crtc_vdisplay - 3; 556 regp->crtc_834 = mode->crtc_vdisplay - 1; 557 558 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 559 /* This is what the blob does */ 560 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 561 562 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 563 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 564 565 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 566 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 567 else 568 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 569 570 /* Some misc regs */ 571 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 572 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 573 regp->CRTC[NV_CIO_CRE_86] = 0x1; 574 } 575 576 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; 577 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 578 if (lvds_output || tmds_output || tv_output) 579 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 580 581 /* Generic PRAMDAC regs */ 582 583 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 584 /* Only bit that bios and blob set. */ 585 regp->nv10_cursync = (1 << 25); 586 587 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 588 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 589 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 590 if (fb->format->depth == 16) 591 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 592 if (drm->client.device.info.chipset >= 0x11) 593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 594 595 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 596 regp->tv_setup = 0; 597 598 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 599 600 /* Some values the blob sets */ 601 regp->ramdac_8c0 = 0x100; 602 regp->ramdac_a20 = 0x0; 603 regp->ramdac_a24 = 0xfffff; 604 regp->ramdac_a34 = 0x1; 605 } 606 607 static int 608 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 609 { 610 struct nv04_display *disp = nv04_display(crtc->dev); 611 struct drm_framebuffer *fb = crtc->primary->fb; 612 struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]); 613 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 614 int ret; 615 616 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, false); 617 if (ret == 0) { 618 if (disp->image[nv_crtc->index]) 619 nouveau_bo_unpin(disp->image[nv_crtc->index]); 620 nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]); 621 } 622 623 return ret; 624 } 625 626 /** 627 * Sets up registers for the given mode/adjusted_mode pair. 628 * 629 * The clocks, CRTCs and outputs attached to this CRTC must be off. 630 * 631 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 632 * be easily turned on/off after this. 633 */ 634 static int 635 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 636 struct drm_display_mode *adjusted_mode, 637 int x, int y, struct drm_framebuffer *old_fb) 638 { 639 struct drm_device *dev = crtc->dev; 640 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 641 struct nouveau_drm *drm = nouveau_drm(dev); 642 int ret; 643 644 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 645 drm_mode_debug_printmodeline(adjusted_mode); 646 647 ret = nv_crtc_swap_fbs(crtc, old_fb); 648 if (ret) 649 return ret; 650 651 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 652 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 653 654 nv_crtc_mode_set_vga(crtc, adjusted_mode); 655 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 656 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 657 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 658 nv_crtc_mode_set_regs(crtc, adjusted_mode); 659 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 660 return 0; 661 } 662 663 static void nv_crtc_save(struct drm_crtc *crtc) 664 { 665 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 666 struct drm_device *dev = crtc->dev; 667 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 668 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 669 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 670 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 671 672 if (nv_two_heads(crtc->dev)) 673 NVSetOwner(crtc->dev, nv_crtc->index); 674 675 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 676 677 /* init some state to saved value */ 678 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 679 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 680 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 681 crtc_state->gpio_ext = crtc_saved->gpio_ext; 682 } 683 684 static void nv_crtc_restore(struct drm_crtc *crtc) 685 { 686 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 687 struct drm_device *dev = crtc->dev; 688 int head = nv_crtc->index; 689 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 690 691 if (nv_two_heads(crtc->dev)) 692 NVSetOwner(crtc->dev, head); 693 694 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 695 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 696 697 nv_crtc->last_dpms = NV_DPMS_CLEARED; 698 } 699 700 static void nv_crtc_prepare(struct drm_crtc *crtc) 701 { 702 struct drm_device *dev = crtc->dev; 703 struct nouveau_drm *drm = nouveau_drm(dev); 704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 705 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 706 707 if (nv_two_heads(dev)) 708 NVSetOwner(dev, nv_crtc->index); 709 710 drm_crtc_vblank_off(crtc); 711 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 712 713 NVBlankScreen(dev, nv_crtc->index, true); 714 715 /* Some more preparation. */ 716 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 717 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 718 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 719 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 720 } 721 } 722 723 static void nv_crtc_commit(struct drm_crtc *crtc) 724 { 725 struct drm_device *dev = crtc->dev; 726 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 727 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 728 729 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 730 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 731 732 #ifdef __BIG_ENDIAN 733 /* turn on LFB swapping */ 734 { 735 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 736 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 737 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 738 } 739 #endif 740 741 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 742 drm_crtc_vblank_on(crtc); 743 } 744 745 static void nv_crtc_destroy(struct drm_crtc *crtc) 746 { 747 struct nv04_display *disp = nv04_display(crtc->dev); 748 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 749 750 if (!nv_crtc) 751 return; 752 753 drm_crtc_cleanup(crtc); 754 755 if (disp->image[nv_crtc->index]) 756 nouveau_bo_unpin(disp->image[nv_crtc->index]); 757 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 758 759 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 760 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 761 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 762 nvif_notify_fini(&nv_crtc->vblank); 763 kfree(nv_crtc); 764 } 765 766 static void 767 nv_crtc_gamma_load(struct drm_crtc *crtc) 768 { 769 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 770 struct drm_device *dev = nv_crtc->base.dev; 771 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 772 u16 *r, *g, *b; 773 int i; 774 775 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 776 r = crtc->gamma_store; 777 g = r + crtc->gamma_size; 778 b = g + crtc->gamma_size; 779 780 for (i = 0; i < 256; i++) { 781 rgbs[i].r = *r++ >> 8; 782 rgbs[i].g = *g++ >> 8; 783 rgbs[i].b = *b++ >> 8; 784 } 785 786 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 787 } 788 789 static void 790 nv_crtc_disable(struct drm_crtc *crtc) 791 { 792 struct nv04_display *disp = nv04_display(crtc->dev); 793 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 794 if (disp->image[nv_crtc->index]) 795 nouveau_bo_unpin(disp->image[nv_crtc->index]); 796 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 797 } 798 799 static int 800 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 801 uint32_t size, 802 struct drm_modeset_acquire_ctx *ctx) 803 { 804 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 805 806 /* We need to know the depth before we upload, but it's possible to 807 * get called before a framebuffer is bound. If this is the case, 808 * mark the lut values as dirty by setting depth==0, and it'll be 809 * uploaded on the first mode_set_base() 810 */ 811 if (!nv_crtc->base.primary->fb) { 812 nv_crtc->lut.depth = 0; 813 return 0; 814 } 815 816 nv_crtc_gamma_load(crtc); 817 818 return 0; 819 } 820 821 static int 822 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 823 struct drm_framebuffer *passed_fb, 824 int x, int y, bool atomic) 825 { 826 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 827 struct drm_device *dev = crtc->dev; 828 struct nouveau_drm *drm = nouveau_drm(dev); 829 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 830 struct nouveau_bo *nvbo; 831 struct drm_framebuffer *drm_fb; 832 int arb_burst, arb_lwm; 833 834 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 835 836 /* no fb bound */ 837 if (!atomic && !crtc->primary->fb) { 838 NV_DEBUG(drm, "No FB bound\n"); 839 return 0; 840 } 841 842 /* If atomic, we want to switch to the fb we were passed, so 843 * now we update pointers to do that. 844 */ 845 if (atomic) { 846 drm_fb = passed_fb; 847 } else { 848 drm_fb = crtc->primary->fb; 849 } 850 851 nvbo = nouveau_gem_object(drm_fb->obj[0]); 852 nv_crtc->fb.offset = nvbo->offset; 853 854 if (nv_crtc->lut.depth != drm_fb->format->depth) { 855 nv_crtc->lut.depth = drm_fb->format->depth; 856 nv_crtc_gamma_load(crtc); 857 } 858 859 /* Update the framebuffer format. */ 860 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 861 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; 862 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 863 if (drm_fb->format->depth == 16) 864 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 865 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 866 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 867 regp->ramdac_gen_ctrl); 868 869 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 870 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 871 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 872 regp->CRTC[NV_CIO_CRE_42] = 873 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 874 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 875 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 876 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 877 878 /* Update the framebuffer location. */ 879 regp->fb_start = nv_crtc->fb.offset & ~3; 880 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); 881 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 882 883 /* Update the arbitration parameters. */ 884 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, 885 &arb_burst, &arb_lwm); 886 887 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 888 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 889 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 891 892 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 893 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 894 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 895 } 896 897 return 0; 898 } 899 900 static int 901 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 902 struct drm_framebuffer *old_fb) 903 { 904 int ret = nv_crtc_swap_fbs(crtc, old_fb); 905 if (ret) 906 return ret; 907 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 908 } 909 910 static int 911 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 912 struct drm_framebuffer *fb, 913 int x, int y, enum mode_set_atomic state) 914 { 915 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 916 struct drm_device *dev = drm->dev; 917 918 if (state == ENTER_ATOMIC_MODE_SET) 919 nouveau_fbcon_accel_save_disable(dev); 920 else 921 nouveau_fbcon_accel_restore(dev); 922 923 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 924 } 925 926 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 927 struct nouveau_bo *dst) 928 { 929 int width = nv_cursor_width(dev); 930 uint32_t pixel; 931 int i, j; 932 933 for (i = 0; i < width; i++) { 934 for (j = 0; j < width; j++) { 935 pixel = nouveau_bo_rd32(src, i*64 + j); 936 937 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 938 | (pixel & 0xf80000) >> 9 939 | (pixel & 0xf800) >> 6 940 | (pixel & 0xf8) >> 3); 941 } 942 } 943 } 944 945 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 946 struct nouveau_bo *dst) 947 { 948 uint32_t pixel; 949 int alpha, i; 950 951 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 952 * cursors (though NPM in combination with fp dithering may not work on 953 * nv11, from "nv" driver history) 954 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 955 * blob uses, however we get given PM cursors so we use PM mode 956 */ 957 for (i = 0; i < 64 * 64; i++) { 958 pixel = nouveau_bo_rd32(src, i); 959 960 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 961 * than" shouldn't happen; fix "equal to" case by adding one to 962 * alpha channel (slightly inaccurate, but so is attempting to 963 * get back to NPM images, due to limits of integer precision) 964 */ 965 alpha = pixel >> 24; 966 if (alpha > 0 && alpha < 255) 967 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 968 969 #ifdef __BIG_ENDIAN 970 { 971 struct nouveau_drm *drm = nouveau_drm(dev); 972 973 if (drm->client.device.info.chipset == 0x11) { 974 pixel = ((pixel & 0x000000ff) << 24) | 975 ((pixel & 0x0000ff00) << 8) | 976 ((pixel & 0x00ff0000) >> 8) | 977 ((pixel & 0xff000000) >> 24); 978 } 979 } 980 #endif 981 982 nouveau_bo_wr32(dst, i, pixel); 983 } 984 } 985 986 static int 987 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 988 uint32_t buffer_handle, uint32_t width, uint32_t height) 989 { 990 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 991 struct drm_device *dev = drm->dev; 992 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 993 struct nouveau_bo *cursor = NULL; 994 struct drm_gem_object *gem; 995 int ret = 0; 996 997 if (!buffer_handle) { 998 nv_crtc->cursor.hide(nv_crtc, true); 999 return 0; 1000 } 1001 1002 if (width != 64 || height != 64) 1003 return -EINVAL; 1004 1005 gem = drm_gem_object_lookup(file_priv, buffer_handle); 1006 if (!gem) 1007 return -ENOENT; 1008 cursor = nouveau_gem_object(gem); 1009 1010 ret = nouveau_bo_map(cursor); 1011 if (ret) 1012 goto out; 1013 1014 if (drm->client.device.info.chipset >= 0x11) 1015 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1016 else 1017 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1018 1019 nouveau_bo_unmap(cursor); 1020 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset; 1021 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1022 nv_crtc->cursor.show(nv_crtc, true); 1023 out: 1024 drm_gem_object_put(gem); 1025 return ret; 1026 } 1027 1028 static int 1029 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1030 { 1031 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1032 1033 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1034 return 0; 1035 } 1036 1037 struct nv04_page_flip_state { 1038 struct list_head head; 1039 struct drm_pending_vblank_event *event; 1040 struct drm_crtc *crtc; 1041 int bpp, pitch; 1042 u64 offset; 1043 }; 1044 1045 static int 1046 nv04_finish_page_flip(struct nouveau_channel *chan, 1047 struct nv04_page_flip_state *ps) 1048 { 1049 struct nouveau_fence_chan *fctx = chan->fence; 1050 struct nouveau_drm *drm = chan->drm; 1051 struct drm_device *dev = drm->dev; 1052 struct nv04_page_flip_state *s; 1053 unsigned long flags; 1054 1055 spin_lock_irqsave(&dev->event_lock, flags); 1056 1057 if (list_empty(&fctx->flip)) { 1058 NV_ERROR(drm, "unexpected pageflip\n"); 1059 spin_unlock_irqrestore(&dev->event_lock, flags); 1060 return -EINVAL; 1061 } 1062 1063 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head); 1064 if (s->event) { 1065 drm_crtc_arm_vblank_event(s->crtc, s->event); 1066 } else { 1067 /* Give up ownership of vblank for page-flipped crtc */ 1068 drm_crtc_vblank_put(s->crtc); 1069 } 1070 1071 list_del(&s->head); 1072 if (ps) 1073 *ps = *s; 1074 kfree(s); 1075 1076 spin_unlock_irqrestore(&dev->event_lock, flags); 1077 return 0; 1078 } 1079 1080 int 1081 nv04_flip_complete(struct nvif_notify *notify) 1082 { 1083 struct nouveau_cli *cli = (void *)notify->object->client; 1084 struct nouveau_drm *drm = cli->drm; 1085 struct nouveau_channel *chan = drm->channel; 1086 struct nv04_page_flip_state state; 1087 1088 if (!nv04_finish_page_flip(chan, &state)) { 1089 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), 1090 state.offset + state.crtc->y * 1091 state.pitch + state.crtc->x * 1092 state.bpp / 8); 1093 } 1094 1095 return NVIF_NOTIFY_KEEP; 1096 } 1097 1098 static int 1099 nv04_page_flip_emit(struct nouveau_channel *chan, 1100 struct nouveau_bo *old_bo, 1101 struct nouveau_bo *new_bo, 1102 struct nv04_page_flip_state *s, 1103 struct nouveau_fence **pfence) 1104 { 1105 struct nouveau_fence_chan *fctx = chan->fence; 1106 struct nouveau_drm *drm = chan->drm; 1107 struct drm_device *dev = drm->dev; 1108 unsigned long flags; 1109 int ret; 1110 1111 /* Queue it to the pending list */ 1112 spin_lock_irqsave(&dev->event_lock, flags); 1113 list_add_tail(&s->head, &fctx->flip); 1114 spin_unlock_irqrestore(&dev->event_lock, flags); 1115 1116 /* Synchronize with the old framebuffer */ 1117 ret = nouveau_fence_sync(old_bo, chan, false, false); 1118 if (ret) 1119 goto fail; 1120 1121 /* Emit the pageflip */ 1122 ret = RING_SPACE(chan, 2); 1123 if (ret) 1124 goto fail; 1125 1126 BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); 1127 OUT_RING (chan, 0x00000000); 1128 FIRE_RING (chan); 1129 1130 ret = nouveau_fence_new(chan, false, pfence); 1131 if (ret) 1132 goto fail; 1133 1134 return 0; 1135 fail: 1136 spin_lock_irqsave(&dev->event_lock, flags); 1137 list_del(&s->head); 1138 spin_unlock_irqrestore(&dev->event_lock, flags); 1139 return ret; 1140 } 1141 1142 static int 1143 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1144 struct drm_pending_vblank_event *event, u32 flags, 1145 struct drm_modeset_acquire_ctx *ctx) 1146 { 1147 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; 1148 struct drm_device *dev = crtc->dev; 1149 struct nouveau_drm *drm = nouveau_drm(dev); 1150 struct drm_framebuffer *old_fb = crtc->primary->fb; 1151 struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]); 1152 struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]); 1153 struct nv04_page_flip_state *s; 1154 struct nouveau_channel *chan; 1155 struct nouveau_cli *cli; 1156 struct nouveau_fence *fence; 1157 struct nv04_display *dispnv04 = nv04_display(dev); 1158 int head = nouveau_crtc(crtc)->index; 1159 int ret; 1160 1161 chan = drm->channel; 1162 if (!chan) 1163 return -ENODEV; 1164 cli = (void *)chan->user.client; 1165 1166 s = kzalloc(sizeof(*s), GFP_KERNEL); 1167 if (!s) 1168 return -ENOMEM; 1169 1170 if (new_bo != old_bo) { 1171 ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM, true); 1172 if (ret) 1173 goto fail_free; 1174 } 1175 1176 mutex_lock(&cli->mutex); 1177 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL); 1178 if (ret) 1179 goto fail_unpin; 1180 1181 /* synchronise rendering channel with the kernel's channel */ 1182 ret = nouveau_fence_sync(new_bo, chan, false, true); 1183 if (ret) { 1184 ttm_bo_unreserve(&new_bo->bo); 1185 goto fail_unpin; 1186 } 1187 1188 if (new_bo != old_bo) { 1189 ttm_bo_unreserve(&new_bo->bo); 1190 1191 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL); 1192 if (ret) 1193 goto fail_unpin; 1194 } 1195 1196 /* Initialize a page flip struct */ 1197 *s = (struct nv04_page_flip_state) 1198 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], 1199 new_bo->offset }; 1200 1201 /* Keep vblanks on during flip, for the target crtc of this flip */ 1202 drm_crtc_vblank_get(crtc); 1203 1204 /* Emit a page flip */ 1205 if (swap_interval) { 1206 ret = RING_SPACE(chan, 8); 1207 if (ret) 1208 goto fail_unreserve; 1209 1210 BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); 1211 OUT_RING (chan, 0); 1212 BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); 1213 OUT_RING (chan, head); 1214 BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); 1215 OUT_RING (chan, 0); 1216 BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); 1217 OUT_RING (chan, 0); 1218 } 1219 1220 nouveau_bo_ref(new_bo, &dispnv04->image[head]); 1221 1222 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence); 1223 if (ret) 1224 goto fail_unreserve; 1225 mutex_unlock(&cli->mutex); 1226 1227 /* Update the crtc struct and cleanup */ 1228 crtc->primary->fb = fb; 1229 1230 nouveau_bo_fence(old_bo, fence, false); 1231 ttm_bo_unreserve(&old_bo->bo); 1232 if (old_bo != new_bo) 1233 nouveau_bo_unpin(old_bo); 1234 nouveau_fence_unref(&fence); 1235 return 0; 1236 1237 fail_unreserve: 1238 drm_crtc_vblank_put(crtc); 1239 ttm_bo_unreserve(&old_bo->bo); 1240 fail_unpin: 1241 mutex_unlock(&cli->mutex); 1242 if (old_bo != new_bo) 1243 nouveau_bo_unpin(new_bo); 1244 fail_free: 1245 kfree(s); 1246 return ret; 1247 } 1248 1249 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1250 .cursor_set = nv04_crtc_cursor_set, 1251 .cursor_move = nv04_crtc_cursor_move, 1252 .gamma_set = nv_crtc_gamma_set, 1253 .set_config = drm_crtc_helper_set_config, 1254 .page_flip = nv04_crtc_page_flip, 1255 .destroy = nv_crtc_destroy, 1256 .enable_vblank = nouveau_display_vblank_enable, 1257 .disable_vblank = nouveau_display_vblank_disable, 1258 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1259 }; 1260 1261 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1262 .dpms = nv_crtc_dpms, 1263 .prepare = nv_crtc_prepare, 1264 .commit = nv_crtc_commit, 1265 .mode_set = nv_crtc_mode_set, 1266 .mode_set_base = nv04_crtc_mode_set_base, 1267 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1268 .disable = nv_crtc_disable, 1269 .get_scanout_position = nouveau_display_scanoutpos, 1270 }; 1271 1272 static const uint32_t modeset_formats[] = { 1273 DRM_FORMAT_XRGB8888, 1274 DRM_FORMAT_RGB565, 1275 DRM_FORMAT_XRGB1555, 1276 }; 1277 1278 static struct drm_plane * 1279 create_primary_plane(struct drm_device *dev) 1280 { 1281 struct drm_plane *primary; 1282 int ret; 1283 1284 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 1285 if (primary == NULL) { 1286 DRM_DEBUG_KMS("Failed to allocate primary plane\n"); 1287 return NULL; 1288 } 1289 1290 /* possible_crtc's will be filled in later by crtc_init */ 1291 ret = drm_universal_plane_init(dev, primary, 0, 1292 &drm_primary_helper_funcs, 1293 modeset_formats, 1294 ARRAY_SIZE(modeset_formats), NULL, 1295 DRM_PLANE_TYPE_PRIMARY, NULL); 1296 if (ret) { 1297 kfree(primary); 1298 primary = NULL; 1299 } 1300 1301 return primary; 1302 } 1303 1304 static int nv04_crtc_vblank_handler(struct nvif_notify *notify) 1305 { 1306 struct nouveau_crtc *nv_crtc = 1307 container_of(notify, struct nouveau_crtc, vblank); 1308 1309 drm_crtc_handle_vblank(&nv_crtc->base); 1310 return NVIF_NOTIFY_KEEP; 1311 } 1312 1313 int 1314 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1315 { 1316 struct nouveau_display *disp = nouveau_display(dev); 1317 struct nouveau_crtc *nv_crtc; 1318 int ret; 1319 1320 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1321 if (!nv_crtc) 1322 return -ENOMEM; 1323 1324 nv_crtc->lut.depth = 0; 1325 1326 nv_crtc->index = crtc_num; 1327 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1328 1329 nv_crtc->save = nv_crtc_save; 1330 nv_crtc->restore = nv_crtc_restore; 1331 1332 drm_crtc_init_with_planes(dev, &nv_crtc->base, 1333 create_primary_plane(dev), NULL, 1334 &nv04_crtc_funcs, NULL); 1335 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1336 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1337 1338 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, 1339 TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, 1340 &nv_crtc->cursor.nvbo); 1341 if (!ret) { 1342 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); 1343 if (!ret) { 1344 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1345 if (ret) 1346 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1347 } 1348 if (ret) 1349 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1350 } 1351 1352 nv04_cursor_init(nv_crtc); 1353 1354 ret = nvif_notify_init(&disp->disp.object, nv04_crtc_vblank_handler, 1355 false, NV04_DISP_NTFY_VBLANK, 1356 &(struct nvif_notify_head_req_v0) { 1357 .head = nv_crtc->index, 1358 }, 1359 sizeof(struct nvif_notify_head_req_v0), 1360 sizeof(struct nvif_notify_head_rep_v0), 1361 &nv_crtc->vblank); 1362 1363 return ret; 1364 } 1365