1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <linux/pm_runtime.h> 26 27 #include <drm/drmP.h> 28 #include <drm/drm_crtc_helper.h> 29 30 #include "nouveau_drm.h" 31 #include "nouveau_reg.h" 32 #include "nouveau_bo.h" 33 #include "nouveau_gem.h" 34 #include "nouveau_encoder.h" 35 #include "nouveau_connector.h" 36 #include "nouveau_crtc.h" 37 #include "hw.h" 38 #include "nvreg.h" 39 #include "nouveau_fbcon.h" 40 #include "disp.h" 41 42 #include <subdev/bios/pll.h> 43 #include <subdev/clock.h> 44 45 static int 46 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 47 struct drm_framebuffer *old_fb); 48 49 static void 50 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 51 { 52 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 53 crtcstate->CRTC[index]); 54 } 55 56 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 57 { 58 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 59 struct drm_device *dev = crtc->dev; 60 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 61 62 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 63 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 64 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 65 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 66 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 67 } 68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 69 } 70 71 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 72 { 73 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 76 77 nv_crtc->sharpness = level; 78 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 79 level += 0x40; 80 regp->ramdac_634 = level; 81 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 82 } 83 84 #define PLLSEL_VPLL1_MASK \ 85 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 86 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 87 #define PLLSEL_VPLL2_MASK \ 88 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 89 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 90 #define PLLSEL_TV_MASK \ 91 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 92 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 93 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 95 96 /* NV4x 0x40.. pll notes: 97 * gpu pll: 0x4000 + 0x4004 98 * ?gpu? pll: 0x4008 + 0x400c 99 * vpll1: 0x4010 + 0x4014 100 * vpll2: 0x4018 + 0x401c 101 * mpll: 0x4020 + 0x4024 102 * mpll: 0x4038 + 0x403c 103 * 104 * the first register of each pair has some unknown details: 105 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 106 * bits 20-23: (mpll) something to do with post divider? 107 * bits 28-31: related to single stage mode? (bit 8/12) 108 */ 109 110 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 111 { 112 struct drm_device *dev = crtc->dev; 113 struct nouveau_drm *drm = nouveau_drm(dev); 114 struct nouveau_bios *bios = nouveau_bios(drm->device); 115 struct nouveau_clock *clk = nouveau_clock(drm->device); 116 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 117 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 118 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 119 struct nouveau_pll_vals *pv = ®p->pllvals; 120 struct nvbios_pll pll_lim; 121 122 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 123 &pll_lim)) 124 return; 125 126 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 127 pv->NM2 = 0; 128 129 /* for newer nv4x the blob uses only the first stage of the vpll below a 130 * certain clock. for a certain nv4b this is 150MHz. since the max 131 * output frequency of the first stage for this card is 300MHz, it is 132 * assumed the threshold is given by vco1 maxfreq/2 133 */ 134 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 135 * not 8, others unknown), the blob always uses both plls. no problem 136 * has yet been observed in allowing the use a single stage pll on all 137 * nv43 however. the behaviour of single stage use is untested on nv40 138 */ 139 if (nv_device(drm->device)->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 140 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 141 142 143 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 144 return; 145 146 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 147 148 /* The blob uses this always, so let's do the same */ 149 if (nv_device(drm->device)->card_type == NV_40) 150 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 151 /* again nv40 and some nv43 act more like nv3x as described above */ 152 if (nv_device(drm->device)->chipset < 0x41) 153 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 154 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 155 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 156 157 if (pv->NM2) 158 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 159 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 160 else 161 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 162 pv->N1, pv->M1, pv->log2P); 163 164 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 165 } 166 167 static void 168 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 169 { 170 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 171 struct drm_device *dev = crtc->dev; 172 struct nouveau_drm *drm = nouveau_drm(dev); 173 unsigned char seq1 = 0, crtc17 = 0; 174 unsigned char crtc1A; 175 176 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 177 nv_crtc->index); 178 179 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 180 return; 181 182 nv_crtc->last_dpms = mode; 183 184 if (nv_two_heads(dev)) 185 NVSetOwner(dev, nv_crtc->index); 186 187 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 188 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 189 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 190 switch (mode) { 191 case DRM_MODE_DPMS_STANDBY: 192 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 193 seq1 = 0x20; 194 crtc17 = 0x80; 195 crtc1A |= 0x80; 196 break; 197 case DRM_MODE_DPMS_SUSPEND: 198 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 199 seq1 = 0x20; 200 crtc17 = 0x80; 201 crtc1A |= 0x40; 202 break; 203 case DRM_MODE_DPMS_OFF: 204 /* Screen: Off; HSync: Off, VSync: Off */ 205 seq1 = 0x20; 206 crtc17 = 0x00; 207 crtc1A |= 0xC0; 208 break; 209 case DRM_MODE_DPMS_ON: 210 default: 211 /* Screen: On; HSync: On, VSync: On */ 212 seq1 = 0x00; 213 crtc17 = 0x80; 214 break; 215 } 216 217 NVVgaSeqReset(dev, nv_crtc->index, true); 218 /* Each head has it's own sequencer, so we can turn it off when we want */ 219 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 220 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 221 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 222 mdelay(10); 223 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 224 NVVgaSeqReset(dev, nv_crtc->index, false); 225 226 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 227 } 228 229 static bool 230 nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, 231 struct drm_display_mode *adjusted_mode) 232 { 233 return true; 234 } 235 236 static void 237 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 238 { 239 struct drm_device *dev = crtc->dev; 240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 242 struct drm_framebuffer *fb = crtc->fb; 243 244 /* Calculate our timings */ 245 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 246 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 247 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 248 int horizTotal = (mode->crtc_htotal >> 3) - 5; 249 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 250 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 251 int vertDisplay = mode->crtc_vdisplay - 1; 252 int vertStart = mode->crtc_vsync_start - 1; 253 int vertEnd = mode->crtc_vsync_end - 1; 254 int vertTotal = mode->crtc_vtotal - 2; 255 int vertBlankStart = mode->crtc_vdisplay - 1; 256 int vertBlankEnd = mode->crtc_vtotal - 1; 257 258 struct drm_encoder *encoder; 259 bool fp_output = false; 260 261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 262 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 263 264 if (encoder->crtc == crtc && 265 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 266 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 267 fp_output = true; 268 } 269 270 if (fp_output) { 271 vertStart = vertTotal - 3; 272 vertEnd = vertTotal - 2; 273 vertBlankStart = vertStart; 274 horizStart = horizTotal - 5; 275 horizEnd = horizTotal - 2; 276 horizBlankEnd = horizTotal + 4; 277 #if 0 278 if (dev->overlayAdaptor && nv_device(drm->device)->card_type >= NV_10) 279 /* This reportedly works around some video overlay bandwidth problems */ 280 horizTotal += 2; 281 #endif 282 } 283 284 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 285 vertTotal |= 1; 286 287 #if 0 288 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 289 ErrorF("horizStart: 0x%X \n", horizStart); 290 ErrorF("horizEnd: 0x%X \n", horizEnd); 291 ErrorF("horizTotal: 0x%X \n", horizTotal); 292 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 293 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 294 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 295 ErrorF("vertStart: 0x%X \n", vertStart); 296 ErrorF("vertEnd: 0x%X \n", vertEnd); 297 ErrorF("vertTotal: 0x%X \n", vertTotal); 298 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 299 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 300 #endif 301 302 /* 303 * compute correct Hsync & Vsync polarity 304 */ 305 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 306 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 307 308 regp->MiscOutReg = 0x23; 309 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 310 regp->MiscOutReg |= 0x40; 311 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 312 regp->MiscOutReg |= 0x80; 313 } else { 314 int vdisplay = mode->vdisplay; 315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 316 vdisplay *= 2; 317 if (mode->vscan > 1) 318 vdisplay *= mode->vscan; 319 if (vdisplay < 400) 320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 321 else if (vdisplay < 480) 322 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 323 else if (vdisplay < 768) 324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 325 else 326 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 327 } 328 329 regp->MiscOutReg |= (mode->clock_index & 0x03) << 2; 330 331 /* 332 * Time Sequencer 333 */ 334 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 335 /* 0x20 disables the sequencer */ 336 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 338 else 339 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 340 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 341 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 342 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 343 344 /* 345 * CRTC 346 */ 347 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 348 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 349 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 350 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 351 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 352 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 353 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 354 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 355 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 356 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 357 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 358 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 359 (1 << 4) | 360 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 361 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 362 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 363 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 364 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 365 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 366 1 << 6 | 367 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 368 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 369 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 370 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 371 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 372 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 373 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 374 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 375 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 376 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 377 /* framebuffer can be larger than crtc scanout area. */ 378 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 379 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 380 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 381 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 382 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 383 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 384 385 /* 386 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 387 */ 388 389 /* framebuffer can be larger than crtc scanout area. */ 390 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 391 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 392 regp->CRTC[NV_CIO_CRE_42] = 393 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 394 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 395 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 396 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 397 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 398 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 399 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 400 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 401 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 402 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 403 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 404 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 405 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 406 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 407 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 408 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 409 410 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 411 horizTotal = (horizTotal >> 1) & ~1; 412 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 413 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 414 } else 415 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 416 417 /* 418 * Graphics Display Controller 419 */ 420 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 421 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 422 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 423 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 424 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 425 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 426 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 427 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 428 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 429 430 regp->Attribute[0] = 0x00; /* standard colormap translation */ 431 regp->Attribute[1] = 0x01; 432 regp->Attribute[2] = 0x02; 433 regp->Attribute[3] = 0x03; 434 regp->Attribute[4] = 0x04; 435 regp->Attribute[5] = 0x05; 436 regp->Attribute[6] = 0x06; 437 regp->Attribute[7] = 0x07; 438 regp->Attribute[8] = 0x08; 439 regp->Attribute[9] = 0x09; 440 regp->Attribute[10] = 0x0A; 441 regp->Attribute[11] = 0x0B; 442 regp->Attribute[12] = 0x0C; 443 regp->Attribute[13] = 0x0D; 444 regp->Attribute[14] = 0x0E; 445 regp->Attribute[15] = 0x0F; 446 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 447 /* Non-vga */ 448 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 449 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 450 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 451 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 452 } 453 454 /** 455 * Sets up registers for the given mode/adjusted_mode pair. 456 * 457 * The clocks, CRTCs and outputs attached to this CRTC must be off. 458 * 459 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 460 * be easily turned on/off after this. 461 */ 462 static void 463 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 464 { 465 struct drm_device *dev = crtc->dev; 466 struct nouveau_drm *drm = nouveau_drm(dev); 467 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 468 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 469 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 470 struct drm_encoder *encoder; 471 bool lvds_output = false, tmds_output = false, tv_output = false, 472 off_chip_digital = false; 473 474 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 475 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 476 bool digital = false; 477 478 if (encoder->crtc != crtc) 479 continue; 480 481 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 482 digital = lvds_output = true; 483 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 484 tv_output = true; 485 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 486 digital = tmds_output = true; 487 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 488 off_chip_digital = true; 489 } 490 491 /* Registers not directly related to the (s)vga mode */ 492 493 /* What is the meaning of this register? */ 494 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 495 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 496 497 regp->crtc_eng_ctrl = 0; 498 /* Except for rare conditions I2C is enabled on the primary crtc */ 499 if (nv_crtc->index == 0) 500 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 501 #if 0 502 /* Set overlay to desired crtc. */ 503 if (dev->overlayAdaptor) { 504 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 505 if (pPriv->overlayCRTC == nv_crtc->index) 506 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 507 } 508 #endif 509 510 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 511 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 512 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 513 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 514 if (nv_device(drm->device)->chipset >= 0x11) 515 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 516 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 517 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 518 519 /* Unblock some timings */ 520 regp->CRTC[NV_CIO_CRE_53] = 0; 521 regp->CRTC[NV_CIO_CRE_54] = 0; 522 523 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 524 if (lvds_output) 525 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 526 else if (tmds_output) 527 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 528 else 529 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 530 531 /* These values seem to vary */ 532 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 533 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 534 535 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 536 537 /* probably a scratch reg, but kept for cargo-cult purposes: 538 * bit0: crtc0?, head A 539 * bit6: lvds, head A 540 * bit7: (only in X), head A 541 */ 542 if (nv_crtc->index == 0) 543 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 544 545 /* The blob seems to take the current value from crtc 0, add 4 to that 546 * and reuse the old value for crtc 1 */ 547 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 548 if (!nv_crtc->index) 549 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 550 551 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 552 * 1 << 30 on 0x60.830), for no apparent reason */ 553 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 554 555 if (nv_device(drm->device)->card_type >= NV_30) 556 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 557 558 regp->crtc_830 = mode->crtc_vdisplay - 3; 559 regp->crtc_834 = mode->crtc_vdisplay - 1; 560 561 if (nv_device(drm->device)->card_type == NV_40) 562 /* This is what the blob does */ 563 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 564 565 if (nv_device(drm->device)->card_type >= NV_30) 566 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 567 568 if (nv_device(drm->device)->card_type >= NV_10) 569 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 570 else 571 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 572 573 /* Some misc regs */ 574 if (nv_device(drm->device)->card_type == NV_40) { 575 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 576 regp->CRTC[NV_CIO_CRE_86] = 0x1; 577 } 578 579 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8; 580 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 581 if (lvds_output || tmds_output || tv_output) 582 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 583 584 /* Generic PRAMDAC regs */ 585 586 if (nv_device(drm->device)->card_type >= NV_10) 587 /* Only bit that bios and blob set. */ 588 regp->nv10_cursync = (1 << 25); 589 590 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 591 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 592 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 593 if (crtc->fb->depth == 16) 594 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 595 if (nv_device(drm->device)->chipset >= 0x11) 596 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 597 598 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 599 regp->tv_setup = 0; 600 601 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 602 603 /* Some values the blob sets */ 604 regp->ramdac_8c0 = 0x100; 605 regp->ramdac_a20 = 0x0; 606 regp->ramdac_a24 = 0xfffff; 607 regp->ramdac_a34 = 0x1; 608 } 609 610 static int 611 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 612 { 613 struct nv04_display *disp = nv04_display(crtc->dev); 614 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb); 615 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 616 int ret; 617 618 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); 619 if (ret == 0) { 620 if (disp->image[nv_crtc->index]) 621 nouveau_bo_unpin(disp->image[nv_crtc->index]); 622 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); 623 } 624 625 return ret; 626 } 627 628 /** 629 * Sets up registers for the given mode/adjusted_mode pair. 630 * 631 * The clocks, CRTCs and outputs attached to this CRTC must be off. 632 * 633 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 634 * be easily turned on/off after this. 635 */ 636 static int 637 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 638 struct drm_display_mode *adjusted_mode, 639 int x, int y, struct drm_framebuffer *old_fb) 640 { 641 struct drm_device *dev = crtc->dev; 642 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 643 struct nouveau_drm *drm = nouveau_drm(dev); 644 int ret; 645 646 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 647 drm_mode_debug_printmodeline(adjusted_mode); 648 649 ret = nv_crtc_swap_fbs(crtc, old_fb); 650 if (ret) 651 return ret; 652 653 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 654 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 655 656 nv_crtc_mode_set_vga(crtc, adjusted_mode); 657 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 658 if (nv_device(drm->device)->card_type == NV_40) 659 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 660 nv_crtc_mode_set_regs(crtc, adjusted_mode); 661 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 662 return 0; 663 } 664 665 static void nv_crtc_save(struct drm_crtc *crtc) 666 { 667 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 668 struct drm_device *dev = crtc->dev; 669 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 670 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 671 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 672 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 673 674 if (nv_two_heads(crtc->dev)) 675 NVSetOwner(crtc->dev, nv_crtc->index); 676 677 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 678 679 /* init some state to saved value */ 680 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 681 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 682 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 683 crtc_state->gpio_ext = crtc_saved->gpio_ext; 684 } 685 686 static void nv_crtc_restore(struct drm_crtc *crtc) 687 { 688 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 689 struct drm_device *dev = crtc->dev; 690 int head = nv_crtc->index; 691 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 692 693 if (nv_two_heads(crtc->dev)) 694 NVSetOwner(crtc->dev, head); 695 696 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 697 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 698 699 nv_crtc->last_dpms = NV_DPMS_CLEARED; 700 } 701 702 static void nv_crtc_prepare(struct drm_crtc *crtc) 703 { 704 struct drm_device *dev = crtc->dev; 705 struct nouveau_drm *drm = nouveau_drm(dev); 706 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 707 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 708 709 if (nv_two_heads(dev)) 710 NVSetOwner(dev, nv_crtc->index); 711 712 drm_vblank_pre_modeset(dev, nv_crtc->index); 713 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 714 715 NVBlankScreen(dev, nv_crtc->index, true); 716 717 /* Some more preparation. */ 718 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 719 if (nv_device(drm->device)->card_type == NV_40) { 720 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 721 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 722 } 723 } 724 725 static void nv_crtc_commit(struct drm_crtc *crtc) 726 { 727 struct drm_device *dev = crtc->dev; 728 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 729 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 730 731 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 732 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 733 734 #ifdef __BIG_ENDIAN 735 /* turn on LFB swapping */ 736 { 737 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 738 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 739 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 740 } 741 #endif 742 743 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 744 drm_vblank_post_modeset(dev, nv_crtc->index); 745 } 746 747 static void nv_crtc_destroy(struct drm_crtc *crtc) 748 { 749 struct nv04_display *disp = nv04_display(crtc->dev); 750 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 751 752 if (!nv_crtc) 753 return; 754 755 drm_crtc_cleanup(crtc); 756 757 if (disp->image[nv_crtc->index]) 758 nouveau_bo_unpin(disp->image[nv_crtc->index]); 759 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 760 761 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 762 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 763 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 764 kfree(nv_crtc); 765 } 766 767 static void 768 nv_crtc_gamma_load(struct drm_crtc *crtc) 769 { 770 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 771 struct drm_device *dev = nv_crtc->base.dev; 772 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 773 int i; 774 775 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 776 for (i = 0; i < 256; i++) { 777 rgbs[i].r = nv_crtc->lut.r[i] >> 8; 778 rgbs[i].g = nv_crtc->lut.g[i] >> 8; 779 rgbs[i].b = nv_crtc->lut.b[i] >> 8; 780 } 781 782 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 783 } 784 785 static void 786 nv_crtc_disable(struct drm_crtc *crtc) 787 { 788 struct nv04_display *disp = nv04_display(crtc->dev); 789 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 790 if (disp->image[nv_crtc->index]) 791 nouveau_bo_unpin(disp->image[nv_crtc->index]); 792 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 793 } 794 795 static void 796 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, 797 uint32_t size) 798 { 799 int end = (start + size > 256) ? 256 : start + size, i; 800 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 801 802 for (i = start; i < end; i++) { 803 nv_crtc->lut.r[i] = r[i]; 804 nv_crtc->lut.g[i] = g[i]; 805 nv_crtc->lut.b[i] = b[i]; 806 } 807 808 /* We need to know the depth before we upload, but it's possible to 809 * get called before a framebuffer is bound. If this is the case, 810 * mark the lut values as dirty by setting depth==0, and it'll be 811 * uploaded on the first mode_set_base() 812 */ 813 if (!nv_crtc->base.fb) { 814 nv_crtc->lut.depth = 0; 815 return; 816 } 817 818 nv_crtc_gamma_load(crtc); 819 } 820 821 static int 822 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 823 struct drm_framebuffer *passed_fb, 824 int x, int y, bool atomic) 825 { 826 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 827 struct drm_device *dev = crtc->dev; 828 struct nouveau_drm *drm = nouveau_drm(dev); 829 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 830 struct drm_framebuffer *drm_fb; 831 struct nouveau_framebuffer *fb; 832 int arb_burst, arb_lwm; 833 834 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 835 836 /* no fb bound */ 837 if (!atomic && !crtc->fb) { 838 NV_DEBUG(drm, "No FB bound\n"); 839 return 0; 840 } 841 842 /* If atomic, we want to switch to the fb we were passed, so 843 * now we update pointers to do that. 844 */ 845 if (atomic) { 846 drm_fb = passed_fb; 847 fb = nouveau_framebuffer(passed_fb); 848 } else { 849 drm_fb = crtc->fb; 850 fb = nouveau_framebuffer(crtc->fb); 851 } 852 853 nv_crtc->fb.offset = fb->nvbo->bo.offset; 854 855 if (nv_crtc->lut.depth != drm_fb->depth) { 856 nv_crtc->lut.depth = drm_fb->depth; 857 nv_crtc_gamma_load(crtc); 858 } 859 860 /* Update the framebuffer format. */ 861 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 862 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8; 863 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 864 if (crtc->fb->depth == 16) 865 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 866 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 867 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 868 regp->ramdac_gen_ctrl); 869 870 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 871 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 872 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 873 regp->CRTC[NV_CIO_CRE_42] = 874 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 875 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 876 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 877 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 878 879 /* Update the framebuffer location. */ 880 regp->fb_start = nv_crtc->fb.offset & ~3; 881 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); 882 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 883 884 /* Update the arbitration parameters. */ 885 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, 886 &arb_burst, &arb_lwm); 887 888 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 889 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 891 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 892 893 if (nv_device(drm->device)->card_type >= NV_20) { 894 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 895 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 896 } 897 898 return 0; 899 } 900 901 static int 902 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 903 struct drm_framebuffer *old_fb) 904 { 905 int ret = nv_crtc_swap_fbs(crtc, old_fb); 906 if (ret) 907 return ret; 908 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 909 } 910 911 static int 912 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 913 struct drm_framebuffer *fb, 914 int x, int y, enum mode_set_atomic state) 915 { 916 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 917 struct drm_device *dev = drm->dev; 918 919 if (state == ENTER_ATOMIC_MODE_SET) 920 nouveau_fbcon_save_disable_accel(dev); 921 else 922 nouveau_fbcon_restore_accel(dev); 923 924 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 925 } 926 927 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 928 struct nouveau_bo *dst) 929 { 930 int width = nv_cursor_width(dev); 931 uint32_t pixel; 932 int i, j; 933 934 for (i = 0; i < width; i++) { 935 for (j = 0; j < width; j++) { 936 pixel = nouveau_bo_rd32(src, i*64 + j); 937 938 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 939 | (pixel & 0xf80000) >> 9 940 | (pixel & 0xf800) >> 6 941 | (pixel & 0xf8) >> 3); 942 } 943 } 944 } 945 946 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 947 struct nouveau_bo *dst) 948 { 949 uint32_t pixel; 950 int alpha, i; 951 952 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 953 * cursors (though NPM in combination with fp dithering may not work on 954 * nv11, from "nv" driver history) 955 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 956 * blob uses, however we get given PM cursors so we use PM mode 957 */ 958 for (i = 0; i < 64 * 64; i++) { 959 pixel = nouveau_bo_rd32(src, i); 960 961 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 962 * than" shouldn't happen; fix "equal to" case by adding one to 963 * alpha channel (slightly inaccurate, but so is attempting to 964 * get back to NPM images, due to limits of integer precision) 965 */ 966 alpha = pixel >> 24; 967 if (alpha > 0 && alpha < 255) 968 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 969 970 #ifdef __BIG_ENDIAN 971 { 972 struct nouveau_drm *drm = nouveau_drm(dev); 973 974 if (nv_device(drm->device)->chipset == 0x11) { 975 pixel = ((pixel & 0x000000ff) << 24) | 976 ((pixel & 0x0000ff00) << 8) | 977 ((pixel & 0x00ff0000) >> 8) | 978 ((pixel & 0xff000000) >> 24); 979 } 980 } 981 #endif 982 983 nouveau_bo_wr32(dst, i, pixel); 984 } 985 } 986 987 static int 988 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 989 uint32_t buffer_handle, uint32_t width, uint32_t height) 990 { 991 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 992 struct drm_device *dev = drm->dev; 993 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 994 struct nouveau_bo *cursor = NULL; 995 struct drm_gem_object *gem; 996 int ret = 0; 997 998 if (!buffer_handle) { 999 nv_crtc->cursor.hide(nv_crtc, true); 1000 return 0; 1001 } 1002 1003 if (width != 64 || height != 64) 1004 return -EINVAL; 1005 1006 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 1007 if (!gem) 1008 return -ENOENT; 1009 cursor = nouveau_gem_object(gem); 1010 1011 ret = nouveau_bo_map(cursor); 1012 if (ret) 1013 goto out; 1014 1015 if (nv_device(drm->device)->chipset >= 0x11) 1016 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1017 else 1018 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1019 1020 nouveau_bo_unmap(cursor); 1021 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 1022 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1023 nv_crtc->cursor.show(nv_crtc, true); 1024 out: 1025 drm_gem_object_unreference_unlocked(gem); 1026 return ret; 1027 } 1028 1029 static int 1030 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1031 { 1032 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1033 1034 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1035 return 0; 1036 } 1037 1038 int 1039 nouveau_crtc_set_config(struct drm_mode_set *set) 1040 { 1041 struct drm_device *dev; 1042 struct nouveau_drm *drm; 1043 int ret; 1044 struct drm_crtc *crtc; 1045 bool active = false; 1046 if (!set || !set->crtc) 1047 return -EINVAL; 1048 1049 dev = set->crtc->dev; 1050 1051 /* get a pm reference here */ 1052 ret = pm_runtime_get_sync(dev->dev); 1053 if (ret < 0) 1054 return ret; 1055 1056 ret = drm_crtc_helper_set_config(set); 1057 1058 drm = nouveau_drm(dev); 1059 1060 /* if we get here with no crtcs active then we can drop a reference */ 1061 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1062 if (crtc->enabled) 1063 active = true; 1064 } 1065 1066 pm_runtime_mark_last_busy(dev->dev); 1067 /* if we have active crtcs and we don't have a power ref, 1068 take the current one */ 1069 if (active && !drm->have_disp_power_ref) { 1070 drm->have_disp_power_ref = true; 1071 return ret; 1072 } 1073 /* if we have no active crtcs, then drop the power ref 1074 we got before */ 1075 if (!active && drm->have_disp_power_ref) { 1076 pm_runtime_put_autosuspend(dev->dev); 1077 drm->have_disp_power_ref = false; 1078 } 1079 /* drop the power reference we got coming in here */ 1080 pm_runtime_put_autosuspend(dev->dev); 1081 return ret; 1082 } 1083 1084 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1085 .save = nv_crtc_save, 1086 .restore = nv_crtc_restore, 1087 .cursor_set = nv04_crtc_cursor_set, 1088 .cursor_move = nv04_crtc_cursor_move, 1089 .gamma_set = nv_crtc_gamma_set, 1090 .set_config = nouveau_crtc_set_config, 1091 .page_flip = nouveau_crtc_page_flip, 1092 .destroy = nv_crtc_destroy, 1093 }; 1094 1095 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1096 .dpms = nv_crtc_dpms, 1097 .prepare = nv_crtc_prepare, 1098 .commit = nv_crtc_commit, 1099 .mode_fixup = nv_crtc_mode_fixup, 1100 .mode_set = nv_crtc_mode_set, 1101 .mode_set_base = nv04_crtc_mode_set_base, 1102 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1103 .load_lut = nv_crtc_gamma_load, 1104 .disable = nv_crtc_disable, 1105 }; 1106 1107 int 1108 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1109 { 1110 struct nouveau_crtc *nv_crtc; 1111 int ret, i; 1112 1113 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1114 if (!nv_crtc) 1115 return -ENOMEM; 1116 1117 for (i = 0; i < 256; i++) { 1118 nv_crtc->lut.r[i] = i << 8; 1119 nv_crtc->lut.g[i] = i << 8; 1120 nv_crtc->lut.b[i] = i << 8; 1121 } 1122 nv_crtc->lut.depth = 0; 1123 1124 nv_crtc->index = crtc_num; 1125 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1126 1127 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); 1128 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1129 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1130 1131 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, 1132 0, 0x0000, NULL, &nv_crtc->cursor.nvbo); 1133 if (!ret) { 1134 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); 1135 if (!ret) { 1136 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1137 if (ret) 1138 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1139 } 1140 if (ret) 1141 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1142 } 1143 1144 nv04_cursor_init(nv_crtc); 1145 1146 return 0; 1147 } 1148