1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <linux/pm_runtime.h> 26 27 #include <drm/drmP.h> 28 #include <drm/drm_crtc_helper.h> 29 30 #include "nouveau_drm.h" 31 #include "nouveau_reg.h" 32 #include "nouveau_bo.h" 33 #include "nouveau_gem.h" 34 #include "nouveau_encoder.h" 35 #include "nouveau_connector.h" 36 #include "nouveau_crtc.h" 37 #include "hw.h" 38 #include "nvreg.h" 39 #include "nouveau_fbcon.h" 40 #include "disp.h" 41 42 #include <subdev/bios/pll.h> 43 #include <subdev/clock.h> 44 45 static int 46 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 47 struct drm_framebuffer *old_fb); 48 49 static void 50 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 51 { 52 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 53 crtcstate->CRTC[index]); 54 } 55 56 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 57 { 58 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 59 struct drm_device *dev = crtc->dev; 60 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 61 62 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 63 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 64 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 65 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 66 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 67 } 68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 69 } 70 71 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 72 { 73 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 76 77 nv_crtc->sharpness = level; 78 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 79 level += 0x40; 80 regp->ramdac_634 = level; 81 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 82 } 83 84 #define PLLSEL_VPLL1_MASK \ 85 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 86 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 87 #define PLLSEL_VPLL2_MASK \ 88 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 89 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 90 #define PLLSEL_TV_MASK \ 91 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 92 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 93 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 95 96 /* NV4x 0x40.. pll notes: 97 * gpu pll: 0x4000 + 0x4004 98 * ?gpu? pll: 0x4008 + 0x400c 99 * vpll1: 0x4010 + 0x4014 100 * vpll2: 0x4018 + 0x401c 101 * mpll: 0x4020 + 0x4024 102 * mpll: 0x4038 + 0x403c 103 * 104 * the first register of each pair has some unknown details: 105 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 106 * bits 20-23: (mpll) something to do with post divider? 107 * bits 28-31: related to single stage mode? (bit 8/12) 108 */ 109 110 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 111 { 112 struct drm_device *dev = crtc->dev; 113 struct nouveau_drm *drm = nouveau_drm(dev); 114 struct nouveau_bios *bios = nvkm_bios(&drm->device); 115 struct nouveau_clock *clk = nvkm_clock(&drm->device); 116 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 117 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 118 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 119 struct nouveau_pll_vals *pv = ®p->pllvals; 120 struct nvbios_pll pll_lim; 121 122 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 123 &pll_lim)) 124 return; 125 126 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 127 pv->NM2 = 0; 128 129 /* for newer nv4x the blob uses only the first stage of the vpll below a 130 * certain clock. for a certain nv4b this is 150MHz. since the max 131 * output frequency of the first stage for this card is 300MHz, it is 132 * assumed the threshold is given by vco1 maxfreq/2 133 */ 134 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 135 * not 8, others unknown), the blob always uses both plls. no problem 136 * has yet been observed in allowing the use a single stage pll on all 137 * nv43 however. the behaviour of single stage use is untested on nv40 138 */ 139 if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 140 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 141 142 143 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 144 return; 145 146 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 147 148 /* The blob uses this always, so let's do the same */ 149 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 150 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 151 /* again nv40 and some nv43 act more like nv3x as described above */ 152 if (drm->device.info.chipset < 0x41) 153 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 154 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 155 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 156 157 if (pv->NM2) 158 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 159 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 160 else 161 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 162 pv->N1, pv->M1, pv->log2P); 163 164 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 165 } 166 167 static void 168 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 169 { 170 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 171 struct drm_device *dev = crtc->dev; 172 struct nouveau_drm *drm = nouveau_drm(dev); 173 unsigned char seq1 = 0, crtc17 = 0; 174 unsigned char crtc1A; 175 176 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 177 nv_crtc->index); 178 179 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 180 return; 181 182 nv_crtc->last_dpms = mode; 183 184 if (nv_two_heads(dev)) 185 NVSetOwner(dev, nv_crtc->index); 186 187 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 188 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 189 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 190 switch (mode) { 191 case DRM_MODE_DPMS_STANDBY: 192 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 193 seq1 = 0x20; 194 crtc17 = 0x80; 195 crtc1A |= 0x80; 196 break; 197 case DRM_MODE_DPMS_SUSPEND: 198 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 199 seq1 = 0x20; 200 crtc17 = 0x80; 201 crtc1A |= 0x40; 202 break; 203 case DRM_MODE_DPMS_OFF: 204 /* Screen: Off; HSync: Off, VSync: Off */ 205 seq1 = 0x20; 206 crtc17 = 0x00; 207 crtc1A |= 0xC0; 208 break; 209 case DRM_MODE_DPMS_ON: 210 default: 211 /* Screen: On; HSync: On, VSync: On */ 212 seq1 = 0x00; 213 crtc17 = 0x80; 214 break; 215 } 216 217 NVVgaSeqReset(dev, nv_crtc->index, true); 218 /* Each head has it's own sequencer, so we can turn it off when we want */ 219 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 220 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 221 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 222 mdelay(10); 223 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 224 NVVgaSeqReset(dev, nv_crtc->index, false); 225 226 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 227 } 228 229 static bool 230 nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, 231 struct drm_display_mode *adjusted_mode) 232 { 233 return true; 234 } 235 236 static void 237 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 238 { 239 struct drm_device *dev = crtc->dev; 240 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 242 struct drm_framebuffer *fb = crtc->primary->fb; 243 244 /* Calculate our timings */ 245 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 246 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 247 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 248 int horizTotal = (mode->crtc_htotal >> 3) - 5; 249 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 250 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 251 int vertDisplay = mode->crtc_vdisplay - 1; 252 int vertStart = mode->crtc_vsync_start - 1; 253 int vertEnd = mode->crtc_vsync_end - 1; 254 int vertTotal = mode->crtc_vtotal - 2; 255 int vertBlankStart = mode->crtc_vdisplay - 1; 256 int vertBlankEnd = mode->crtc_vtotal - 1; 257 258 struct drm_encoder *encoder; 259 bool fp_output = false; 260 261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 262 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 263 264 if (encoder->crtc == crtc && 265 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 266 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 267 fp_output = true; 268 } 269 270 if (fp_output) { 271 vertStart = vertTotal - 3; 272 vertEnd = vertTotal - 2; 273 vertBlankStart = vertStart; 274 horizStart = horizTotal - 5; 275 horizEnd = horizTotal - 2; 276 horizBlankEnd = horizTotal + 4; 277 #if 0 278 if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 279 /* This reportedly works around some video overlay bandwidth problems */ 280 horizTotal += 2; 281 #endif 282 } 283 284 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 285 vertTotal |= 1; 286 287 #if 0 288 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 289 ErrorF("horizStart: 0x%X \n", horizStart); 290 ErrorF("horizEnd: 0x%X \n", horizEnd); 291 ErrorF("horizTotal: 0x%X \n", horizTotal); 292 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 293 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 294 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 295 ErrorF("vertStart: 0x%X \n", vertStart); 296 ErrorF("vertEnd: 0x%X \n", vertEnd); 297 ErrorF("vertTotal: 0x%X \n", vertTotal); 298 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 299 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 300 #endif 301 302 /* 303 * compute correct Hsync & Vsync polarity 304 */ 305 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 306 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 307 308 regp->MiscOutReg = 0x23; 309 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 310 regp->MiscOutReg |= 0x40; 311 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 312 regp->MiscOutReg |= 0x80; 313 } else { 314 int vdisplay = mode->vdisplay; 315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 316 vdisplay *= 2; 317 if (mode->vscan > 1) 318 vdisplay *= mode->vscan; 319 if (vdisplay < 400) 320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 321 else if (vdisplay < 480) 322 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 323 else if (vdisplay < 768) 324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 325 else 326 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 327 } 328 329 /* 330 * Time Sequencer 331 */ 332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 333 /* 0x20 disables the sequencer */ 334 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 336 else 337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 341 342 /* 343 * CRTC 344 */ 345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 349 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 352 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 355 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 356 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 357 (1 << 4) | 358 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 359 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 360 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 361 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 364 1 << 6 | 365 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 375 /* framebuffer can be larger than crtc scanout area. */ 376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 382 383 /* 384 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 385 */ 386 387 /* framebuffer can be larger than crtc scanout area. */ 388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 389 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 390 regp->CRTC[NV_CIO_CRE_42] = 391 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 393 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 395 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 396 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 397 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 398 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 400 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 401 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 402 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 404 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 405 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 406 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 407 408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 409 horizTotal = (horizTotal >> 1) & ~1; 410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 412 } else 413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 414 415 /* 416 * Graphics Display Controller 417 */ 418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 427 428 regp->Attribute[0] = 0x00; /* standard colormap translation */ 429 regp->Attribute[1] = 0x01; 430 regp->Attribute[2] = 0x02; 431 regp->Attribute[3] = 0x03; 432 regp->Attribute[4] = 0x04; 433 regp->Attribute[5] = 0x05; 434 regp->Attribute[6] = 0x06; 435 regp->Attribute[7] = 0x07; 436 regp->Attribute[8] = 0x08; 437 regp->Attribute[9] = 0x09; 438 regp->Attribute[10] = 0x0A; 439 regp->Attribute[11] = 0x0B; 440 regp->Attribute[12] = 0x0C; 441 regp->Attribute[13] = 0x0D; 442 regp->Attribute[14] = 0x0E; 443 regp->Attribute[15] = 0x0F; 444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 445 /* Non-vga */ 446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 450 } 451 452 /** 453 * Sets up registers for the given mode/adjusted_mode pair. 454 * 455 * The clocks, CRTCs and outputs attached to this CRTC must be off. 456 * 457 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 458 * be easily turned on/off after this. 459 */ 460 static void 461 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 462 { 463 struct drm_device *dev = crtc->dev; 464 struct nouveau_drm *drm = nouveau_drm(dev); 465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 468 struct drm_encoder *encoder; 469 bool lvds_output = false, tmds_output = false, tv_output = false, 470 off_chip_digital = false; 471 472 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 473 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 474 bool digital = false; 475 476 if (encoder->crtc != crtc) 477 continue; 478 479 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 480 digital = lvds_output = true; 481 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 482 tv_output = true; 483 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 484 digital = tmds_output = true; 485 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 486 off_chip_digital = true; 487 } 488 489 /* Registers not directly related to the (s)vga mode */ 490 491 /* What is the meaning of this register? */ 492 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 493 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 494 495 regp->crtc_eng_ctrl = 0; 496 /* Except for rare conditions I2C is enabled on the primary crtc */ 497 if (nv_crtc->index == 0) 498 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 499 #if 0 500 /* Set overlay to desired crtc. */ 501 if (dev->overlayAdaptor) { 502 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 503 if (pPriv->overlayCRTC == nv_crtc->index) 504 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 505 } 506 #endif 507 508 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 509 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 510 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 511 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 512 if (drm->device.info.chipset >= 0x11) 513 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 514 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 515 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 516 517 /* Unblock some timings */ 518 regp->CRTC[NV_CIO_CRE_53] = 0; 519 regp->CRTC[NV_CIO_CRE_54] = 0; 520 521 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 522 if (lvds_output) 523 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 524 else if (tmds_output) 525 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 526 else 527 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 528 529 /* These values seem to vary */ 530 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 531 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 532 533 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 534 535 /* probably a scratch reg, but kept for cargo-cult purposes: 536 * bit0: crtc0?, head A 537 * bit6: lvds, head A 538 * bit7: (only in X), head A 539 */ 540 if (nv_crtc->index == 0) 541 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 542 543 /* The blob seems to take the current value from crtc 0, add 4 to that 544 * and reuse the old value for crtc 1 */ 545 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 546 if (!nv_crtc->index) 547 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 548 549 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 550 * 1 << 30 on 0x60.830), for no apparent reason */ 551 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 552 553 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 554 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 555 556 regp->crtc_830 = mode->crtc_vdisplay - 3; 557 regp->crtc_834 = mode->crtc_vdisplay - 1; 558 559 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 560 /* This is what the blob does */ 561 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 562 563 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 564 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 565 566 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 567 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 568 else 569 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 570 571 /* Some misc regs */ 572 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { 573 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 574 regp->CRTC[NV_CIO_CRE_86] = 0x1; 575 } 576 577 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; 578 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 579 if (lvds_output || tmds_output || tv_output) 580 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 581 582 /* Generic PRAMDAC regs */ 583 584 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 585 /* Only bit that bios and blob set. */ 586 regp->nv10_cursync = (1 << 25); 587 588 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 589 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 590 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 591 if (crtc->primary->fb->depth == 16) 592 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 593 if (drm->device.info.chipset >= 0x11) 594 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 595 596 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 597 regp->tv_setup = 0; 598 599 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 600 601 /* Some values the blob sets */ 602 regp->ramdac_8c0 = 0x100; 603 regp->ramdac_a20 = 0x0; 604 regp->ramdac_a24 = 0xfffff; 605 regp->ramdac_a34 = 0x1; 606 } 607 608 static int 609 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 610 { 611 struct nv04_display *disp = nv04_display(crtc->dev); 612 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); 613 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 614 int ret; 615 616 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); 617 if (ret == 0) { 618 if (disp->image[nv_crtc->index]) 619 nouveau_bo_unpin(disp->image[nv_crtc->index]); 620 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); 621 } 622 623 return ret; 624 } 625 626 /** 627 * Sets up registers for the given mode/adjusted_mode pair. 628 * 629 * The clocks, CRTCs and outputs attached to this CRTC must be off. 630 * 631 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 632 * be easily turned on/off after this. 633 */ 634 static int 635 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 636 struct drm_display_mode *adjusted_mode, 637 int x, int y, struct drm_framebuffer *old_fb) 638 { 639 struct drm_device *dev = crtc->dev; 640 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 641 struct nouveau_drm *drm = nouveau_drm(dev); 642 int ret; 643 644 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 645 drm_mode_debug_printmodeline(adjusted_mode); 646 647 ret = nv_crtc_swap_fbs(crtc, old_fb); 648 if (ret) 649 return ret; 650 651 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 652 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 653 654 nv_crtc_mode_set_vga(crtc, adjusted_mode); 655 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 656 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) 657 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 658 nv_crtc_mode_set_regs(crtc, adjusted_mode); 659 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 660 return 0; 661 } 662 663 static void nv_crtc_save(struct drm_crtc *crtc) 664 { 665 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 666 struct drm_device *dev = crtc->dev; 667 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 668 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 669 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 670 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 671 672 if (nv_two_heads(crtc->dev)) 673 NVSetOwner(crtc->dev, nv_crtc->index); 674 675 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 676 677 /* init some state to saved value */ 678 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 679 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 680 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 681 crtc_state->gpio_ext = crtc_saved->gpio_ext; 682 } 683 684 static void nv_crtc_restore(struct drm_crtc *crtc) 685 { 686 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 687 struct drm_device *dev = crtc->dev; 688 int head = nv_crtc->index; 689 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 690 691 if (nv_two_heads(crtc->dev)) 692 NVSetOwner(crtc->dev, head); 693 694 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 695 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 696 697 nv_crtc->last_dpms = NV_DPMS_CLEARED; 698 } 699 700 static void nv_crtc_prepare(struct drm_crtc *crtc) 701 { 702 struct drm_device *dev = crtc->dev; 703 struct nouveau_drm *drm = nouveau_drm(dev); 704 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 705 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 706 707 if (nv_two_heads(dev)) 708 NVSetOwner(dev, nv_crtc->index); 709 710 drm_vblank_pre_modeset(dev, nv_crtc->index); 711 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 712 713 NVBlankScreen(dev, nv_crtc->index, true); 714 715 /* Some more preparation. */ 716 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 717 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { 718 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 719 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 720 } 721 } 722 723 static void nv_crtc_commit(struct drm_crtc *crtc) 724 { 725 struct drm_device *dev = crtc->dev; 726 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 727 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 728 729 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 730 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 731 732 #ifdef __BIG_ENDIAN 733 /* turn on LFB swapping */ 734 { 735 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 736 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 737 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 738 } 739 #endif 740 741 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 742 drm_vblank_post_modeset(dev, nv_crtc->index); 743 } 744 745 static void nv_crtc_destroy(struct drm_crtc *crtc) 746 { 747 struct nv04_display *disp = nv04_display(crtc->dev); 748 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 749 750 if (!nv_crtc) 751 return; 752 753 drm_crtc_cleanup(crtc); 754 755 if (disp->image[nv_crtc->index]) 756 nouveau_bo_unpin(disp->image[nv_crtc->index]); 757 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 758 759 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 760 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 761 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 762 kfree(nv_crtc); 763 } 764 765 static void 766 nv_crtc_gamma_load(struct drm_crtc *crtc) 767 { 768 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 769 struct drm_device *dev = nv_crtc->base.dev; 770 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 771 int i; 772 773 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 774 for (i = 0; i < 256; i++) { 775 rgbs[i].r = nv_crtc->lut.r[i] >> 8; 776 rgbs[i].g = nv_crtc->lut.g[i] >> 8; 777 rgbs[i].b = nv_crtc->lut.b[i] >> 8; 778 } 779 780 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 781 } 782 783 static void 784 nv_crtc_disable(struct drm_crtc *crtc) 785 { 786 struct nv04_display *disp = nv04_display(crtc->dev); 787 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 788 if (disp->image[nv_crtc->index]) 789 nouveau_bo_unpin(disp->image[nv_crtc->index]); 790 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 791 } 792 793 static void 794 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, 795 uint32_t size) 796 { 797 int end = (start + size > 256) ? 256 : start + size, i; 798 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 799 800 for (i = start; i < end; i++) { 801 nv_crtc->lut.r[i] = r[i]; 802 nv_crtc->lut.g[i] = g[i]; 803 nv_crtc->lut.b[i] = b[i]; 804 } 805 806 /* We need to know the depth before we upload, but it's possible to 807 * get called before a framebuffer is bound. If this is the case, 808 * mark the lut values as dirty by setting depth==0, and it'll be 809 * uploaded on the first mode_set_base() 810 */ 811 if (!nv_crtc->base.primary->fb) { 812 nv_crtc->lut.depth = 0; 813 return; 814 } 815 816 nv_crtc_gamma_load(crtc); 817 } 818 819 static int 820 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 821 struct drm_framebuffer *passed_fb, 822 int x, int y, bool atomic) 823 { 824 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 825 struct drm_device *dev = crtc->dev; 826 struct nouveau_drm *drm = nouveau_drm(dev); 827 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 828 struct drm_framebuffer *drm_fb; 829 struct nouveau_framebuffer *fb; 830 int arb_burst, arb_lwm; 831 832 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 833 834 /* no fb bound */ 835 if (!atomic && !crtc->primary->fb) { 836 NV_DEBUG(drm, "No FB bound\n"); 837 return 0; 838 } 839 840 /* If atomic, we want to switch to the fb we were passed, so 841 * now we update pointers to do that. 842 */ 843 if (atomic) { 844 drm_fb = passed_fb; 845 fb = nouveau_framebuffer(passed_fb); 846 } else { 847 drm_fb = crtc->primary->fb; 848 fb = nouveau_framebuffer(crtc->primary->fb); 849 } 850 851 nv_crtc->fb.offset = fb->nvbo->bo.offset; 852 853 if (nv_crtc->lut.depth != drm_fb->depth) { 854 nv_crtc->lut.depth = drm_fb->depth; 855 nv_crtc_gamma_load(crtc); 856 } 857 858 /* Update the framebuffer format. */ 859 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 860 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; 861 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 862 if (crtc->primary->fb->depth == 16) 863 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 864 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 865 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 866 regp->ramdac_gen_ctrl); 867 868 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 869 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 870 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 871 regp->CRTC[NV_CIO_CRE_42] = 872 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 873 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 874 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 875 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 876 877 /* Update the framebuffer location. */ 878 regp->fb_start = nv_crtc->fb.offset & ~3; 879 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); 880 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 881 882 /* Update the arbitration parameters. */ 883 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, 884 &arb_burst, &arb_lwm); 885 886 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 887 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 888 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 889 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 890 891 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 892 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 893 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 894 } 895 896 return 0; 897 } 898 899 static int 900 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 901 struct drm_framebuffer *old_fb) 902 { 903 int ret = nv_crtc_swap_fbs(crtc, old_fb); 904 if (ret) 905 return ret; 906 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 907 } 908 909 static int 910 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 911 struct drm_framebuffer *fb, 912 int x, int y, enum mode_set_atomic state) 913 { 914 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 915 struct drm_device *dev = drm->dev; 916 917 if (state == ENTER_ATOMIC_MODE_SET) 918 nouveau_fbcon_accel_save_disable(dev); 919 else 920 nouveau_fbcon_accel_restore(dev); 921 922 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 923 } 924 925 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 926 struct nouveau_bo *dst) 927 { 928 int width = nv_cursor_width(dev); 929 uint32_t pixel; 930 int i, j; 931 932 for (i = 0; i < width; i++) { 933 for (j = 0; j < width; j++) { 934 pixel = nouveau_bo_rd32(src, i*64 + j); 935 936 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 937 | (pixel & 0xf80000) >> 9 938 | (pixel & 0xf800) >> 6 939 | (pixel & 0xf8) >> 3); 940 } 941 } 942 } 943 944 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 945 struct nouveau_bo *dst) 946 { 947 uint32_t pixel; 948 int alpha, i; 949 950 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 951 * cursors (though NPM in combination with fp dithering may not work on 952 * nv11, from "nv" driver history) 953 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 954 * blob uses, however we get given PM cursors so we use PM mode 955 */ 956 for (i = 0; i < 64 * 64; i++) { 957 pixel = nouveau_bo_rd32(src, i); 958 959 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 960 * than" shouldn't happen; fix "equal to" case by adding one to 961 * alpha channel (slightly inaccurate, but so is attempting to 962 * get back to NPM images, due to limits of integer precision) 963 */ 964 alpha = pixel >> 24; 965 if (alpha > 0 && alpha < 255) 966 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 967 968 #ifdef __BIG_ENDIAN 969 { 970 struct nouveau_drm *drm = nouveau_drm(dev); 971 972 if (drm->device.info.chipset == 0x11) { 973 pixel = ((pixel & 0x000000ff) << 24) | 974 ((pixel & 0x0000ff00) << 8) | 975 ((pixel & 0x00ff0000) >> 8) | 976 ((pixel & 0xff000000) >> 24); 977 } 978 } 979 #endif 980 981 nouveau_bo_wr32(dst, i, pixel); 982 } 983 } 984 985 static int 986 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 987 uint32_t buffer_handle, uint32_t width, uint32_t height) 988 { 989 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 990 struct drm_device *dev = drm->dev; 991 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 992 struct nouveau_bo *cursor = NULL; 993 struct drm_gem_object *gem; 994 int ret = 0; 995 996 if (!buffer_handle) { 997 nv_crtc->cursor.hide(nv_crtc, true); 998 return 0; 999 } 1000 1001 if (width != 64 || height != 64) 1002 return -EINVAL; 1003 1004 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 1005 if (!gem) 1006 return -ENOENT; 1007 cursor = nouveau_gem_object(gem); 1008 1009 ret = nouveau_bo_map(cursor); 1010 if (ret) 1011 goto out; 1012 1013 if (drm->device.info.chipset >= 0x11) 1014 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1015 else 1016 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1017 1018 nouveau_bo_unmap(cursor); 1019 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 1020 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1021 nv_crtc->cursor.show(nv_crtc, true); 1022 out: 1023 drm_gem_object_unreference_unlocked(gem); 1024 return ret; 1025 } 1026 1027 static int 1028 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1029 { 1030 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1031 1032 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1033 return 0; 1034 } 1035 1036 int 1037 nouveau_crtc_set_config(struct drm_mode_set *set) 1038 { 1039 struct drm_device *dev; 1040 struct nouveau_drm *drm; 1041 int ret; 1042 struct drm_crtc *crtc; 1043 bool active = false; 1044 if (!set || !set->crtc) 1045 return -EINVAL; 1046 1047 dev = set->crtc->dev; 1048 1049 /* get a pm reference here */ 1050 ret = pm_runtime_get_sync(dev->dev); 1051 if (ret < 0 && ret != -EACCES) 1052 return ret; 1053 1054 ret = drm_crtc_helper_set_config(set); 1055 1056 drm = nouveau_drm(dev); 1057 1058 /* if we get here with no crtcs active then we can drop a reference */ 1059 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1060 if (crtc->enabled) 1061 active = true; 1062 } 1063 1064 pm_runtime_mark_last_busy(dev->dev); 1065 /* if we have active crtcs and we don't have a power ref, 1066 take the current one */ 1067 if (active && !drm->have_disp_power_ref) { 1068 drm->have_disp_power_ref = true; 1069 return ret; 1070 } 1071 /* if we have no active crtcs, then drop the power ref 1072 we got before */ 1073 if (!active && drm->have_disp_power_ref) { 1074 pm_runtime_put_autosuspend(dev->dev); 1075 drm->have_disp_power_ref = false; 1076 } 1077 /* drop the power reference we got coming in here */ 1078 pm_runtime_put_autosuspend(dev->dev); 1079 return ret; 1080 } 1081 1082 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1083 .save = nv_crtc_save, 1084 .restore = nv_crtc_restore, 1085 .cursor_set = nv04_crtc_cursor_set, 1086 .cursor_move = nv04_crtc_cursor_move, 1087 .gamma_set = nv_crtc_gamma_set, 1088 .set_config = nouveau_crtc_set_config, 1089 .page_flip = nouveau_crtc_page_flip, 1090 .destroy = nv_crtc_destroy, 1091 }; 1092 1093 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1094 .dpms = nv_crtc_dpms, 1095 .prepare = nv_crtc_prepare, 1096 .commit = nv_crtc_commit, 1097 .mode_fixup = nv_crtc_mode_fixup, 1098 .mode_set = nv_crtc_mode_set, 1099 .mode_set_base = nv04_crtc_mode_set_base, 1100 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1101 .load_lut = nv_crtc_gamma_load, 1102 .disable = nv_crtc_disable, 1103 }; 1104 1105 int 1106 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1107 { 1108 struct nouveau_crtc *nv_crtc; 1109 int ret, i; 1110 1111 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1112 if (!nv_crtc) 1113 return -ENOMEM; 1114 1115 for (i = 0; i < 256; i++) { 1116 nv_crtc->lut.r[i] = i << 8; 1117 nv_crtc->lut.g[i] = i << 8; 1118 nv_crtc->lut.b[i] = i << 8; 1119 } 1120 nv_crtc->lut.depth = 0; 1121 1122 nv_crtc->index = crtc_num; 1123 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1124 1125 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); 1126 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1127 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1128 1129 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, 1130 0, 0x0000, NULL, &nv_crtc->cursor.nvbo); 1131 if (!ret) { 1132 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); 1133 if (!ret) { 1134 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1135 if (ret) 1136 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1137 } 1138 if (ret) 1139 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1140 } 1141 1142 nv04_cursor_init(nv_crtc); 1143 1144 return 0; 1145 } 1146