1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2010 Juergen Beisert, Pengutronix 4 * Copyright (C) 2016 Marek Vasut <marex@denx.de> 5 * 6 * i.MX23/i.MX28/i.MX6SX MXSFB LCD controller driver. 7 */ 8 9 #ifndef __MXSFB_REGS_H__ 10 #define __MXSFB_REGS_H__ 11 12 #define REG_SET 4 13 #define REG_CLR 8 14 15 #define LCDC_CTRL 0x00 16 #define LCDC_CTRL1 0x10 17 #define LCDC_V3_TRANSFER_COUNT 0x20 18 #define LCDC_V4_TRANSFER_COUNT 0x30 19 #define LCDC_V4_CUR_BUF 0x40 20 #define LCDC_V4_NEXT_BUF 0x50 21 #define LCDC_V3_CUR_BUF 0x30 22 #define LCDC_V3_NEXT_BUF 0x40 23 #define LCDC_VDCTRL0 0x70 24 #define LCDC_VDCTRL1 0x80 25 #define LCDC_VDCTRL2 0x90 26 #define LCDC_VDCTRL3 0xa0 27 #define LCDC_VDCTRL4 0xb0 28 #define LCDC_V4_DEBUG0 0x1d0 29 #define LCDC_V3_DEBUG0 0x1f0 30 31 #define CTRL_SFTRST BIT(31) 32 #define CTRL_CLKGATE BIT(30) 33 #define CTRL_BYPASS_COUNT BIT(19) 34 #define CTRL_VSYNC_MODE BIT(18) 35 #define CTRL_DOTCLK_MODE BIT(17) 36 #define CTRL_DATA_SELECT BIT(16) 37 #define CTRL_BUS_WIDTH_16 (0 << 10) 38 #define CTRL_BUS_WIDTH_8 (1 << 10) 39 #define CTRL_BUS_WIDTH_18 (2 << 10) 40 #define CTRL_BUS_WIDTH_24 (3 << 10) 41 #define CTRL_BUS_WIDTH_MASK (0x3 << 10) 42 #define CTRL_WORD_LENGTH_16 (0 << 8) 43 #define CTRL_WORD_LENGTH_8 (1 << 8) 44 #define CTRL_WORD_LENGTH_18 (2 << 8) 45 #define CTRL_WORD_LENGTH_24 (3 << 8) 46 #define CTRL_MASTER BIT(5) 47 #define CTRL_DF16 BIT(3) 48 #define CTRL_DF18 BIT(2) 49 #define CTRL_DF24 BIT(1) 50 #define CTRL_RUN BIT(0) 51 52 #define CTRL1_FIFO_CLEAR BIT(21) 53 #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) 54 #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) 55 #define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13) 56 #define CTRL1_CUR_FRAME_DONE_IRQ BIT(9) 57 58 #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) 59 #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) 60 #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) 61 #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) 62 63 #define VDCTRL0_ENABLE_PRESENT BIT(28) 64 #define VDCTRL0_VSYNC_ACT_HIGH BIT(27) 65 #define VDCTRL0_HSYNC_ACT_HIGH BIT(26) 66 #define VDCTRL0_DOTCLK_ACT_FALLING BIT(25) 67 #define VDCTRL0_ENABLE_ACT_HIGH BIT(24) 68 #define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21) 69 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT BIT(20) 70 #define VDCTRL0_HALF_LINE BIT(19) 71 #define VDCTRL0_HALF_LINE_MODE BIT(18) 72 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) 73 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) 74 75 #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) 76 #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) 77 78 #define VDCTRL3_MUX_SYNC_SIGNALS BIT(29) 79 #define VDCTRL3_VSYNC_ONLY BIT(28) 80 #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) 81 #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) 82 #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) 83 #define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) 84 85 #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ 86 #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ 87 #define VDCTRL4_SYNC_SIGNALS_ON BIT(18) 88 #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) 89 90 #define DEBUG0_HSYNC BIT(26) 91 #define DEBUG0_VSYNC BIT(25) 92 93 #define MXSFB_MIN_XRES 120 94 #define MXSFB_MIN_YRES 120 95 #define MXSFB_MAX_XRES 0xffff 96 #define MXSFB_MAX_YRES 0xffff 97 98 #endif /* __MXSFB_REGS_H__ */ 99