1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include "msm_ringbuffer.h"
8 #include "msm_gpu.h"
9 
10 static uint num_hw_submissions = 8;
11 MODULE_PARM_DESC(num_hw_submissions, "The max # of jobs to write into ringbuffer (default 8)");
12 module_param(num_hw_submissions, uint, 0600);
13 
14 static struct dma_fence *msm_job_run(struct drm_sched_job *job)
15 {
16 	struct msm_gem_submit *submit = to_msm_submit(job);
17 	struct msm_fence_context *fctx = submit->ring->fctx;
18 	struct msm_gpu *gpu = submit->gpu;
19 	struct msm_drm_private *priv = gpu->dev->dev_private;
20 	int i;
21 
22 	msm_fence_init(submit->hw_fence, fctx);
23 
24 	mutex_lock(&priv->lru.lock);
25 
26 	for (i = 0; i < submit->nr_bos; i++) {
27 		struct drm_gem_object *obj = submit->bos[i].obj;
28 
29 		msm_gem_unpin_active(obj);
30 		submit->bos[i].flags &= ~BO_PINNED;
31 	}
32 
33 	mutex_unlock(&priv->lru.lock);
34 
35 	/* TODO move submit path over to using a per-ring lock.. */
36 	mutex_lock(&gpu->lock);
37 
38 	msm_gpu_submit(gpu, submit);
39 
40 	mutex_unlock(&gpu->lock);
41 
42 	return dma_fence_get(submit->hw_fence);
43 }
44 
45 static void msm_job_free(struct drm_sched_job *job)
46 {
47 	struct msm_gem_submit *submit = to_msm_submit(job);
48 
49 	drm_sched_job_cleanup(job);
50 	msm_gem_submit_put(submit);
51 }
52 
53 static const struct drm_sched_backend_ops msm_sched_ops = {
54 	.run_job = msm_job_run,
55 	.free_job = msm_job_free
56 };
57 
58 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
59 		void *memptrs, uint64_t memptrs_iova)
60 {
61 	struct msm_ringbuffer *ring;
62 	long sched_timeout;
63 	char name[32];
64 	int ret;
65 
66 	/* We assume everwhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */
67 	BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ));
68 
69 	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
70 	if (!ring) {
71 		ret = -ENOMEM;
72 		goto fail;
73 	}
74 
75 	ring->gpu = gpu;
76 	ring->id = id;
77 
78 	ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
79 		check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
80 		gpu->aspace, &ring->bo, &ring->iova);
81 
82 	if (IS_ERR(ring->start)) {
83 		ret = PTR_ERR(ring->start);
84 		ring->start = NULL;
85 		goto fail;
86 	}
87 
88 	msm_gem_object_set_name(ring->bo, "ring%d", id);
89 
90 	ring->end   = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2);
91 	ring->next  = ring->start;
92 	ring->cur   = ring->start;
93 
94 	ring->memptrs = memptrs;
95 	ring->memptrs_iova = memptrs_iova;
96 
97 	 /* currently managing hangcheck ourselves: */
98 	sched_timeout = MAX_SCHEDULE_TIMEOUT;
99 
100 	ret = drm_sched_init(&ring->sched, &msm_sched_ops,
101 			num_hw_submissions, 0, sched_timeout,
102 			NULL, NULL, to_msm_bo(ring->bo)->name, gpu->dev->dev);
103 	if (ret) {
104 		goto fail;
105 	}
106 
107 	INIT_LIST_HEAD(&ring->submits);
108 	spin_lock_init(&ring->submit_lock);
109 	spin_lock_init(&ring->preempt_lock);
110 
111 	snprintf(name, sizeof(name), "gpu-ring-%d", ring->id);
112 
113 	ring->fctx = msm_fence_context_alloc(gpu->dev, &ring->memptrs->fence, name);
114 
115 	return ring;
116 
117 fail:
118 	msm_ringbuffer_destroy(ring);
119 	return ERR_PTR(ret);
120 }
121 
122 void msm_ringbuffer_destroy(struct msm_ringbuffer *ring)
123 {
124 	if (IS_ERR_OR_NULL(ring))
125 		return;
126 
127 	drm_sched_fini(&ring->sched);
128 
129 	msm_fence_context_free(ring->fctx);
130 
131 	msm_gem_kernel_put(ring->bo, ring->gpu->aspace);
132 
133 	kfree(ring);
134 }
135