1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 /* For debugging crashes, userspace can: 8 * 9 * tail -f /sys/kernel/debug/dri/<minor>/rd > logfile.rd 10 * 11 * to log the cmdstream in a format that is understood by freedreno/cffdump 12 * utility. By comparing the last successfully completed fence #, to the 13 * cmdstream for the next fence, you can narrow down which process and submit 14 * caused the gpu crash/lockup. 15 * 16 * Additionally: 17 * 18 * tail -f /sys/kernel/debug/dri/<minor>/hangrd > logfile.rd 19 * 20 * will capture just the cmdstream from submits which triggered a GPU hang. 21 * 22 * This bypasses drm_debugfs_create_files() mainly because we need to use 23 * our own fops for a bit more control. In particular, we don't want to 24 * do anything if userspace doesn't have the debugfs file open. 25 * 26 * The module-param "rd_full", which defaults to false, enables snapshotting 27 * all (non-written) buffers in the submit, rather than just cmdstream bo's. 28 * This is useful to capture the contents of (for example) vbo's or textures, 29 * or shader programs (if not emitted inline in cmdstream). 30 */ 31 32 #ifdef CONFIG_DEBUG_FS 33 34 #include <linux/kfifo.h> 35 #include <linux/debugfs.h> 36 #include <linux/circ_buf.h> 37 #include <linux/wait.h> 38 39 #include "msm_drv.h" 40 #include "msm_gpu.h" 41 #include "msm_gem.h" 42 43 static bool rd_full = false; 44 MODULE_PARM_DESC(rd_full, "If true, $debugfs/.../rd will snapshot all buffer contents"); 45 module_param_named(rd_full, rd_full, bool, 0600); 46 47 enum rd_sect_type { 48 RD_NONE, 49 RD_TEST, /* ascii text */ 50 RD_CMD, /* ascii text */ 51 RD_GPUADDR, /* u32 gpuaddr, u32 size */ 52 RD_CONTEXT, /* raw dump */ 53 RD_CMDSTREAM, /* raw dump */ 54 RD_CMDSTREAM_ADDR, /* gpu addr of cmdstream */ 55 RD_PARAM, /* u32 param_type, u32 param_val, u32 bitlen */ 56 RD_FLUSH, /* empty, clear previous params */ 57 RD_PROGRAM, /* shader program, raw dump */ 58 RD_VERT_SHADER, 59 RD_FRAG_SHADER, 60 RD_BUFFER_CONTENTS, 61 RD_GPU_ID, 62 }; 63 64 #define BUF_SZ 512 /* should be power of 2 */ 65 66 /* space used: */ 67 #define circ_count(circ) \ 68 (CIRC_CNT((circ)->head, (circ)->tail, BUF_SZ)) 69 #define circ_count_to_end(circ) \ 70 (CIRC_CNT_TO_END((circ)->head, (circ)->tail, BUF_SZ)) 71 /* space available: */ 72 #define circ_space(circ) \ 73 (CIRC_SPACE((circ)->head, (circ)->tail, BUF_SZ)) 74 #define circ_space_to_end(circ) \ 75 (CIRC_SPACE_TO_END((circ)->head, (circ)->tail, BUF_SZ)) 76 77 struct msm_rd_state { 78 struct drm_device *dev; 79 80 bool open; 81 82 /* current submit to read out: */ 83 struct msm_gem_submit *submit; 84 85 /* fifo access is synchronized on the producer side by 86 * struct_mutex held by submit code (otherwise we could 87 * end up w/ cmds logged in different order than they 88 * were executed). And read_lock synchronizes the reads 89 */ 90 struct mutex read_lock; 91 92 wait_queue_head_t fifo_event; 93 struct circ_buf fifo; 94 95 char buf[BUF_SZ]; 96 }; 97 98 static void rd_write(struct msm_rd_state *rd, const void *buf, int sz) 99 { 100 struct circ_buf *fifo = &rd->fifo; 101 const char *ptr = buf; 102 103 while (sz > 0) { 104 char *fptr = &fifo->buf[fifo->head]; 105 int n; 106 107 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open); 108 if (!rd->open) 109 return; 110 111 /* Note that smp_load_acquire() is not strictly required 112 * as CIRC_SPACE_TO_END() does not access the tail more 113 * than once. 114 */ 115 n = min(sz, circ_space_to_end(&rd->fifo)); 116 memcpy(fptr, ptr, n); 117 118 smp_store_release(&fifo->head, (fifo->head + n) & (BUF_SZ - 1)); 119 sz -= n; 120 ptr += n; 121 122 wake_up_all(&rd->fifo_event); 123 } 124 } 125 126 static void rd_write_section(struct msm_rd_state *rd, 127 enum rd_sect_type type, const void *buf, int sz) 128 { 129 rd_write(rd, &type, 4); 130 rd_write(rd, &sz, 4); 131 rd_write(rd, buf, sz); 132 } 133 134 static ssize_t rd_read(struct file *file, char __user *buf, 135 size_t sz, loff_t *ppos) 136 { 137 struct msm_rd_state *rd = file->private_data; 138 struct circ_buf *fifo = &rd->fifo; 139 const char *fptr = &fifo->buf[fifo->tail]; 140 int n = 0, ret = 0; 141 142 mutex_lock(&rd->read_lock); 143 144 ret = wait_event_interruptible(rd->fifo_event, 145 circ_count(&rd->fifo) > 0); 146 if (ret) 147 goto out; 148 149 /* Note that smp_load_acquire() is not strictly required 150 * as CIRC_CNT_TO_END() does not access the head more than 151 * once. 152 */ 153 n = min_t(int, sz, circ_count_to_end(&rd->fifo)); 154 if (copy_to_user(buf, fptr, n)) { 155 ret = -EFAULT; 156 goto out; 157 } 158 159 smp_store_release(&fifo->tail, (fifo->tail + n) & (BUF_SZ - 1)); 160 *ppos += n; 161 162 wake_up_all(&rd->fifo_event); 163 164 out: 165 mutex_unlock(&rd->read_lock); 166 if (ret) 167 return ret; 168 return n; 169 } 170 171 static int rd_open(struct inode *inode, struct file *file) 172 { 173 struct msm_rd_state *rd = inode->i_private; 174 struct drm_device *dev = rd->dev; 175 struct msm_drm_private *priv = dev->dev_private; 176 struct msm_gpu *gpu = priv->gpu; 177 uint64_t val; 178 uint32_t gpu_id; 179 int ret = 0; 180 181 mutex_lock(&dev->struct_mutex); 182 183 if (rd->open || !gpu) { 184 ret = -EBUSY; 185 goto out; 186 } 187 188 file->private_data = rd; 189 rd->open = true; 190 191 /* the parsing tools need to know gpu-id to know which 192 * register database to load. 193 */ 194 gpu->funcs->get_param(gpu, MSM_PARAM_GPU_ID, &val); 195 gpu_id = val; 196 197 rd_write_section(rd, RD_GPU_ID, &gpu_id, sizeof(gpu_id)); 198 199 out: 200 mutex_unlock(&dev->struct_mutex); 201 return ret; 202 } 203 204 static int rd_release(struct inode *inode, struct file *file) 205 { 206 struct msm_rd_state *rd = inode->i_private; 207 208 rd->open = false; 209 wake_up_all(&rd->fifo_event); 210 211 return 0; 212 } 213 214 215 static const struct file_operations rd_debugfs_fops = { 216 .owner = THIS_MODULE, 217 .open = rd_open, 218 .read = rd_read, 219 .llseek = no_llseek, 220 .release = rd_release, 221 }; 222 223 224 static void rd_cleanup(struct msm_rd_state *rd) 225 { 226 if (!rd) 227 return; 228 229 mutex_destroy(&rd->read_lock); 230 kfree(rd); 231 } 232 233 static struct msm_rd_state *rd_init(struct drm_minor *minor, const char *name) 234 { 235 struct msm_rd_state *rd; 236 237 rd = kzalloc(sizeof(*rd), GFP_KERNEL); 238 if (!rd) 239 return ERR_PTR(-ENOMEM); 240 241 rd->dev = minor->dev; 242 rd->fifo.buf = rd->buf; 243 244 mutex_init(&rd->read_lock); 245 246 init_waitqueue_head(&rd->fifo_event); 247 248 debugfs_create_file(name, S_IFREG | S_IRUGO, minor->debugfs_root, rd, 249 &rd_debugfs_fops); 250 251 return rd; 252 } 253 254 int msm_rd_debugfs_init(struct drm_minor *minor) 255 { 256 struct msm_drm_private *priv = minor->dev->dev_private; 257 struct msm_rd_state *rd; 258 int ret; 259 260 /* only create on first minor: */ 261 if (priv->rd) 262 return 0; 263 264 rd = rd_init(minor, "rd"); 265 if (IS_ERR(rd)) { 266 ret = PTR_ERR(rd); 267 goto fail; 268 } 269 270 priv->rd = rd; 271 272 rd = rd_init(minor, "hangrd"); 273 if (IS_ERR(rd)) { 274 ret = PTR_ERR(rd); 275 goto fail; 276 } 277 278 priv->hangrd = rd; 279 280 return 0; 281 282 fail: 283 msm_rd_debugfs_cleanup(priv); 284 return ret; 285 } 286 287 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) 288 { 289 rd_cleanup(priv->rd); 290 priv->rd = NULL; 291 292 rd_cleanup(priv->hangrd); 293 priv->hangrd = NULL; 294 } 295 296 static void snapshot_buf(struct msm_rd_state *rd, 297 struct msm_gem_submit *submit, int idx, 298 uint64_t iova, uint32_t size) 299 { 300 struct msm_gem_object *obj = submit->bos[idx].obj; 301 unsigned offset = 0; 302 const char *buf; 303 304 if (iova) { 305 offset = iova - submit->bos[idx].iova; 306 } else { 307 iova = submit->bos[idx].iova; 308 size = obj->base.size; 309 } 310 311 /* 312 * Always write the GPUADDR header so can get a complete list of all the 313 * buffers in the cmd 314 */ 315 rd_write_section(rd, RD_GPUADDR, 316 (uint32_t[3]){ iova, size, iova >> 32 }, 12); 317 318 /* But only dump the contents of buffers marked READ */ 319 if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ)) 320 return; 321 322 buf = msm_gem_get_vaddr_active(&obj->base); 323 if (IS_ERR(buf)) 324 return; 325 326 buf += offset; 327 328 rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size); 329 330 msm_gem_put_vaddr(&obj->base); 331 } 332 333 static bool 334 should_dump(struct msm_gem_submit *submit, int idx) 335 { 336 return rd_full || (submit->bos[idx].flags & MSM_SUBMIT_BO_DUMP); 337 } 338 339 /* called under struct_mutex */ 340 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 341 const char *fmt, ...) 342 { 343 struct drm_device *dev = submit->dev; 344 struct task_struct *task; 345 char msg[256]; 346 int i, n; 347 348 if (!rd->open) 349 return; 350 351 /* writing into fifo is serialized by caller, and 352 * rd->read_lock is used to serialize the reads 353 */ 354 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 355 356 if (fmt) { 357 va_list args; 358 359 va_start(args, fmt); 360 n = vscnprintf(msg, sizeof(msg), fmt, args); 361 va_end(args); 362 363 rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4)); 364 } 365 366 rcu_read_lock(); 367 task = pid_task(submit->pid, PIDTYPE_PID); 368 if (task) { 369 n = scnprintf(msg, sizeof(msg), "%.*s/%d: fence=%u", 370 TASK_COMM_LEN, task->comm, 371 pid_nr(submit->pid), submit->seqno); 372 } else { 373 n = scnprintf(msg, sizeof(msg), "???/%d: fence=%u", 374 pid_nr(submit->pid), submit->seqno); 375 } 376 rcu_read_unlock(); 377 378 rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4)); 379 380 for (i = 0; i < submit->nr_bos; i++) 381 if (should_dump(submit, i)) 382 snapshot_buf(rd, submit, i, 0, 0); 383 384 for (i = 0; i < submit->nr_cmds; i++) { 385 uint64_t iova = submit->cmd[i].iova; 386 uint32_t szd = submit->cmd[i].size; /* in dwords */ 387 388 /* snapshot cmdstream bo's (if we haven't already): */ 389 if (!should_dump(submit, i)) { 390 snapshot_buf(rd, submit, submit->cmd[i].idx, 391 submit->cmd[i].iova, szd * 4); 392 } 393 394 switch (submit->cmd[i].type) { 395 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 396 /* ignore IB-targets, we've logged the buffer, the 397 * parser tool will follow the IB based on the logged 398 * buffer/gpuaddr, so nothing more to do. 399 */ 400 break; 401 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 402 case MSM_SUBMIT_CMD_BUF: 403 rd_write_section(rd, RD_CMDSTREAM_ADDR, 404 (uint32_t[3]){ iova, szd, iova >> 32 }, 12); 405 break; 406 } 407 } 408 } 409 #endif 410