1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/interconnect.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdesc.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 16 #include "msm_drv.h" 17 #include "msm_kms.h" 18 19 #define HW_REV 0x0 20 #define HW_INTR_STATUS 0x0010 21 22 #define UBWC_DEC_HW_VERSION 0x58 23 #define UBWC_STATIC 0x144 24 #define UBWC_CTRL_2 0x150 25 #define UBWC_PREDICTION_MODE 0x154 26 27 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 28 29 struct msm_mdss_data { 30 u32 ubwc_version; 31 /* can be read from register 0x58 */ 32 u32 ubwc_dec_version; 33 u32 ubwc_swizzle; 34 u32 ubwc_static; 35 u32 highest_bank_bit; 36 u32 macrotile_mode; 37 }; 38 39 struct msm_mdss { 40 struct device *dev; 41 42 void __iomem *mmio; 43 struct clk_bulk_data *clocks; 44 size_t num_clocks; 45 bool is_mdp5; 46 struct { 47 unsigned long enabled_mask; 48 struct irq_domain *domain; 49 } irq_controller; 50 const struct msm_mdss_data *mdss_data; 51 struct icc_path *path[2]; 52 u32 num_paths; 53 }; 54 55 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 56 struct msm_mdss *msm_mdss) 57 { 58 struct icc_path *path0; 59 struct icc_path *path1; 60 61 path0 = of_icc_get(dev, "mdp0-mem"); 62 if (IS_ERR_OR_NULL(path0)) 63 return PTR_ERR_OR_ZERO(path0); 64 65 msm_mdss->path[0] = path0; 66 msm_mdss->num_paths = 1; 67 68 path1 = of_icc_get(dev, "mdp1-mem"); 69 if (!IS_ERR_OR_NULL(path1)) { 70 msm_mdss->path[1] = path1; 71 msm_mdss->num_paths++; 72 } 73 74 return 0; 75 } 76 77 static void msm_mdss_put_icc_path(void *data) 78 { 79 struct msm_mdss *msm_mdss = data; 80 int i; 81 82 for (i = 0; i < msm_mdss->num_paths; i++) 83 icc_put(msm_mdss->path[i]); 84 } 85 86 static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) 87 { 88 int i; 89 90 for (i = 0; i < msm_mdss->num_paths; i++) 91 icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); 92 } 93 94 static void msm_mdss_irq(struct irq_desc *desc) 95 { 96 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 97 struct irq_chip *chip = irq_desc_get_chip(desc); 98 u32 interrupts; 99 100 chained_irq_enter(chip, desc); 101 102 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); 103 104 while (interrupts) { 105 irq_hw_number_t hwirq = fls(interrupts) - 1; 106 int rc; 107 108 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 109 hwirq); 110 if (rc < 0) { 111 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 112 hwirq, rc); 113 break; 114 } 115 116 interrupts &= ~(1 << hwirq); 117 } 118 119 chained_irq_exit(chip, desc); 120 } 121 122 static void msm_mdss_irq_mask(struct irq_data *irqd) 123 { 124 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 125 126 /* memory barrier */ 127 smp_mb__before_atomic(); 128 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 129 /* memory barrier */ 130 smp_mb__after_atomic(); 131 } 132 133 static void msm_mdss_irq_unmask(struct irq_data *irqd) 134 { 135 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 136 137 /* memory barrier */ 138 smp_mb__before_atomic(); 139 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 140 /* memory barrier */ 141 smp_mb__after_atomic(); 142 } 143 144 static struct irq_chip msm_mdss_irq_chip = { 145 .name = "msm_mdss", 146 .irq_mask = msm_mdss_irq_mask, 147 .irq_unmask = msm_mdss_irq_unmask, 148 }; 149 150 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 151 152 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 153 unsigned int irq, irq_hw_number_t hwirq) 154 { 155 struct msm_mdss *msm_mdss = domain->host_data; 156 157 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 158 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 159 160 return irq_set_chip_data(irq, msm_mdss); 161 } 162 163 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 164 .map = msm_mdss_irqdomain_map, 165 .xlate = irq_domain_xlate_onecell, 166 }; 167 168 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 169 { 170 struct device *dev; 171 struct irq_domain *domain; 172 173 dev = msm_mdss->dev; 174 175 domain = irq_domain_add_linear(dev->of_node, 32, 176 &msm_mdss_irqdomain_ops, msm_mdss); 177 if (!domain) { 178 dev_err(dev, "failed to add irq_domain\n"); 179 return -EINVAL; 180 } 181 182 msm_mdss->irq_controller.enabled_mask = 0; 183 msm_mdss->irq_controller.domain = domain; 184 185 return 0; 186 } 187 188 #define UBWC_1_0 0x10000000 189 #define UBWC_2_0 0x20000000 190 #define UBWC_3_0 0x30000000 191 #define UBWC_4_0 0x40000000 192 #define UBWC_4_3 0x40030000 193 194 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) 195 { 196 const struct msm_mdss_data *data = msm_mdss->mdss_data; 197 198 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); 199 } 200 201 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) 202 { 203 const struct msm_mdss_data *data = msm_mdss->mdss_data; 204 u32 value = (data->ubwc_swizzle & 0x1) | 205 (data->highest_bank_bit & 0x3) << 4 | 206 (data->macrotile_mode & 0x1) << 12; 207 208 if (data->ubwc_version == UBWC_3_0) 209 value |= BIT(10); 210 211 if (data->ubwc_version == UBWC_1_0) 212 value |= BIT(8); 213 214 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 215 } 216 217 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) 218 { 219 const struct msm_mdss_data *data = msm_mdss->mdss_data; 220 u32 value = (data->ubwc_swizzle & 0x7) | 221 (data->ubwc_static & 0x1) << 3 | 222 (data->highest_bank_bit & 0x7) << 4 | 223 (data->macrotile_mode & 0x1) << 12; 224 225 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 226 227 if (data->ubwc_version == UBWC_3_0) { 228 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); 229 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); 230 } else { 231 if (data->ubwc_dec_version == UBWC_4_3) 232 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); 233 else 234 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); 235 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); 236 } 237 } 238 239 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 240 { 241 int ret; 242 243 /* 244 * Several components have AXI clocks that can only be turned on if 245 * the interconnect is enabled (non-zero bandwidth). Let's make sure 246 * that the interconnects are at least at a minimum amount. 247 */ 248 msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); 249 250 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 251 if (ret) { 252 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 253 return ret; 254 } 255 256 /* 257 * Register access requires MDSS_MDP_CLK, which is not enabled by the 258 * mdss on mdp5 hardware. Skip it for now. 259 */ 260 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) 261 return 0; 262 263 /* 264 * ubwc config is part of the "mdss" region which is not accessible 265 * from the rest of the driver. hardcode known configurations here 266 * 267 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, 268 * UBWC_n and the rest of params comes from hw data. 269 */ 270 switch (msm_mdss->mdss_data->ubwc_dec_version) { 271 case UBWC_2_0: 272 msm_mdss_setup_ubwc_dec_20(msm_mdss); 273 break; 274 case UBWC_3_0: 275 msm_mdss_setup_ubwc_dec_30(msm_mdss); 276 break; 277 case UBWC_4_0: 278 case UBWC_4_3: 279 msm_mdss_setup_ubwc_dec_40(msm_mdss); 280 break; 281 default: 282 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", 283 msm_mdss->mdss_data->ubwc_dec_version); 284 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", 285 readl_relaxed(msm_mdss->mmio + HW_REV)); 286 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 287 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); 288 break; 289 } 290 291 return ret; 292 } 293 294 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 295 { 296 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 297 msm_mdss_icc_request_bw(msm_mdss, 0); 298 299 return 0; 300 } 301 302 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 303 { 304 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 305 int irq; 306 307 pm_runtime_suspend(msm_mdss->dev); 308 pm_runtime_disable(msm_mdss->dev); 309 irq_domain_remove(msm_mdss->irq_controller.domain); 310 msm_mdss->irq_controller.domain = NULL; 311 irq = platform_get_irq(pdev, 0); 312 irq_set_chained_handler_and_data(irq, NULL, NULL); 313 } 314 315 static int msm_mdss_reset(struct device *dev) 316 { 317 struct reset_control *reset; 318 319 reset = reset_control_get_optional_exclusive(dev, NULL); 320 if (!reset) { 321 /* Optional reset not specified */ 322 return 0; 323 } else if (IS_ERR(reset)) { 324 return dev_err_probe(dev, PTR_ERR(reset), 325 "failed to acquire mdss reset\n"); 326 } 327 328 reset_control_assert(reset); 329 /* 330 * Tests indicate that reset has to be held for some period of time, 331 * make it one frame in a typical system 332 */ 333 msleep(20); 334 reset_control_deassert(reset); 335 336 reset_control_put(reset); 337 338 return 0; 339 } 340 341 /* 342 * MDP5 MDSS uses at most three specified clocks. 343 */ 344 #define MDP5_MDSS_NUM_CLOCKS 3 345 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 346 { 347 struct clk_bulk_data *bulk; 348 int num_clocks = 0; 349 int ret; 350 351 if (!pdev) 352 return -EINVAL; 353 354 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 355 if (!bulk) 356 return -ENOMEM; 357 358 bulk[num_clocks++].id = "iface"; 359 bulk[num_clocks++].id = "bus"; 360 bulk[num_clocks++].id = "vsync"; 361 362 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 363 if (ret) 364 return ret; 365 366 *clocks = bulk; 367 368 return num_clocks; 369 } 370 371 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 372 { 373 struct msm_mdss *msm_mdss; 374 int ret; 375 int irq; 376 377 ret = msm_mdss_reset(&pdev->dev); 378 if (ret) 379 return ERR_PTR(ret); 380 381 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 382 if (!msm_mdss) 383 return ERR_PTR(-ENOMEM); 384 385 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 386 if (IS_ERR(msm_mdss->mmio)) 387 return ERR_CAST(msm_mdss->mmio); 388 389 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 390 391 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 392 if (ret) 393 return ERR_PTR(ret); 394 ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); 395 if (ret) 396 return ERR_PTR(ret); 397 398 if (is_mdp5) 399 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 400 else 401 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 402 if (ret < 0) { 403 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 404 return ERR_PTR(ret); 405 } 406 msm_mdss->num_clocks = ret; 407 msm_mdss->is_mdp5 = is_mdp5; 408 409 msm_mdss->dev = &pdev->dev; 410 411 irq = platform_get_irq(pdev, 0); 412 if (irq < 0) 413 return ERR_PTR(irq); 414 415 ret = _msm_mdss_irq_domain_add(msm_mdss); 416 if (ret) 417 return ERR_PTR(ret); 418 419 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 420 msm_mdss); 421 422 pm_runtime_enable(&pdev->dev); 423 424 return msm_mdss; 425 } 426 427 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 428 { 429 struct msm_mdss *mdss = dev_get_drvdata(dev); 430 431 DBG(""); 432 433 return msm_mdss_disable(mdss); 434 } 435 436 static int __maybe_unused mdss_runtime_resume(struct device *dev) 437 { 438 struct msm_mdss *mdss = dev_get_drvdata(dev); 439 440 DBG(""); 441 442 return msm_mdss_enable(mdss); 443 } 444 445 static int __maybe_unused mdss_pm_suspend(struct device *dev) 446 { 447 448 if (pm_runtime_suspended(dev)) 449 return 0; 450 451 return mdss_runtime_suspend(dev); 452 } 453 454 static int __maybe_unused mdss_pm_resume(struct device *dev) 455 { 456 if (pm_runtime_suspended(dev)) 457 return 0; 458 459 return mdss_runtime_resume(dev); 460 } 461 462 static const struct dev_pm_ops mdss_pm_ops = { 463 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 464 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 465 }; 466 467 static int mdss_probe(struct platform_device *pdev) 468 { 469 struct msm_mdss *mdss; 470 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 471 struct device *dev = &pdev->dev; 472 int ret; 473 474 mdss = msm_mdss_init(pdev, is_mdp5); 475 if (IS_ERR(mdss)) 476 return PTR_ERR(mdss); 477 478 mdss->mdss_data = of_device_get_match_data(&pdev->dev); 479 480 platform_set_drvdata(pdev, mdss); 481 482 /* 483 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 484 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 485 * Populate the children devices, find the MDP5/DPU node, and then add 486 * the interfaces to our components list. 487 */ 488 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 489 if (ret) { 490 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 491 msm_mdss_destroy(mdss); 492 return ret; 493 } 494 495 return 0; 496 } 497 498 static int mdss_remove(struct platform_device *pdev) 499 { 500 struct msm_mdss *mdss = platform_get_drvdata(pdev); 501 502 of_platform_depopulate(&pdev->dev); 503 504 msm_mdss_destroy(mdss); 505 506 return 0; 507 } 508 509 static const struct msm_mdss_data sc7180_data = { 510 .ubwc_version = UBWC_2_0, 511 .ubwc_dec_version = UBWC_2_0, 512 .ubwc_static = 0x1e, 513 }; 514 515 static const struct msm_mdss_data sc7280_data = { 516 .ubwc_version = UBWC_3_0, 517 .ubwc_dec_version = UBWC_4_0, 518 .ubwc_swizzle = 6, 519 .ubwc_static = 1, 520 .highest_bank_bit = 1, 521 .macrotile_mode = 1, 522 }; 523 524 static const struct msm_mdss_data sc8180x_data = { 525 .ubwc_version = UBWC_3_0, 526 .ubwc_dec_version = UBWC_3_0, 527 .highest_bank_bit = 3, 528 .macrotile_mode = 1, 529 }; 530 531 static const struct msm_mdss_data sc8280xp_data = { 532 .ubwc_version = UBWC_4_0, 533 .ubwc_dec_version = UBWC_4_0, 534 .ubwc_swizzle = 6, 535 .ubwc_static = 1, 536 .highest_bank_bit = 2, 537 .macrotile_mode = 1, 538 }; 539 540 static const struct msm_mdss_data sdm845_data = { 541 .ubwc_version = UBWC_2_0, 542 .ubwc_dec_version = UBWC_2_0, 543 .highest_bank_bit = 2, 544 }; 545 546 static const struct msm_mdss_data sm6350_data = { 547 .ubwc_version = UBWC_2_0, 548 .ubwc_dec_version = UBWC_2_0, 549 .ubwc_swizzle = 6, 550 .ubwc_static = 0x1e, 551 .highest_bank_bit = 1, 552 }; 553 554 static const struct msm_mdss_data sm8150_data = { 555 .ubwc_version = UBWC_3_0, 556 .ubwc_dec_version = UBWC_3_0, 557 .highest_bank_bit = 2, 558 }; 559 560 static const struct msm_mdss_data sm6115_data = { 561 .ubwc_version = UBWC_1_0, 562 .ubwc_dec_version = UBWC_2_0, 563 .ubwc_swizzle = 7, 564 .ubwc_static = 0x11f, 565 }; 566 567 static const struct msm_mdss_data sm8250_data = { 568 .ubwc_version = UBWC_4_0, 569 .ubwc_dec_version = UBWC_4_0, 570 .ubwc_swizzle = 6, 571 .ubwc_static = 1, 572 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 573 .highest_bank_bit = 3, 574 .macrotile_mode = 1, 575 }; 576 577 static const struct msm_mdss_data sm8550_data = { 578 .ubwc_version = UBWC_4_0, 579 .ubwc_dec_version = UBWC_4_3, 580 .ubwc_swizzle = 6, 581 .ubwc_static = 1, 582 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 583 .highest_bank_bit = 3, 584 .macrotile_mode = 1, 585 }; 586 587 static const struct of_device_id mdss_dt_match[] = { 588 { .compatible = "qcom,mdss" }, 589 { .compatible = "qcom,msm8998-mdss" }, 590 { .compatible = "qcom,qcm2290-mdss" }, 591 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, 592 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, 593 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, 594 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, 595 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, 596 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, 597 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, 598 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, 599 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, 600 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, 601 { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, 602 { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data }, 603 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, 604 {} 605 }; 606 MODULE_DEVICE_TABLE(of, mdss_dt_match); 607 608 static struct platform_driver mdss_platform_driver = { 609 .probe = mdss_probe, 610 .remove = mdss_remove, 611 .driver = { 612 .name = "msm-mdss", 613 .of_match_table = mdss_dt_match, 614 .pm = &mdss_pm_ops, 615 }, 616 }; 617 618 void __init msm_mdss_register(void) 619 { 620 platform_driver_register(&mdss_platform_driver); 621 } 622 623 void __exit msm_mdss_unregister(void) 624 { 625 platform_driver_unregister(&mdss_platform_driver); 626 } 627