1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/interconnect.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdesc.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 16 #include "msm_drv.h" 17 #include "msm_kms.h" 18 19 /* for DPU_HW_* defines */ 20 #include "disp/dpu1/dpu_hw_catalog.h" 21 22 #define HW_REV 0x0 23 #define HW_INTR_STATUS 0x0010 24 25 #define UBWC_DEC_HW_VERSION 0x58 26 #define UBWC_STATIC 0x144 27 #define UBWC_CTRL_2 0x150 28 #define UBWC_PREDICTION_MODE 0x154 29 30 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 31 32 struct msm_mdss { 33 struct device *dev; 34 35 void __iomem *mmio; 36 struct clk_bulk_data *clocks; 37 size_t num_clocks; 38 bool is_mdp5; 39 struct { 40 unsigned long enabled_mask; 41 struct irq_domain *domain; 42 } irq_controller; 43 struct icc_path *path[2]; 44 u32 num_paths; 45 }; 46 47 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 48 struct msm_mdss *msm_mdss) 49 { 50 struct icc_path *path0; 51 struct icc_path *path1; 52 53 path0 = of_icc_get(dev, "mdp0-mem"); 54 if (IS_ERR_OR_NULL(path0)) 55 return PTR_ERR_OR_ZERO(path0); 56 57 msm_mdss->path[0] = path0; 58 msm_mdss->num_paths = 1; 59 60 path1 = of_icc_get(dev, "mdp1-mem"); 61 if (!IS_ERR_OR_NULL(path1)) { 62 msm_mdss->path[1] = path1; 63 msm_mdss->num_paths++; 64 } 65 66 return 0; 67 } 68 69 static void msm_mdss_put_icc_path(void *data) 70 { 71 struct msm_mdss *msm_mdss = data; 72 int i; 73 74 for (i = 0; i < msm_mdss->num_paths; i++) 75 icc_put(msm_mdss->path[i]); 76 } 77 78 static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) 79 { 80 int i; 81 82 for (i = 0; i < msm_mdss->num_paths; i++) 83 icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); 84 } 85 86 static void msm_mdss_irq(struct irq_desc *desc) 87 { 88 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 89 struct irq_chip *chip = irq_desc_get_chip(desc); 90 u32 interrupts; 91 92 chained_irq_enter(chip, desc); 93 94 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); 95 96 while (interrupts) { 97 irq_hw_number_t hwirq = fls(interrupts) - 1; 98 int rc; 99 100 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 101 hwirq); 102 if (rc < 0) { 103 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 104 hwirq, rc); 105 break; 106 } 107 108 interrupts &= ~(1 << hwirq); 109 } 110 111 chained_irq_exit(chip, desc); 112 } 113 114 static void msm_mdss_irq_mask(struct irq_data *irqd) 115 { 116 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 117 118 /* memory barrier */ 119 smp_mb__before_atomic(); 120 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 121 /* memory barrier */ 122 smp_mb__after_atomic(); 123 } 124 125 static void msm_mdss_irq_unmask(struct irq_data *irqd) 126 { 127 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 128 129 /* memory barrier */ 130 smp_mb__before_atomic(); 131 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 132 /* memory barrier */ 133 smp_mb__after_atomic(); 134 } 135 136 static struct irq_chip msm_mdss_irq_chip = { 137 .name = "msm_mdss", 138 .irq_mask = msm_mdss_irq_mask, 139 .irq_unmask = msm_mdss_irq_unmask, 140 }; 141 142 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 143 144 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 145 unsigned int irq, irq_hw_number_t hwirq) 146 { 147 struct msm_mdss *msm_mdss = domain->host_data; 148 149 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 150 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 151 152 return irq_set_chip_data(irq, msm_mdss); 153 } 154 155 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 156 .map = msm_mdss_irqdomain_map, 157 .xlate = irq_domain_xlate_onecell, 158 }; 159 160 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 161 { 162 struct device *dev; 163 struct irq_domain *domain; 164 165 dev = msm_mdss->dev; 166 167 domain = irq_domain_add_linear(dev->of_node, 32, 168 &msm_mdss_irqdomain_ops, msm_mdss); 169 if (!domain) { 170 dev_err(dev, "failed to add irq_domain\n"); 171 return -EINVAL; 172 } 173 174 msm_mdss->irq_controller.enabled_mask = 0; 175 msm_mdss->irq_controller.domain = domain; 176 177 return 0; 178 } 179 180 #define UBWC_1_0 0x10000000 181 #define UBWC_2_0 0x20000000 182 #define UBWC_3_0 0x30000000 183 #define UBWC_4_0 0x40000000 184 185 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss, 186 u32 ubwc_static) 187 { 188 writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC); 189 } 190 191 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss, 192 unsigned int ubwc_version, 193 u32 ubwc_swizzle, 194 u32 highest_bank_bit, 195 u32 macrotile_mode) 196 { 197 u32 value = (ubwc_swizzle & 0x1) | 198 (highest_bank_bit & 0x3) << 4 | 199 (macrotile_mode & 0x1) << 12; 200 201 if (ubwc_version == UBWC_3_0) 202 value |= BIT(10); 203 204 if (ubwc_version == UBWC_1_0) 205 value |= BIT(8); 206 207 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 208 } 209 210 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss, 211 unsigned int ubwc_version, 212 u32 ubwc_swizzle, 213 u32 ubwc_static, 214 u32 highest_bank_bit, 215 u32 macrotile_mode) 216 { 217 u32 value = (ubwc_swizzle & 0x7) | 218 (ubwc_static & 0x1) << 3 | 219 (highest_bank_bit & 0x7) << 4 | 220 (macrotile_mode & 0x1) << 12; 221 222 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 223 224 if (ubwc_version == UBWC_3_0) { 225 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); 226 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); 227 } else { 228 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); 229 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); 230 } 231 } 232 233 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 234 { 235 int ret; 236 u32 hw_rev; 237 238 /* 239 * Several components have AXI clocks that can only be turned on if 240 * the interconnect is enabled (non-zero bandwidth). Let's make sure 241 * that the interconnects are at least at a minimum amount. 242 */ 243 msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); 244 245 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 246 if (ret) { 247 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 248 return ret; 249 } 250 251 /* 252 * HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on 253 * mdp5 hardware. Skip reading it for now. 254 */ 255 if (msm_mdss->is_mdp5) 256 return 0; 257 258 hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV); 259 dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev); 260 dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 261 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); 262 263 /* 264 * ubwc config is part of the "mdss" region which is not accessible 265 * from the rest of the driver. hardcode known configurations here 266 * 267 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, 268 * UBWC_n and the rest of params comes from hw_catalog. 269 * Unforunately this driver can not access hw catalog, so we have to 270 * hardcode them here. 271 */ 272 switch (hw_rev) { 273 case DPU_HW_VER_500: 274 case DPU_HW_VER_501: 275 msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0); 276 break; 277 case DPU_HW_VER_600: 278 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 279 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); 280 break; 281 case DPU_HW_VER_620: 282 /* UBWC_2_0 */ 283 msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); 284 break; 285 case DPU_HW_VER_630: 286 /* UBWC_2_0 */ 287 msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f); 288 break; 289 case DPU_HW_VER_700: 290 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 291 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); 292 break; 293 case DPU_HW_VER_720: 294 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); 295 break; 296 case DPU_HW_VER_800: 297 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 2, 1); 298 break; 299 case DPU_HW_VER_810: 300 case DPU_HW_VER_900: 301 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 302 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); 303 break; 304 } 305 306 return ret; 307 } 308 309 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 310 { 311 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 312 msm_mdss_icc_request_bw(msm_mdss, 0); 313 314 return 0; 315 } 316 317 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 318 { 319 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 320 int irq; 321 322 pm_runtime_suspend(msm_mdss->dev); 323 pm_runtime_disable(msm_mdss->dev); 324 irq_domain_remove(msm_mdss->irq_controller.domain); 325 msm_mdss->irq_controller.domain = NULL; 326 irq = platform_get_irq(pdev, 0); 327 irq_set_chained_handler_and_data(irq, NULL, NULL); 328 } 329 330 static int msm_mdss_reset(struct device *dev) 331 { 332 struct reset_control *reset; 333 334 reset = reset_control_get_optional_exclusive(dev, NULL); 335 if (!reset) { 336 /* Optional reset not specified */ 337 return 0; 338 } else if (IS_ERR(reset)) { 339 return dev_err_probe(dev, PTR_ERR(reset), 340 "failed to acquire mdss reset\n"); 341 } 342 343 reset_control_assert(reset); 344 /* 345 * Tests indicate that reset has to be held for some period of time, 346 * make it one frame in a typical system 347 */ 348 msleep(20); 349 reset_control_deassert(reset); 350 351 reset_control_put(reset); 352 353 return 0; 354 } 355 356 /* 357 * MDP5 MDSS uses at most three specified clocks. 358 */ 359 #define MDP5_MDSS_NUM_CLOCKS 3 360 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 361 { 362 struct clk_bulk_data *bulk; 363 int num_clocks = 0; 364 int ret; 365 366 if (!pdev) 367 return -EINVAL; 368 369 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 370 if (!bulk) 371 return -ENOMEM; 372 373 bulk[num_clocks++].id = "iface"; 374 bulk[num_clocks++].id = "bus"; 375 bulk[num_clocks++].id = "vsync"; 376 377 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 378 if (ret) 379 return ret; 380 381 *clocks = bulk; 382 383 return num_clocks; 384 } 385 386 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 387 { 388 struct msm_mdss *msm_mdss; 389 int ret; 390 int irq; 391 392 ret = msm_mdss_reset(&pdev->dev); 393 if (ret) 394 return ERR_PTR(ret); 395 396 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 397 if (!msm_mdss) 398 return ERR_PTR(-ENOMEM); 399 400 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 401 if (IS_ERR(msm_mdss->mmio)) 402 return ERR_CAST(msm_mdss->mmio); 403 404 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 405 406 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 407 if (ret) 408 return ERR_PTR(ret); 409 ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); 410 if (ret) 411 return ERR_PTR(ret); 412 413 if (is_mdp5) 414 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 415 else 416 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 417 if (ret < 0) { 418 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 419 return ERR_PTR(ret); 420 } 421 msm_mdss->num_clocks = ret; 422 msm_mdss->is_mdp5 = is_mdp5; 423 424 msm_mdss->dev = &pdev->dev; 425 426 irq = platform_get_irq(pdev, 0); 427 if (irq < 0) 428 return ERR_PTR(irq); 429 430 ret = _msm_mdss_irq_domain_add(msm_mdss); 431 if (ret) 432 return ERR_PTR(ret); 433 434 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 435 msm_mdss); 436 437 pm_runtime_enable(&pdev->dev); 438 439 return msm_mdss; 440 } 441 442 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 443 { 444 struct msm_mdss *mdss = dev_get_drvdata(dev); 445 446 DBG(""); 447 448 return msm_mdss_disable(mdss); 449 } 450 451 static int __maybe_unused mdss_runtime_resume(struct device *dev) 452 { 453 struct msm_mdss *mdss = dev_get_drvdata(dev); 454 455 DBG(""); 456 457 return msm_mdss_enable(mdss); 458 } 459 460 static int __maybe_unused mdss_pm_suspend(struct device *dev) 461 { 462 463 if (pm_runtime_suspended(dev)) 464 return 0; 465 466 return mdss_runtime_suspend(dev); 467 } 468 469 static int __maybe_unused mdss_pm_resume(struct device *dev) 470 { 471 if (pm_runtime_suspended(dev)) 472 return 0; 473 474 return mdss_runtime_resume(dev); 475 } 476 477 static const struct dev_pm_ops mdss_pm_ops = { 478 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 479 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 480 }; 481 482 static int mdss_probe(struct platform_device *pdev) 483 { 484 struct msm_mdss *mdss; 485 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 486 struct device *dev = &pdev->dev; 487 int ret; 488 489 mdss = msm_mdss_init(pdev, is_mdp5); 490 if (IS_ERR(mdss)) 491 return PTR_ERR(mdss); 492 493 platform_set_drvdata(pdev, mdss); 494 495 /* 496 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 497 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 498 * Populate the children devices, find the MDP5/DPU node, and then add 499 * the interfaces to our components list. 500 */ 501 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 502 if (ret) { 503 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 504 msm_mdss_destroy(mdss); 505 return ret; 506 } 507 508 return 0; 509 } 510 511 static int mdss_remove(struct platform_device *pdev) 512 { 513 struct msm_mdss *mdss = platform_get_drvdata(pdev); 514 515 of_platform_depopulate(&pdev->dev); 516 517 msm_mdss_destroy(mdss); 518 519 return 0; 520 } 521 522 static const struct of_device_id mdss_dt_match[] = { 523 { .compatible = "qcom,mdss" }, 524 { .compatible = "qcom,msm8998-mdss" }, 525 { .compatible = "qcom,qcm2290-mdss" }, 526 { .compatible = "qcom,sdm845-mdss" }, 527 { .compatible = "qcom,sc7180-mdss" }, 528 { .compatible = "qcom,sc7280-mdss" }, 529 { .compatible = "qcom,sc8180x-mdss" }, 530 { .compatible = "qcom,sc8280xp-mdss" }, 531 { .compatible = "qcom,sm6115-mdss" }, 532 { .compatible = "qcom,sm8150-mdss" }, 533 { .compatible = "qcom,sm8250-mdss" }, 534 { .compatible = "qcom,sm8350-mdss" }, 535 { .compatible = "qcom,sm8450-mdss" }, 536 { .compatible = "qcom,sm8550-mdss" }, 537 {} 538 }; 539 MODULE_DEVICE_TABLE(of, mdss_dt_match); 540 541 static struct platform_driver mdss_platform_driver = { 542 .probe = mdss_probe, 543 .remove = mdss_remove, 544 .driver = { 545 .name = "msm-mdss", 546 .of_match_table = mdss_dt_match, 547 .pm = &mdss_pm_ops, 548 }, 549 }; 550 551 void __init msm_mdss_register(void) 552 { 553 platform_driver_register(&mdss_platform_driver); 554 } 555 556 void __exit msm_mdss_unregister(void) 557 { 558 platform_driver_unregister(&mdss_platform_driver); 559 } 560