1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/interconnect.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdesc.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include "msm_drv.h" 19 #include "msm_kms.h" 20 21 #define HW_REV 0x0 22 #define HW_INTR_STATUS 0x0010 23 24 #define UBWC_DEC_HW_VERSION 0x58 25 #define UBWC_STATIC 0x144 26 #define UBWC_CTRL_2 0x150 27 #define UBWC_PREDICTION_MODE 0x154 28 29 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 30 31 struct msm_mdss_data { 32 u32 ubwc_version; 33 /* can be read from register 0x58 */ 34 u32 ubwc_dec_version; 35 u32 ubwc_swizzle; 36 u32 ubwc_static; 37 u32 highest_bank_bit; 38 u32 macrotile_mode; 39 }; 40 41 struct msm_mdss { 42 struct device *dev; 43 44 void __iomem *mmio; 45 struct clk_bulk_data *clocks; 46 size_t num_clocks; 47 bool is_mdp5; 48 struct { 49 unsigned long enabled_mask; 50 struct irq_domain *domain; 51 } irq_controller; 52 const struct msm_mdss_data *mdss_data; 53 struct icc_path *path[2]; 54 u32 num_paths; 55 }; 56 57 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 58 struct msm_mdss *msm_mdss) 59 { 60 struct icc_path *path0; 61 struct icc_path *path1; 62 63 path0 = of_icc_get(dev, "mdp0-mem"); 64 if (IS_ERR_OR_NULL(path0)) 65 return PTR_ERR_OR_ZERO(path0); 66 67 msm_mdss->path[0] = path0; 68 msm_mdss->num_paths = 1; 69 70 path1 = of_icc_get(dev, "mdp1-mem"); 71 if (!IS_ERR_OR_NULL(path1)) { 72 msm_mdss->path[1] = path1; 73 msm_mdss->num_paths++; 74 } 75 76 return 0; 77 } 78 79 static void msm_mdss_put_icc_path(void *data) 80 { 81 struct msm_mdss *msm_mdss = data; 82 int i; 83 84 for (i = 0; i < msm_mdss->num_paths; i++) 85 icc_put(msm_mdss->path[i]); 86 } 87 88 static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) 89 { 90 int i; 91 92 for (i = 0; i < msm_mdss->num_paths; i++) 93 icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); 94 } 95 96 static void msm_mdss_irq(struct irq_desc *desc) 97 { 98 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 99 struct irq_chip *chip = irq_desc_get_chip(desc); 100 u32 interrupts; 101 102 chained_irq_enter(chip, desc); 103 104 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); 105 106 while (interrupts) { 107 irq_hw_number_t hwirq = fls(interrupts) - 1; 108 int rc; 109 110 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 111 hwirq); 112 if (rc < 0) { 113 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 114 hwirq, rc); 115 break; 116 } 117 118 interrupts &= ~(1 << hwirq); 119 } 120 121 chained_irq_exit(chip, desc); 122 } 123 124 static void msm_mdss_irq_mask(struct irq_data *irqd) 125 { 126 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 127 128 /* memory barrier */ 129 smp_mb__before_atomic(); 130 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 131 /* memory barrier */ 132 smp_mb__after_atomic(); 133 } 134 135 static void msm_mdss_irq_unmask(struct irq_data *irqd) 136 { 137 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 138 139 /* memory barrier */ 140 smp_mb__before_atomic(); 141 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 142 /* memory barrier */ 143 smp_mb__after_atomic(); 144 } 145 146 static struct irq_chip msm_mdss_irq_chip = { 147 .name = "msm_mdss", 148 .irq_mask = msm_mdss_irq_mask, 149 .irq_unmask = msm_mdss_irq_unmask, 150 }; 151 152 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 153 154 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 155 unsigned int irq, irq_hw_number_t hwirq) 156 { 157 struct msm_mdss *msm_mdss = domain->host_data; 158 159 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 160 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 161 162 return irq_set_chip_data(irq, msm_mdss); 163 } 164 165 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 166 .map = msm_mdss_irqdomain_map, 167 .xlate = irq_domain_xlate_onecell, 168 }; 169 170 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 171 { 172 struct device *dev; 173 struct irq_domain *domain; 174 175 dev = msm_mdss->dev; 176 177 domain = irq_domain_add_linear(dev->of_node, 32, 178 &msm_mdss_irqdomain_ops, msm_mdss); 179 if (!domain) { 180 dev_err(dev, "failed to add irq_domain\n"); 181 return -EINVAL; 182 } 183 184 msm_mdss->irq_controller.enabled_mask = 0; 185 msm_mdss->irq_controller.domain = domain; 186 187 return 0; 188 } 189 190 #define UBWC_1_0 0x10000000 191 #define UBWC_2_0 0x20000000 192 #define UBWC_3_0 0x30000000 193 #define UBWC_4_0 0x40000000 194 195 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) 196 { 197 const struct msm_mdss_data *data = msm_mdss->mdss_data; 198 199 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); 200 } 201 202 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) 203 { 204 const struct msm_mdss_data *data = msm_mdss->mdss_data; 205 u32 value = (data->ubwc_swizzle & 0x1) | 206 (data->highest_bank_bit & 0x3) << 4 | 207 (data->macrotile_mode & 0x1) << 12; 208 209 if (data->ubwc_version == UBWC_3_0) 210 value |= BIT(10); 211 212 if (data->ubwc_version == UBWC_1_0) 213 value |= BIT(8); 214 215 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 216 } 217 218 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) 219 { 220 const struct msm_mdss_data *data = msm_mdss->mdss_data; 221 u32 value = (data->ubwc_swizzle & 0x7) | 222 (data->ubwc_static & 0x1) << 3 | 223 (data->highest_bank_bit & 0x7) << 4 | 224 (data->macrotile_mode & 0x1) << 12; 225 226 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 227 228 if (data->ubwc_version == UBWC_3_0) { 229 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); 230 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); 231 } else { 232 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); 233 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); 234 } 235 } 236 237 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 238 { 239 int ret; 240 241 /* 242 * Several components have AXI clocks that can only be turned on if 243 * the interconnect is enabled (non-zero bandwidth). Let's make sure 244 * that the interconnects are at least at a minimum amount. 245 */ 246 msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); 247 248 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 249 if (ret) { 250 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 251 return ret; 252 } 253 254 /* 255 * Register access requires MDSS_MDP_CLK, which is not enabled by the 256 * mdss on mdp5 hardware. Skip it for now. 257 */ 258 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) 259 return 0; 260 261 /* 262 * ubwc config is part of the "mdss" region which is not accessible 263 * from the rest of the driver. hardcode known configurations here 264 * 265 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, 266 * UBWC_n and the rest of params comes from hw data. 267 */ 268 switch (msm_mdss->mdss_data->ubwc_dec_version) { 269 case UBWC_2_0: 270 msm_mdss_setup_ubwc_dec_20(msm_mdss); 271 break; 272 case UBWC_3_0: 273 msm_mdss_setup_ubwc_dec_30(msm_mdss); 274 break; 275 case UBWC_4_0: 276 msm_mdss_setup_ubwc_dec_40(msm_mdss); 277 break; 278 default: 279 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", 280 msm_mdss->mdss_data->ubwc_dec_version); 281 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", 282 readl_relaxed(msm_mdss->mmio + HW_REV)); 283 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 284 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); 285 break; 286 } 287 288 return ret; 289 } 290 291 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 292 { 293 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 294 msm_mdss_icc_request_bw(msm_mdss, 0); 295 296 return 0; 297 } 298 299 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 300 { 301 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 302 int irq; 303 304 pm_runtime_suspend(msm_mdss->dev); 305 pm_runtime_disable(msm_mdss->dev); 306 irq_domain_remove(msm_mdss->irq_controller.domain); 307 msm_mdss->irq_controller.domain = NULL; 308 irq = platform_get_irq(pdev, 0); 309 irq_set_chained_handler_and_data(irq, NULL, NULL); 310 } 311 312 static int msm_mdss_reset(struct device *dev) 313 { 314 struct reset_control *reset; 315 316 reset = reset_control_get_optional_exclusive(dev, NULL); 317 if (!reset) { 318 /* Optional reset not specified */ 319 return 0; 320 } else if (IS_ERR(reset)) { 321 return dev_err_probe(dev, PTR_ERR(reset), 322 "failed to acquire mdss reset\n"); 323 } 324 325 reset_control_assert(reset); 326 /* 327 * Tests indicate that reset has to be held for some period of time, 328 * make it one frame in a typical system 329 */ 330 msleep(20); 331 reset_control_deassert(reset); 332 333 reset_control_put(reset); 334 335 return 0; 336 } 337 338 /* 339 * MDP5 MDSS uses at most three specified clocks. 340 */ 341 #define MDP5_MDSS_NUM_CLOCKS 3 342 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 343 { 344 struct clk_bulk_data *bulk; 345 int num_clocks = 0; 346 int ret; 347 348 if (!pdev) 349 return -EINVAL; 350 351 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 352 if (!bulk) 353 return -ENOMEM; 354 355 bulk[num_clocks++].id = "iface"; 356 bulk[num_clocks++].id = "bus"; 357 bulk[num_clocks++].id = "vsync"; 358 359 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 360 if (ret) 361 return ret; 362 363 *clocks = bulk; 364 365 return num_clocks; 366 } 367 368 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 369 { 370 struct msm_mdss *msm_mdss; 371 int ret; 372 int irq; 373 374 ret = msm_mdss_reset(&pdev->dev); 375 if (ret) 376 return ERR_PTR(ret); 377 378 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 379 if (!msm_mdss) 380 return ERR_PTR(-ENOMEM); 381 382 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 383 if (IS_ERR(msm_mdss->mmio)) 384 return ERR_CAST(msm_mdss->mmio); 385 386 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 387 388 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 389 if (ret) 390 return ERR_PTR(ret); 391 ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); 392 if (ret) 393 return ERR_PTR(ret); 394 395 if (is_mdp5) 396 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 397 else 398 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 399 if (ret < 0) { 400 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 401 return ERR_PTR(ret); 402 } 403 msm_mdss->num_clocks = ret; 404 msm_mdss->is_mdp5 = is_mdp5; 405 406 msm_mdss->dev = &pdev->dev; 407 408 irq = platform_get_irq(pdev, 0); 409 if (irq < 0) 410 return ERR_PTR(irq); 411 412 ret = _msm_mdss_irq_domain_add(msm_mdss); 413 if (ret) 414 return ERR_PTR(ret); 415 416 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 417 msm_mdss); 418 419 pm_runtime_enable(&pdev->dev); 420 421 return msm_mdss; 422 } 423 424 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 425 { 426 struct msm_mdss *mdss = dev_get_drvdata(dev); 427 428 DBG(""); 429 430 return msm_mdss_disable(mdss); 431 } 432 433 static int __maybe_unused mdss_runtime_resume(struct device *dev) 434 { 435 struct msm_mdss *mdss = dev_get_drvdata(dev); 436 437 DBG(""); 438 439 return msm_mdss_enable(mdss); 440 } 441 442 static int __maybe_unused mdss_pm_suspend(struct device *dev) 443 { 444 445 if (pm_runtime_suspended(dev)) 446 return 0; 447 448 return mdss_runtime_suspend(dev); 449 } 450 451 static int __maybe_unused mdss_pm_resume(struct device *dev) 452 { 453 if (pm_runtime_suspended(dev)) 454 return 0; 455 456 return mdss_runtime_resume(dev); 457 } 458 459 static const struct dev_pm_ops mdss_pm_ops = { 460 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 461 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 462 }; 463 464 static int mdss_probe(struct platform_device *pdev) 465 { 466 struct msm_mdss *mdss; 467 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 468 struct device *dev = &pdev->dev; 469 int ret; 470 471 mdss = msm_mdss_init(pdev, is_mdp5); 472 if (IS_ERR(mdss)) 473 return PTR_ERR(mdss); 474 475 mdss->mdss_data = of_device_get_match_data(&pdev->dev); 476 477 platform_set_drvdata(pdev, mdss); 478 479 /* 480 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 481 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 482 * Populate the children devices, find the MDP5/DPU node, and then add 483 * the interfaces to our components list. 484 */ 485 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 486 if (ret) { 487 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 488 msm_mdss_destroy(mdss); 489 return ret; 490 } 491 492 return 0; 493 } 494 495 static int mdss_remove(struct platform_device *pdev) 496 { 497 struct msm_mdss *mdss = platform_get_drvdata(pdev); 498 499 of_platform_depopulate(&pdev->dev); 500 501 msm_mdss_destroy(mdss); 502 503 return 0; 504 } 505 506 static const struct msm_mdss_data sc7180_data = { 507 .ubwc_version = UBWC_2_0, 508 .ubwc_dec_version = UBWC_2_0, 509 .ubwc_static = 0x1e, 510 }; 511 512 static const struct msm_mdss_data sc7280_data = { 513 .ubwc_version = UBWC_3_0, 514 .ubwc_dec_version = UBWC_4_0, 515 .ubwc_swizzle = 6, 516 .ubwc_static = 1, 517 .highest_bank_bit = 1, 518 .macrotile_mode = 1, 519 }; 520 521 static const struct msm_mdss_data sc8180x_data = { 522 .ubwc_version = UBWC_3_0, 523 .ubwc_dec_version = UBWC_3_0, 524 .highest_bank_bit = 3, 525 .macrotile_mode = 1, 526 }; 527 528 static const struct msm_mdss_data sc8280xp_data = { 529 .ubwc_version = UBWC_4_0, 530 .ubwc_dec_version = UBWC_4_0, 531 .ubwc_swizzle = 6, 532 .ubwc_static = 1, 533 .highest_bank_bit = 2, 534 .macrotile_mode = 1, 535 }; 536 537 static const struct msm_mdss_data sdm845_data = { 538 .ubwc_version = UBWC_2_0, 539 .ubwc_dec_version = UBWC_2_0, 540 .highest_bank_bit = 2, 541 }; 542 543 static const struct msm_mdss_data sm6350_data = { 544 .ubwc_version = UBWC_2_0, 545 .ubwc_dec_version = UBWC_2_0, 546 .ubwc_swizzle = 6, 547 .ubwc_static = 0x1e, 548 .highest_bank_bit = 1, 549 }; 550 551 static const struct msm_mdss_data sm8150_data = { 552 .ubwc_version = UBWC_3_0, 553 .ubwc_dec_version = UBWC_3_0, 554 .highest_bank_bit = 2, 555 }; 556 557 static const struct msm_mdss_data sm6115_data = { 558 .ubwc_version = UBWC_1_0, 559 .ubwc_dec_version = UBWC_2_0, 560 .ubwc_swizzle = 7, 561 .ubwc_static = 0x11f, 562 }; 563 564 static const struct msm_mdss_data sm8250_data = { 565 .ubwc_version = UBWC_4_0, 566 .ubwc_dec_version = UBWC_4_0, 567 .ubwc_swizzle = 6, 568 .ubwc_static = 1, 569 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 570 .highest_bank_bit = 3, 571 .macrotile_mode = 1, 572 }; 573 574 static const struct of_device_id mdss_dt_match[] = { 575 { .compatible = "qcom,mdss" }, 576 { .compatible = "qcom,msm8998-mdss" }, 577 { .compatible = "qcom,qcm2290-mdss" }, 578 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, 579 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, 580 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, 581 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, 582 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, 583 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, 584 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, 585 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, 586 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, 587 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, 588 { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, 589 { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data }, 590 { .compatible = "qcom,sm8550-mdss", .data = &sm8250_data }, 591 {} 592 }; 593 MODULE_DEVICE_TABLE(of, mdss_dt_match); 594 595 static struct platform_driver mdss_platform_driver = { 596 .probe = mdss_probe, 597 .remove = mdss_remove, 598 .driver = { 599 .name = "msm-mdss", 600 .of_match_table = mdss_dt_match, 601 .pm = &mdss_pm_ops, 602 }, 603 }; 604 605 void __init msm_mdss_register(void) 606 { 607 platform_driver_register(&mdss_platform_driver); 608 } 609 610 void __exit msm_mdss_unregister(void) 611 { 612 platform_driver_unregister(&mdss_platform_driver); 613 } 614