1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/interconnect.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdesc.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include "msm_mdss.h" 19 #include "msm_kms.h" 20 21 #define HW_REV 0x0 22 #define HW_INTR_STATUS 0x0010 23 24 #define UBWC_DEC_HW_VERSION 0x58 25 #define UBWC_STATIC 0x144 26 #define UBWC_CTRL_2 0x150 27 #define UBWC_PREDICTION_MODE 0x154 28 29 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 30 31 #define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ 32 33 struct msm_mdss { 34 struct device *dev; 35 36 void __iomem *mmio; 37 struct clk_bulk_data *clocks; 38 size_t num_clocks; 39 bool is_mdp5; 40 struct { 41 unsigned long enabled_mask; 42 struct irq_domain *domain; 43 } irq_controller; 44 const struct msm_mdss_data *mdss_data; 45 struct icc_path *mdp_path[2]; 46 u32 num_mdp_paths; 47 struct icc_path *reg_bus_path; 48 }; 49 50 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 51 struct msm_mdss *msm_mdss) 52 { 53 struct icc_path *path0; 54 struct icc_path *path1; 55 struct icc_path *reg_bus_path; 56 57 path0 = devm_of_icc_get(dev, "mdp0-mem"); 58 if (IS_ERR_OR_NULL(path0)) 59 return PTR_ERR_OR_ZERO(path0); 60 61 msm_mdss->mdp_path[0] = path0; 62 msm_mdss->num_mdp_paths = 1; 63 64 path1 = devm_of_icc_get(dev, "mdp1-mem"); 65 if (!IS_ERR_OR_NULL(path1)) { 66 msm_mdss->mdp_path[1] = path1; 67 msm_mdss->num_mdp_paths++; 68 } 69 70 reg_bus_path = of_icc_get(dev, "cpu-cfg"); 71 if (!IS_ERR_OR_NULL(reg_bus_path)) 72 msm_mdss->reg_bus_path = reg_bus_path; 73 74 return 0; 75 } 76 77 static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) 78 { 79 int i; 80 81 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 82 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw)); 83 } 84 85 static void msm_mdss_irq(struct irq_desc *desc) 86 { 87 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 88 struct irq_chip *chip = irq_desc_get_chip(desc); 89 u32 interrupts; 90 91 chained_irq_enter(chip, desc); 92 93 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); 94 95 while (interrupts) { 96 irq_hw_number_t hwirq = fls(interrupts) - 1; 97 int rc; 98 99 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 100 hwirq); 101 if (rc < 0) { 102 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 103 hwirq, rc); 104 break; 105 } 106 107 interrupts &= ~(1 << hwirq); 108 } 109 110 chained_irq_exit(chip, desc); 111 } 112 113 static void msm_mdss_irq_mask(struct irq_data *irqd) 114 { 115 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 116 117 /* memory barrier */ 118 smp_mb__before_atomic(); 119 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 120 /* memory barrier */ 121 smp_mb__after_atomic(); 122 } 123 124 static void msm_mdss_irq_unmask(struct irq_data *irqd) 125 { 126 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 127 128 /* memory barrier */ 129 smp_mb__before_atomic(); 130 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 131 /* memory barrier */ 132 smp_mb__after_atomic(); 133 } 134 135 static struct irq_chip msm_mdss_irq_chip = { 136 .name = "msm_mdss", 137 .irq_mask = msm_mdss_irq_mask, 138 .irq_unmask = msm_mdss_irq_unmask, 139 }; 140 141 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 142 143 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 144 unsigned int irq, irq_hw_number_t hwirq) 145 { 146 struct msm_mdss *msm_mdss = domain->host_data; 147 148 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 149 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 150 151 return irq_set_chip_data(irq, msm_mdss); 152 } 153 154 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 155 .map = msm_mdss_irqdomain_map, 156 .xlate = irq_domain_xlate_onecell, 157 }; 158 159 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 160 { 161 struct device *dev; 162 struct irq_domain *domain; 163 164 dev = msm_mdss->dev; 165 166 domain = irq_domain_add_linear(dev->of_node, 32, 167 &msm_mdss_irqdomain_ops, msm_mdss); 168 if (!domain) { 169 dev_err(dev, "failed to add irq_domain\n"); 170 return -EINVAL; 171 } 172 173 msm_mdss->irq_controller.enabled_mask = 0; 174 msm_mdss->irq_controller.domain = domain; 175 176 return 0; 177 } 178 179 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) 180 { 181 const struct msm_mdss_data *data = msm_mdss->mdss_data; 182 183 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); 184 } 185 186 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) 187 { 188 const struct msm_mdss_data *data = msm_mdss->mdss_data; 189 u32 value = (data->ubwc_swizzle & 0x1) | 190 (data->highest_bank_bit & 0x3) << 4 | 191 (data->macrotile_mode & 0x1) << 12; 192 193 if (data->ubwc_enc_version == UBWC_3_0) 194 value |= BIT(10); 195 196 if (data->ubwc_enc_version == UBWC_1_0) 197 value |= BIT(8); 198 199 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 200 } 201 202 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) 203 { 204 const struct msm_mdss_data *data = msm_mdss->mdss_data; 205 u32 value = (data->ubwc_swizzle & 0x7) | 206 (data->ubwc_static & 0x1) << 3 | 207 (data->highest_bank_bit & 0x7) << 4 | 208 (data->macrotile_mode & 0x1) << 12; 209 210 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 211 212 if (data->ubwc_enc_version == UBWC_3_0) { 213 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); 214 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); 215 } else { 216 if (data->ubwc_dec_version == UBWC_4_3) 217 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); 218 else 219 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); 220 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); 221 } 222 } 223 224 const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) 225 { 226 struct msm_mdss *mdss; 227 228 if (!dev) 229 return ERR_PTR(-EINVAL); 230 231 mdss = dev_get_drvdata(dev); 232 233 return mdss->mdss_data; 234 } 235 236 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 237 { 238 int ret; 239 240 /* 241 * Several components have AXI clocks that can only be turned on if 242 * the interconnect is enabled (non-zero bandwidth). Let's make sure 243 * that the interconnects are at least at a minimum amount. 244 */ 245 msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); 246 247 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) 248 icc_set_bw(msm_mdss->reg_bus_path, 0, 249 msm_mdss->mdss_data->reg_bus_bw); 250 else 251 icc_set_bw(msm_mdss->reg_bus_path, 0, 252 DEFAULT_REG_BW); 253 254 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 255 if (ret) { 256 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 257 return ret; 258 } 259 260 /* 261 * Register access requires MDSS_MDP_CLK, which is not enabled by the 262 * mdss on mdp5 hardware. Skip it for now. 263 */ 264 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) 265 return 0; 266 267 /* 268 * ubwc config is part of the "mdss" region which is not accessible 269 * from the rest of the driver. hardcode known configurations here 270 * 271 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, 272 * UBWC_n and the rest of params comes from hw data. 273 */ 274 switch (msm_mdss->mdss_data->ubwc_dec_version) { 275 case 0: /* no UBWC */ 276 case UBWC_1_0: 277 /* do nothing */ 278 break; 279 case UBWC_2_0: 280 msm_mdss_setup_ubwc_dec_20(msm_mdss); 281 break; 282 case UBWC_3_0: 283 msm_mdss_setup_ubwc_dec_30(msm_mdss); 284 break; 285 case UBWC_4_0: 286 case UBWC_4_3: 287 msm_mdss_setup_ubwc_dec_40(msm_mdss); 288 break; 289 default: 290 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", 291 msm_mdss->mdss_data->ubwc_dec_version); 292 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", 293 readl_relaxed(msm_mdss->mmio + HW_REV)); 294 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 295 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); 296 break; 297 } 298 299 return ret; 300 } 301 302 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 303 { 304 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 305 msm_mdss_icc_request_bw(msm_mdss, 0); 306 307 if (msm_mdss->reg_bus_path) 308 icc_set_bw(msm_mdss->reg_bus_path, 0, 0); 309 310 return 0; 311 } 312 313 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 314 { 315 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 316 int irq; 317 318 pm_runtime_suspend(msm_mdss->dev); 319 pm_runtime_disable(msm_mdss->dev); 320 irq_domain_remove(msm_mdss->irq_controller.domain); 321 msm_mdss->irq_controller.domain = NULL; 322 irq = platform_get_irq(pdev, 0); 323 irq_set_chained_handler_and_data(irq, NULL, NULL); 324 } 325 326 static int msm_mdss_reset(struct device *dev) 327 { 328 struct reset_control *reset; 329 330 reset = reset_control_get_optional_exclusive(dev, NULL); 331 if (!reset) { 332 /* Optional reset not specified */ 333 return 0; 334 } else if (IS_ERR(reset)) { 335 return dev_err_probe(dev, PTR_ERR(reset), 336 "failed to acquire mdss reset\n"); 337 } 338 339 reset_control_assert(reset); 340 /* 341 * Tests indicate that reset has to be held for some period of time, 342 * make it one frame in a typical system 343 */ 344 msleep(20); 345 reset_control_deassert(reset); 346 347 reset_control_put(reset); 348 349 return 0; 350 } 351 352 /* 353 * MDP5 MDSS uses at most three specified clocks. 354 */ 355 #define MDP5_MDSS_NUM_CLOCKS 3 356 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 357 { 358 struct clk_bulk_data *bulk; 359 int num_clocks = 0; 360 int ret; 361 362 if (!pdev) 363 return -EINVAL; 364 365 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 366 if (!bulk) 367 return -ENOMEM; 368 369 bulk[num_clocks++].id = "iface"; 370 bulk[num_clocks++].id = "bus"; 371 bulk[num_clocks++].id = "vsync"; 372 373 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 374 if (ret) 375 return ret; 376 377 *clocks = bulk; 378 379 return num_clocks; 380 } 381 382 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 383 { 384 struct msm_mdss *msm_mdss; 385 int ret; 386 int irq; 387 388 ret = msm_mdss_reset(&pdev->dev); 389 if (ret) 390 return ERR_PTR(ret); 391 392 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 393 if (!msm_mdss) 394 return ERR_PTR(-ENOMEM); 395 396 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); 397 398 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 399 if (IS_ERR(msm_mdss->mmio)) 400 return ERR_CAST(msm_mdss->mmio); 401 402 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 403 404 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 405 if (ret) 406 return ERR_PTR(ret); 407 408 if (is_mdp5) 409 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 410 else 411 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 412 if (ret < 0) { 413 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 414 return ERR_PTR(ret); 415 } 416 msm_mdss->num_clocks = ret; 417 msm_mdss->is_mdp5 = is_mdp5; 418 419 msm_mdss->dev = &pdev->dev; 420 421 irq = platform_get_irq(pdev, 0); 422 if (irq < 0) 423 return ERR_PTR(irq); 424 425 ret = _msm_mdss_irq_domain_add(msm_mdss); 426 if (ret) 427 return ERR_PTR(ret); 428 429 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 430 msm_mdss); 431 432 pm_runtime_enable(&pdev->dev); 433 434 return msm_mdss; 435 } 436 437 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 438 { 439 struct msm_mdss *mdss = dev_get_drvdata(dev); 440 441 DBG(""); 442 443 return msm_mdss_disable(mdss); 444 } 445 446 static int __maybe_unused mdss_runtime_resume(struct device *dev) 447 { 448 struct msm_mdss *mdss = dev_get_drvdata(dev); 449 450 DBG(""); 451 452 return msm_mdss_enable(mdss); 453 } 454 455 static int __maybe_unused mdss_pm_suspend(struct device *dev) 456 { 457 458 if (pm_runtime_suspended(dev)) 459 return 0; 460 461 return mdss_runtime_suspend(dev); 462 } 463 464 static int __maybe_unused mdss_pm_resume(struct device *dev) 465 { 466 if (pm_runtime_suspended(dev)) 467 return 0; 468 469 return mdss_runtime_resume(dev); 470 } 471 472 static const struct dev_pm_ops mdss_pm_ops = { 473 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 474 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 475 }; 476 477 static int mdss_probe(struct platform_device *pdev) 478 { 479 struct msm_mdss *mdss; 480 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 481 struct device *dev = &pdev->dev; 482 int ret; 483 484 mdss = msm_mdss_init(pdev, is_mdp5); 485 if (IS_ERR(mdss)) 486 return PTR_ERR(mdss); 487 488 platform_set_drvdata(pdev, mdss); 489 490 /* 491 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 492 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 493 * Populate the children devices, find the MDP5/DPU node, and then add 494 * the interfaces to our components list. 495 */ 496 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 497 if (ret) { 498 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 499 msm_mdss_destroy(mdss); 500 return ret; 501 } 502 503 return 0; 504 } 505 506 static int mdss_remove(struct platform_device *pdev) 507 { 508 struct msm_mdss *mdss = platform_get_drvdata(pdev); 509 510 of_platform_depopulate(&pdev->dev); 511 512 msm_mdss_destroy(mdss); 513 514 return 0; 515 } 516 517 static const struct msm_mdss_data msm8998_data = { 518 .ubwc_enc_version = UBWC_1_0, 519 .ubwc_dec_version = UBWC_1_0, 520 .highest_bank_bit = 2, 521 .reg_bus_bw = 76800, 522 }; 523 524 static const struct msm_mdss_data qcm2290_data = { 525 /* no UBWC */ 526 .highest_bank_bit = 0x2, 527 .reg_bus_bw = 76800, 528 }; 529 530 static const struct msm_mdss_data sc7180_data = { 531 .ubwc_enc_version = UBWC_2_0, 532 .ubwc_dec_version = UBWC_2_0, 533 .ubwc_static = 0x1e, 534 .highest_bank_bit = 0x1, 535 .reg_bus_bw = 76800, 536 }; 537 538 static const struct msm_mdss_data sc7280_data = { 539 .ubwc_enc_version = UBWC_3_0, 540 .ubwc_dec_version = UBWC_4_0, 541 .ubwc_swizzle = 6, 542 .ubwc_static = 1, 543 .highest_bank_bit = 1, 544 .macrotile_mode = 1, 545 .reg_bus_bw = 74000, 546 }; 547 548 static const struct msm_mdss_data sc8180x_data = { 549 .ubwc_enc_version = UBWC_3_0, 550 .ubwc_dec_version = UBWC_3_0, 551 .highest_bank_bit = 3, 552 .macrotile_mode = 1, 553 .reg_bus_bw = 76800, 554 }; 555 556 static const struct msm_mdss_data sc8280xp_data = { 557 .ubwc_enc_version = UBWC_4_0, 558 .ubwc_dec_version = UBWC_4_0, 559 .ubwc_swizzle = 6, 560 .ubwc_static = 1, 561 .highest_bank_bit = 2, 562 .macrotile_mode = 1, 563 .reg_bus_bw = 76800, 564 }; 565 566 static const struct msm_mdss_data sdm845_data = { 567 .ubwc_enc_version = UBWC_2_0, 568 .ubwc_dec_version = UBWC_2_0, 569 .highest_bank_bit = 2, 570 .reg_bus_bw = 76800, 571 }; 572 573 static const struct msm_mdss_data sm6350_data = { 574 .ubwc_enc_version = UBWC_2_0, 575 .ubwc_dec_version = UBWC_2_0, 576 .ubwc_swizzle = 6, 577 .ubwc_static = 0x1e, 578 .highest_bank_bit = 1, 579 .reg_bus_bw = 76800, 580 }; 581 582 static const struct msm_mdss_data sm8150_data = { 583 .ubwc_enc_version = UBWC_3_0, 584 .ubwc_dec_version = UBWC_3_0, 585 .highest_bank_bit = 2, 586 .reg_bus_bw = 76800, 587 }; 588 589 static const struct msm_mdss_data sm6115_data = { 590 .ubwc_enc_version = UBWC_1_0, 591 .ubwc_dec_version = UBWC_2_0, 592 .ubwc_swizzle = 7, 593 .ubwc_static = 0x11f, 594 .highest_bank_bit = 0x1, 595 .reg_bus_bw = 76800, 596 }; 597 598 static const struct msm_mdss_data sm6125_data = { 599 .ubwc_enc_version = UBWC_1_0, 600 .ubwc_dec_version = UBWC_3_0, 601 .ubwc_swizzle = 1, 602 .highest_bank_bit = 1, 603 .reg_bus_bw = 76800, 604 }; 605 606 static const struct msm_mdss_data sm8250_data = { 607 .ubwc_enc_version = UBWC_4_0, 608 .ubwc_dec_version = UBWC_4_0, 609 .ubwc_swizzle = 6, 610 .ubwc_static = 1, 611 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 612 .highest_bank_bit = 3, 613 .macrotile_mode = 1, 614 .reg_bus_bw = 76800, 615 }; 616 617 static const struct msm_mdss_data sm8350_data = { 618 .ubwc_enc_version = UBWC_4_0, 619 .ubwc_dec_version = UBWC_4_0, 620 .ubwc_swizzle = 6, 621 .ubwc_static = 1, 622 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 623 .highest_bank_bit = 3, 624 .macrotile_mode = 1, 625 .reg_bus_bw = 74000, 626 }; 627 628 static const struct msm_mdss_data sm8550_data = { 629 .ubwc_enc_version = UBWC_4_0, 630 .ubwc_dec_version = UBWC_4_3, 631 .ubwc_swizzle = 6, 632 .ubwc_static = 1, 633 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 634 .highest_bank_bit = 3, 635 .macrotile_mode = 1, 636 .reg_bus_bw = 57000, 637 }; 638 static const struct of_device_id mdss_dt_match[] = { 639 { .compatible = "qcom,mdss" }, 640 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, 641 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, 642 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, 643 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, 644 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, 645 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, 646 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, 647 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, 648 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data }, 649 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, 650 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, 651 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, 652 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, 653 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data }, 654 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, 655 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, 656 {} 657 }; 658 MODULE_DEVICE_TABLE(of, mdss_dt_match); 659 660 static struct platform_driver mdss_platform_driver = { 661 .probe = mdss_probe, 662 .remove = mdss_remove, 663 .driver = { 664 .name = "msm-mdss", 665 .of_match_table = mdss_dt_match, 666 .pm = &mdss_pm_ops, 667 }, 668 }; 669 670 void __init msm_mdss_register(void) 671 { 672 platform_driver_register(&mdss_platform_driver); 673 } 674 675 void __exit msm_mdss_unregister(void) 676 { 677 platform_driver_unregister(&mdss_platform_driver); 678 } 679