1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/adreno-smmu-priv.h> 8 #include <linux/io-pgtable.h> 9 #include "msm_drv.h" 10 #include "msm_mmu.h" 11 12 struct msm_iommu { 13 struct msm_mmu base; 14 struct iommu_domain *domain; 15 atomic_t pagetables; 16 }; 17 18 #define to_msm_iommu(x) container_of(x, struct msm_iommu, base) 19 20 struct msm_iommu_pagetable { 21 struct msm_mmu base; 22 struct msm_mmu *parent; 23 struct io_pgtable_ops *pgtbl_ops; 24 unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */ 25 phys_addr_t ttbr; 26 u32 asid; 27 }; 28 static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu) 29 { 30 return container_of(mmu, struct msm_iommu_pagetable, base); 31 } 32 33 /* based on iommu_pgsize() in iommu.c: */ 34 static size_t calc_pgsize(struct msm_iommu_pagetable *pagetable, 35 unsigned long iova, phys_addr_t paddr, 36 size_t size, size_t *count) 37 { 38 unsigned int pgsize_idx, pgsize_idx_next; 39 unsigned long pgsizes; 40 size_t offset, pgsize, pgsize_next; 41 unsigned long addr_merge = paddr | iova; 42 43 /* Page sizes supported by the hardware and small enough for @size */ 44 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); 45 46 /* Constrain the page sizes further based on the maximum alignment */ 47 if (likely(addr_merge)) 48 pgsizes &= GENMASK(__ffs(addr_merge), 0); 49 50 /* Make sure we have at least one suitable page size */ 51 BUG_ON(!pgsizes); 52 53 /* Pick the biggest page size remaining */ 54 pgsize_idx = __fls(pgsizes); 55 pgsize = BIT(pgsize_idx); 56 if (!count) 57 return pgsize; 58 59 /* Find the next biggest support page size, if it exists */ 60 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); 61 if (!pgsizes) 62 goto out_set_count; 63 64 pgsize_idx_next = __ffs(pgsizes); 65 pgsize_next = BIT(pgsize_idx_next); 66 67 /* 68 * There's no point trying a bigger page size unless the virtual 69 * and physical addresses are similarly offset within the larger page. 70 */ 71 if ((iova ^ paddr) & (pgsize_next - 1)) 72 goto out_set_count; 73 74 /* Calculate the offset to the next page size alignment boundary */ 75 offset = pgsize_next - (addr_merge & (pgsize_next - 1)); 76 77 /* 78 * If size is big enough to accommodate the larger page, reduce 79 * the number of smaller pages. 80 */ 81 if (offset + pgsize_next <= size) 82 size = offset; 83 84 out_set_count: 85 *count = size >> pgsize_idx; 86 return pgsize; 87 } 88 89 static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, 90 size_t size) 91 { 92 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); 93 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; 94 95 while (size) { 96 size_t unmapped, pgsize, count; 97 98 pgsize = calc_pgsize(pagetable, iova, iova, size, &count); 99 100 unmapped = ops->unmap_pages(ops, iova, pgsize, count, NULL); 101 if (!unmapped) 102 break; 103 104 iova += unmapped; 105 size -= unmapped; 106 } 107 108 iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain); 109 110 return (size == 0) ? 0 : -EINVAL; 111 } 112 113 static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova, 114 struct sg_table *sgt, size_t len, int prot) 115 { 116 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); 117 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; 118 struct scatterlist *sg; 119 u64 addr = iova; 120 unsigned int i; 121 122 for_each_sgtable_sg(sgt, sg, i) { 123 size_t size = sg->length; 124 phys_addr_t phys = sg_phys(sg); 125 126 while (size) { 127 size_t pgsize, count, mapped = 0; 128 int ret; 129 130 pgsize = calc_pgsize(pagetable, addr, phys, size, &count); 131 132 ret = ops->map_pages(ops, addr, phys, pgsize, count, 133 prot, GFP_KERNEL, &mapped); 134 135 /* map_pages could fail after mapping some of the pages, 136 * so update the counters before error handling. 137 */ 138 phys += mapped; 139 addr += mapped; 140 size -= mapped; 141 142 if (ret) { 143 msm_iommu_pagetable_unmap(mmu, iova, addr - iova); 144 return -EINVAL; 145 } 146 } 147 } 148 149 return 0; 150 } 151 152 static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu) 153 { 154 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); 155 struct msm_iommu *iommu = to_msm_iommu(pagetable->parent); 156 struct adreno_smmu_priv *adreno_smmu = 157 dev_get_drvdata(pagetable->parent->dev); 158 159 /* 160 * If this is the last attached pagetable for the parent, 161 * disable TTBR0 in the arm-smmu driver 162 */ 163 if (atomic_dec_return(&iommu->pagetables) == 0) 164 adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL); 165 166 free_io_pgtable_ops(pagetable->pgtbl_ops); 167 kfree(pagetable); 168 } 169 170 int msm_iommu_pagetable_params(struct msm_mmu *mmu, 171 phys_addr_t *ttbr, int *asid) 172 { 173 struct msm_iommu_pagetable *pagetable; 174 175 if (mmu->type != MSM_MMU_IOMMU_PAGETABLE) 176 return -EINVAL; 177 178 pagetable = to_pagetable(mmu); 179 180 if (ttbr) 181 *ttbr = pagetable->ttbr; 182 183 if (asid) 184 *asid = pagetable->asid; 185 186 return 0; 187 } 188 189 static const struct msm_mmu_funcs pagetable_funcs = { 190 .map = msm_iommu_pagetable_map, 191 .unmap = msm_iommu_pagetable_unmap, 192 .destroy = msm_iommu_pagetable_destroy, 193 }; 194 195 static void msm_iommu_tlb_flush_all(void *cookie) 196 { 197 } 198 199 static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size, 200 size_t granule, void *cookie) 201 { 202 } 203 204 static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather, 205 unsigned long iova, size_t granule, void *cookie) 206 { 207 } 208 209 static const struct iommu_flush_ops null_tlb_ops = { 210 .tlb_flush_all = msm_iommu_tlb_flush_all, 211 .tlb_flush_walk = msm_iommu_tlb_flush_walk, 212 .tlb_add_page = msm_iommu_tlb_add_page, 213 }; 214 215 static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, 216 unsigned long iova, int flags, void *arg); 217 218 struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) 219 { 220 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); 221 struct msm_iommu *iommu = to_msm_iommu(parent); 222 struct msm_iommu_pagetable *pagetable; 223 const struct io_pgtable_cfg *ttbr1_cfg = NULL; 224 struct io_pgtable_cfg ttbr0_cfg; 225 int ret; 226 227 /* Get the pagetable configuration from the domain */ 228 if (adreno_smmu->cookie) 229 ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie); 230 if (!ttbr1_cfg) 231 return ERR_PTR(-ENODEV); 232 233 /* 234 * Defer setting the fault handler until we have a valid adreno_smmu 235 * to avoid accidentially installing a GPU specific fault handler for 236 * the display's iommu 237 */ 238 iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); 239 240 pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); 241 if (!pagetable) 242 return ERR_PTR(-ENOMEM); 243 244 msm_mmu_init(&pagetable->base, parent->dev, &pagetable_funcs, 245 MSM_MMU_IOMMU_PAGETABLE); 246 247 /* Clone the TTBR1 cfg as starting point for TTBR0 cfg: */ 248 ttbr0_cfg = *ttbr1_cfg; 249 250 /* The incoming cfg will have the TTBR1 quirk enabled */ 251 ttbr0_cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1; 252 ttbr0_cfg.tlb = &null_tlb_ops; 253 254 pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1, 255 &ttbr0_cfg, iommu->domain); 256 257 if (!pagetable->pgtbl_ops) { 258 kfree(pagetable); 259 return ERR_PTR(-ENOMEM); 260 } 261 262 /* 263 * If this is the first pagetable that we've allocated, send it back to 264 * the arm-smmu driver as a trigger to set up TTBR0 265 */ 266 if (atomic_inc_return(&iommu->pagetables) == 1) { 267 /* Enable stall on iommu fault: */ 268 adreno_smmu->set_stall(adreno_smmu->cookie, true); 269 270 ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg); 271 if (ret) { 272 free_io_pgtable_ops(pagetable->pgtbl_ops); 273 kfree(pagetable); 274 return ERR_PTR(ret); 275 } 276 } 277 278 /* Needed later for TLB flush */ 279 pagetable->parent = parent; 280 pagetable->pgsize_bitmap = ttbr0_cfg.pgsize_bitmap; 281 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; 282 283 /* 284 * TODO we would like each set of page tables to have a unique ASID 285 * to optimize TLB invalidation. But iommu_flush_iotlb_all() will 286 * end up flushing the ASID used for TTBR1 pagetables, which is not 287 * what we want. So for now just use the same ASID as TTBR1. 288 */ 289 pagetable->asid = 0; 290 291 return &pagetable->base; 292 } 293 294 static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, 295 unsigned long iova, int flags, void *arg) 296 { 297 struct msm_iommu *iommu = arg; 298 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev); 299 struct adreno_smmu_fault_info info, *ptr = NULL; 300 301 if (adreno_smmu->get_fault_info) { 302 adreno_smmu->get_fault_info(adreno_smmu->cookie, &info); 303 ptr = &info; 304 } 305 306 if (iommu->base.handler) 307 return iommu->base.handler(iommu->base.arg, iova, flags, ptr); 308 309 pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); 310 return 0; 311 } 312 313 static void msm_iommu_resume_translation(struct msm_mmu *mmu) 314 { 315 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev); 316 317 adreno_smmu->resume_translation(adreno_smmu->cookie, true); 318 } 319 320 static void msm_iommu_detach(struct msm_mmu *mmu) 321 { 322 struct msm_iommu *iommu = to_msm_iommu(mmu); 323 324 iommu_detach_device(iommu->domain, mmu->dev); 325 } 326 327 static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, 328 struct sg_table *sgt, size_t len, int prot) 329 { 330 struct msm_iommu *iommu = to_msm_iommu(mmu); 331 size_t ret; 332 333 /* The arm-smmu driver expects the addresses to be sign extended */ 334 if (iova & BIT_ULL(48)) 335 iova |= GENMASK_ULL(63, 49); 336 337 ret = iommu_map_sgtable(iommu->domain, iova, sgt, prot); 338 WARN_ON(!ret); 339 340 return (ret == len) ? 0 : -EINVAL; 341 } 342 343 static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) 344 { 345 struct msm_iommu *iommu = to_msm_iommu(mmu); 346 347 if (iova & BIT_ULL(48)) 348 iova |= GENMASK_ULL(63, 49); 349 350 iommu_unmap(iommu->domain, iova, len); 351 352 return 0; 353 } 354 355 static void msm_iommu_destroy(struct msm_mmu *mmu) 356 { 357 struct msm_iommu *iommu = to_msm_iommu(mmu); 358 iommu_domain_free(iommu->domain); 359 kfree(iommu); 360 } 361 362 static const struct msm_mmu_funcs funcs = { 363 .detach = msm_iommu_detach, 364 .map = msm_iommu_map, 365 .unmap = msm_iommu_unmap, 366 .destroy = msm_iommu_destroy, 367 .resume_translation = msm_iommu_resume_translation, 368 }; 369 370 struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) 371 { 372 struct msm_iommu *iommu; 373 int ret; 374 375 if (!domain) 376 return ERR_PTR(-ENODEV); 377 378 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); 379 if (!iommu) 380 return ERR_PTR(-ENOMEM); 381 382 iommu->domain = domain; 383 msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); 384 385 atomic_set(&iommu->pagetables, 0); 386 387 ret = iommu_attach_device(iommu->domain, dev); 388 if (ret) { 389 kfree(iommu); 390 return ERR_PTR(ret); 391 } 392 393 return &iommu->base; 394 } 395