1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_GPU_H__ 19 #define __MSM_GPU_H__ 20 21 #include <linux/clk.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "msm_drv.h" 25 #include "msm_fence.h" 26 #include "msm_ringbuffer.h" 27 28 struct msm_gem_submit; 29 struct msm_gpu_perfcntr; 30 31 struct msm_gpu_config { 32 const char *ioname; 33 const char *irqname; 34 uint64_t va_start; 35 uint64_t va_end; 36 unsigned int nr_rings; 37 }; 38 39 /* So far, with hardware that I've seen to date, we can have: 40 * + zero, one, or two z180 2d cores 41 * + a3xx or a2xx 3d core, which share a common CP (the firmware 42 * for the CP seems to implement some different PM4 packet types 43 * but the basics of cmdstream submission are the same) 44 * 45 * Which means that the eventual complete "class" hierarchy, once 46 * support for all past and present hw is in place, becomes: 47 * + msm_gpu 48 * + adreno_gpu 49 * + a3xx_gpu 50 * + a2xx_gpu 51 * + z180_gpu 52 */ 53 struct msm_gpu_funcs { 54 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 55 int (*hw_init)(struct msm_gpu *gpu); 56 int (*pm_suspend)(struct msm_gpu *gpu); 57 int (*pm_resume)(struct msm_gpu *gpu); 58 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, 59 struct msm_file_private *ctx); 60 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 61 irqreturn_t (*irq)(struct msm_gpu *irq); 62 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); 63 void (*recover)(struct msm_gpu *gpu); 64 void (*destroy)(struct msm_gpu *gpu); 65 #ifdef CONFIG_DEBUG_FS 66 /* show GPU status in debugfs: */ 67 void (*show)(struct msm_gpu *gpu, struct seq_file *m); 68 #endif 69 }; 70 71 struct msm_gpu { 72 const char *name; 73 struct drm_device *dev; 74 struct platform_device *pdev; 75 const struct msm_gpu_funcs *funcs; 76 77 /* performance counters (hw & sw): */ 78 spinlock_t perf_lock; 79 bool perfcntr_active; 80 struct { 81 bool active; 82 ktime_t time; 83 } last_sample; 84 uint32_t totaltime, activetime; /* sw counters */ 85 uint32_t last_cntrs[5]; /* hw counters */ 86 const struct msm_gpu_perfcntr *perfcntrs; 87 uint32_t num_perfcntrs; 88 89 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; 90 int nr_rings; 91 92 /* list of GEM active objects: */ 93 struct list_head active_list; 94 95 /* does gpu need hw_init? */ 96 bool needs_hw_init; 97 98 /* worker for handling active-list retiring: */ 99 struct work_struct retire_work; 100 101 void __iomem *mmio; 102 int irq; 103 104 struct msm_gem_address_space *aspace; 105 106 /* Power Control: */ 107 struct regulator *gpu_reg, *gpu_cx; 108 struct clk **grp_clks; 109 int nr_clocks; 110 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; 111 uint32_t fast_rate, bus_freq; 112 113 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 114 struct msm_bus_scale_pdata *bus_scale_table; 115 uint32_t bsc; 116 #endif 117 118 /* Hang and Inactivity Detection: 119 */ 120 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ 121 122 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ 123 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) 124 struct timer_list hangcheck_timer; 125 struct work_struct recover_work; 126 127 struct drm_gem_object *memptrs_bo; 128 }; 129 130 /* It turns out that all targets use the same ringbuffer size */ 131 #define MSM_GPU_RINGBUFFER_SZ SZ_32K 132 #define MSM_GPU_RINGBUFFER_BLKSIZE 32 133 134 #define MSM_GPU_RB_CNTL_DEFAULT \ 135 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \ 136 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8))) 137 138 static inline bool msm_gpu_active(struct msm_gpu *gpu) 139 { 140 int i; 141 142 for (i = 0; i < gpu->nr_rings; i++) { 143 struct msm_ringbuffer *ring = gpu->rb[i]; 144 145 if (ring->seqno > ring->memptrs->fence) 146 return true; 147 } 148 149 return false; 150 } 151 152 /* Perf-Counters: 153 * The select_reg and select_val are just there for the benefit of the child 154 * class that actually enables the perf counter.. but msm_gpu base class 155 * will handle sampling/displaying the counters. 156 */ 157 158 struct msm_gpu_perfcntr { 159 uint32_t select_reg; 160 uint32_t sample_reg; 161 uint32_t select_val; 162 const char *name; 163 }; 164 165 struct msm_gpu_submitqueue { 166 int id; 167 u32 flags; 168 u32 prio; 169 int faults; 170 struct list_head node; 171 struct kref ref; 172 }; 173 174 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) 175 { 176 msm_writel(data, gpu->mmio + (reg << 2)); 177 } 178 179 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) 180 { 181 return msm_readl(gpu->mmio + (reg << 2)); 182 } 183 184 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) 185 { 186 uint32_t val = gpu_read(gpu, reg); 187 188 val &= ~mask; 189 gpu_write(gpu, reg, val | or); 190 } 191 192 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) 193 { 194 u64 val; 195 196 /* 197 * Why not a readq here? Two reasons: 1) many of the LO registers are 198 * not quad word aligned and 2) the GPU hardware designers have a bit 199 * of a history of putting registers where they fit, especially in 200 * spins. The longer a GPU family goes the higher the chance that 201 * we'll get burned. We could do a series of validity checks if we 202 * wanted to, but really is a readq() that much better? Nah. 203 */ 204 205 /* 206 * For some lo/hi registers (like perfcounters), the hi value is latched 207 * when the lo is read, so make sure to read the lo first to trigger 208 * that 209 */ 210 val = (u64) msm_readl(gpu->mmio + (lo << 2)); 211 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); 212 213 return val; 214 } 215 216 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) 217 { 218 /* Why not a writeq here? Read the screed above */ 219 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); 220 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); 221 } 222 223 int msm_gpu_pm_suspend(struct msm_gpu *gpu); 224 int msm_gpu_pm_resume(struct msm_gpu *gpu); 225 226 int msm_gpu_hw_init(struct msm_gpu *gpu); 227 228 void msm_gpu_perfcntr_start(struct msm_gpu *gpu); 229 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); 230 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 231 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); 232 233 void msm_gpu_retire(struct msm_gpu *gpu); 234 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 235 struct msm_file_private *ctx); 236 237 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 238 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 239 const char *name, struct msm_gpu_config *config); 240 241 void msm_gpu_cleanup(struct msm_gpu *gpu); 242 243 struct msm_gpu *adreno_load_gpu(struct drm_device *dev); 244 void __init adreno_register(void); 245 void __exit adreno_unregister(void); 246 247 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) 248 { 249 if (queue) 250 kref_put(&queue->ref, msm_submitqueue_destroy); 251 } 252 253 #endif /* __MSM_GPU_H__ */ 254