1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_GPU_H__ 19 #define __MSM_GPU_H__ 20 21 #include <linux/clk.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "msm_drv.h" 25 #include "msm_fence.h" 26 #include "msm_ringbuffer.h" 27 28 struct msm_gem_submit; 29 struct msm_gpu_perfcntr; 30 struct msm_gpu_state; 31 32 struct msm_gpu_config { 33 const char *ioname; 34 uint64_t va_start; 35 uint64_t va_end; 36 unsigned int nr_rings; 37 }; 38 39 /* So far, with hardware that I've seen to date, we can have: 40 * + zero, one, or two z180 2d cores 41 * + a3xx or a2xx 3d core, which share a common CP (the firmware 42 * for the CP seems to implement some different PM4 packet types 43 * but the basics of cmdstream submission are the same) 44 * 45 * Which means that the eventual complete "class" hierarchy, once 46 * support for all past and present hw is in place, becomes: 47 * + msm_gpu 48 * + adreno_gpu 49 * + a3xx_gpu 50 * + a2xx_gpu 51 * + z180_gpu 52 */ 53 struct msm_gpu_funcs { 54 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 55 int (*hw_init)(struct msm_gpu *gpu); 56 int (*pm_suspend)(struct msm_gpu *gpu); 57 int (*pm_resume)(struct msm_gpu *gpu); 58 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, 59 struct msm_file_private *ctx); 60 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 61 irqreturn_t (*irq)(struct msm_gpu *irq); 62 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); 63 void (*recover)(struct msm_gpu *gpu); 64 void (*destroy)(struct msm_gpu *gpu); 65 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 66 /* show GPU status in debugfs: */ 67 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state, 68 struct drm_printer *p); 69 /* for generation specific debugfs: */ 70 int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor); 71 #endif 72 unsigned long (*gpu_busy)(struct msm_gpu *gpu); 73 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); 74 int (*gpu_state_put)(struct msm_gpu_state *state); 75 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); 76 void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); 77 }; 78 79 struct msm_gpu { 80 const char *name; 81 struct drm_device *dev; 82 struct platform_device *pdev; 83 const struct msm_gpu_funcs *funcs; 84 85 /* performance counters (hw & sw): */ 86 spinlock_t perf_lock; 87 bool perfcntr_active; 88 struct { 89 bool active; 90 ktime_t time; 91 } last_sample; 92 uint32_t totaltime, activetime; /* sw counters */ 93 uint32_t last_cntrs[5]; /* hw counters */ 94 const struct msm_gpu_perfcntr *perfcntrs; 95 uint32_t num_perfcntrs; 96 97 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; 98 int nr_rings; 99 100 /* list of GEM active objects: */ 101 struct list_head active_list; 102 103 /* does gpu need hw_init? */ 104 bool needs_hw_init; 105 106 /* worker for handling active-list retiring: */ 107 struct work_struct retire_work; 108 109 void __iomem *mmio; 110 int irq; 111 112 struct msm_gem_address_space *aspace; 113 114 /* Power Control: */ 115 struct regulator *gpu_reg, *gpu_cx; 116 struct clk_bulk_data *grp_clks; 117 int nr_clocks; 118 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; 119 uint32_t fast_rate; 120 121 /* Hang and Inactivity Detection: 122 */ 123 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ 124 125 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ 126 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) 127 struct timer_list hangcheck_timer; 128 struct work_struct recover_work; 129 130 struct drm_gem_object *memptrs_bo; 131 132 struct { 133 struct devfreq *devfreq; 134 u64 busy_cycles; 135 ktime_t time; 136 } devfreq; 137 138 struct msm_gpu_state *crashstate; 139 }; 140 141 /* It turns out that all targets use the same ringbuffer size */ 142 #define MSM_GPU_RINGBUFFER_SZ SZ_32K 143 #define MSM_GPU_RINGBUFFER_BLKSIZE 32 144 145 #define MSM_GPU_RB_CNTL_DEFAULT \ 146 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \ 147 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8))) 148 149 static inline bool msm_gpu_active(struct msm_gpu *gpu) 150 { 151 int i; 152 153 for (i = 0; i < gpu->nr_rings; i++) { 154 struct msm_ringbuffer *ring = gpu->rb[i]; 155 156 if (ring->seqno > ring->memptrs->fence) 157 return true; 158 } 159 160 return false; 161 } 162 163 /* Perf-Counters: 164 * The select_reg and select_val are just there for the benefit of the child 165 * class that actually enables the perf counter.. but msm_gpu base class 166 * will handle sampling/displaying the counters. 167 */ 168 169 struct msm_gpu_perfcntr { 170 uint32_t select_reg; 171 uint32_t sample_reg; 172 uint32_t select_val; 173 const char *name; 174 }; 175 176 struct msm_gpu_submitqueue { 177 int id; 178 u32 flags; 179 u32 prio; 180 int faults; 181 struct list_head node; 182 struct kref ref; 183 }; 184 185 struct msm_gpu_state_bo { 186 u64 iova; 187 size_t size; 188 void *data; 189 bool encoded; 190 }; 191 192 struct msm_gpu_state { 193 struct kref ref; 194 struct timespec64 time; 195 196 struct { 197 u64 iova; 198 u32 fence; 199 u32 seqno; 200 u32 rptr; 201 u32 wptr; 202 void *data; 203 int data_size; 204 bool encoded; 205 } ring[MSM_GPU_MAX_RINGS]; 206 207 int nr_registers; 208 u32 *registers; 209 210 u32 rbbm_status; 211 212 char *comm; 213 char *cmd; 214 215 int nr_bos; 216 struct msm_gpu_state_bo *bos; 217 }; 218 219 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) 220 { 221 msm_writel(data, gpu->mmio + (reg << 2)); 222 } 223 224 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) 225 { 226 return msm_readl(gpu->mmio + (reg << 2)); 227 } 228 229 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) 230 { 231 uint32_t val = gpu_read(gpu, reg); 232 233 val &= ~mask; 234 gpu_write(gpu, reg, val | or); 235 } 236 237 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) 238 { 239 u64 val; 240 241 /* 242 * Why not a readq here? Two reasons: 1) many of the LO registers are 243 * not quad word aligned and 2) the GPU hardware designers have a bit 244 * of a history of putting registers where they fit, especially in 245 * spins. The longer a GPU family goes the higher the chance that 246 * we'll get burned. We could do a series of validity checks if we 247 * wanted to, but really is a readq() that much better? Nah. 248 */ 249 250 /* 251 * For some lo/hi registers (like perfcounters), the hi value is latched 252 * when the lo is read, so make sure to read the lo first to trigger 253 * that 254 */ 255 val = (u64) msm_readl(gpu->mmio + (lo << 2)); 256 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); 257 258 return val; 259 } 260 261 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) 262 { 263 /* Why not a writeq here? Read the screed above */ 264 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); 265 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); 266 } 267 268 int msm_gpu_pm_suspend(struct msm_gpu *gpu); 269 int msm_gpu_pm_resume(struct msm_gpu *gpu); 270 void msm_gpu_resume_devfreq(struct msm_gpu *gpu); 271 272 int msm_gpu_hw_init(struct msm_gpu *gpu); 273 274 void msm_gpu_perfcntr_start(struct msm_gpu *gpu); 275 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); 276 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 277 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); 278 279 void msm_gpu_retire(struct msm_gpu *gpu); 280 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 281 struct msm_file_private *ctx); 282 283 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 284 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 285 const char *name, struct msm_gpu_config *config); 286 287 void msm_gpu_cleanup(struct msm_gpu *gpu); 288 289 struct msm_gpu *adreno_load_gpu(struct drm_device *dev); 290 void __init adreno_register(void); 291 void __exit adreno_unregister(void); 292 293 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) 294 { 295 if (queue) 296 kref_put(&queue->ref, msm_submitqueue_destroy); 297 } 298 299 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu) 300 { 301 struct msm_gpu_state *state = NULL; 302 303 mutex_lock(&gpu->dev->struct_mutex); 304 305 if (gpu->crashstate) { 306 kref_get(&gpu->crashstate->ref); 307 state = gpu->crashstate; 308 } 309 310 mutex_unlock(&gpu->dev->struct_mutex); 311 312 return state; 313 } 314 315 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) 316 { 317 mutex_lock(&gpu->dev->struct_mutex); 318 319 if (gpu->crashstate) { 320 if (gpu->funcs->gpu_state_put(gpu->crashstate)) 321 gpu->crashstate = NULL; 322 } 323 324 mutex_unlock(&gpu->dev->struct_mutex); 325 } 326 327 #endif /* __MSM_GPU_H__ */ 328