1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_GPU_H__ 19 #define __MSM_GPU_H__ 20 21 #include <linux/clk.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "msm_drv.h" 25 #include "msm_ringbuffer.h" 26 27 struct msm_gem_submit; 28 29 /* So far, with hardware that I've seen to date, we can have: 30 * + zero, one, or two z180 2d cores 31 * + a3xx or a2xx 3d core, which share a common CP (the firmware 32 * for the CP seems to implement some different PM4 packet types 33 * but the basics of cmdstream submission are the same) 34 * 35 * Which means that the eventual complete "class" hierarchy, once 36 * support for all past and present hw is in place, becomes: 37 * + msm_gpu 38 * + adreno_gpu 39 * + a3xx_gpu 40 * + a2xx_gpu 41 * + z180_gpu 42 */ 43 struct msm_gpu_funcs { 44 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 45 int (*hw_init)(struct msm_gpu *gpu); 46 int (*pm_suspend)(struct msm_gpu *gpu); 47 int (*pm_resume)(struct msm_gpu *gpu); 48 int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, 49 struct msm_file_private *ctx); 50 void (*flush)(struct msm_gpu *gpu); 51 void (*idle)(struct msm_gpu *gpu); 52 irqreturn_t (*irq)(struct msm_gpu *irq); 53 uint32_t (*last_fence)(struct msm_gpu *gpu); 54 void (*recover)(struct msm_gpu *gpu); 55 void (*destroy)(struct msm_gpu *gpu); 56 #ifdef CONFIG_DEBUG_FS 57 /* show GPU status in debugfs: */ 58 void (*show)(struct msm_gpu *gpu, struct seq_file *m); 59 #endif 60 }; 61 62 struct msm_gpu { 63 const char *name; 64 struct drm_device *dev; 65 const struct msm_gpu_funcs *funcs; 66 67 struct msm_ringbuffer *rb; 68 uint32_t rb_iova; 69 70 /* list of GEM active objects: */ 71 struct list_head active_list; 72 73 uint32_t submitted_fence; 74 75 /* worker for handling active-list retiring: */ 76 struct work_struct retire_work; 77 78 void __iomem *mmio; 79 int irq; 80 81 struct iommu_domain *iommu; 82 int id; 83 84 /* Power Control: */ 85 struct regulator *gpu_reg, *gpu_cx; 86 struct clk *ebi1_clk, *grp_clks[5]; 87 uint32_t fast_rate, slow_rate, bus_freq; 88 uint32_t bsc; 89 90 /* Hang Detction: */ 91 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ 92 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) 93 struct timer_list hangcheck_timer; 94 uint32_t hangcheck_fence; 95 struct work_struct recover_work; 96 }; 97 98 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) 99 { 100 msm_writel(data, gpu->mmio + (reg << 2)); 101 } 102 103 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) 104 { 105 return msm_readl(gpu->mmio + (reg << 2)); 106 } 107 108 int msm_gpu_pm_suspend(struct msm_gpu *gpu); 109 int msm_gpu_pm_resume(struct msm_gpu *gpu); 110 111 void msm_gpu_retire(struct msm_gpu *gpu); 112 int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 113 struct msm_file_private *ctx); 114 115 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 116 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 117 const char *name, const char *ioname, const char *irqname, int ringsz); 118 void msm_gpu_cleanup(struct msm_gpu *gpu); 119 120 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 121 void __init a3xx_register(void); 122 void __exit a3xx_unregister(void); 123 124 #endif /* __MSM_GPU_H__ */ 125