1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #ifndef __MSM_GPU_H__ 8 #define __MSM_GPU_H__ 9 10 #include <linux/adreno-smmu-priv.h> 11 #include <linux/clk.h> 12 #include <linux/interconnect.h> 13 #include <linux/pm_opp.h> 14 #include <linux/regulator/consumer.h> 15 16 #include "msm_drv.h" 17 #include "msm_fence.h" 18 #include "msm_ringbuffer.h" 19 #include "msm_gem.h" 20 21 struct msm_gem_submit; 22 struct msm_gpu_perfcntr; 23 struct msm_gpu_state; 24 25 struct msm_gpu_config { 26 const char *ioname; 27 unsigned int nr_rings; 28 }; 29 30 /* So far, with hardware that I've seen to date, we can have: 31 * + zero, one, or two z180 2d cores 32 * + a3xx or a2xx 3d core, which share a common CP (the firmware 33 * for the CP seems to implement some different PM4 packet types 34 * but the basics of cmdstream submission are the same) 35 * 36 * Which means that the eventual complete "class" hierarchy, once 37 * support for all past and present hw is in place, becomes: 38 * + msm_gpu 39 * + adreno_gpu 40 * + a3xx_gpu 41 * + a2xx_gpu 42 * + z180_gpu 43 */ 44 struct msm_gpu_funcs { 45 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 46 int (*hw_init)(struct msm_gpu *gpu); 47 int (*pm_suspend)(struct msm_gpu *gpu); 48 int (*pm_resume)(struct msm_gpu *gpu); 49 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit); 50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 51 irqreturn_t (*irq)(struct msm_gpu *irq); 52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); 53 void (*recover)(struct msm_gpu *gpu); 54 void (*destroy)(struct msm_gpu *gpu); 55 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 56 /* show GPU status in debugfs: */ 57 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state, 58 struct drm_printer *p); 59 /* for generation specific debugfs: */ 60 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor); 61 #endif 62 unsigned long (*gpu_busy)(struct msm_gpu *gpu); 63 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); 64 int (*gpu_state_put)(struct msm_gpu_state *state); 65 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); 66 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp); 67 struct msm_gem_address_space *(*create_address_space) 68 (struct msm_gpu *gpu, struct platform_device *pdev); 69 struct msm_gem_address_space *(*create_private_address_space) 70 (struct msm_gpu *gpu); 71 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 72 }; 73 74 struct msm_gpu { 75 const char *name; 76 struct drm_device *dev; 77 struct platform_device *pdev; 78 const struct msm_gpu_funcs *funcs; 79 80 struct adreno_smmu_priv adreno_smmu; 81 82 /* performance counters (hw & sw): */ 83 spinlock_t perf_lock; 84 bool perfcntr_active; 85 struct { 86 bool active; 87 ktime_t time; 88 } last_sample; 89 uint32_t totaltime, activetime; /* sw counters */ 90 uint32_t last_cntrs[5]; /* hw counters */ 91 const struct msm_gpu_perfcntr *perfcntrs; 92 uint32_t num_perfcntrs; 93 94 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; 95 int nr_rings; 96 97 /* list of GEM active objects: */ 98 struct list_head active_list; 99 100 /* does gpu need hw_init? */ 101 bool needs_hw_init; 102 103 /* number of GPU hangs (for all contexts) */ 104 int global_faults; 105 106 /* worker for handling active-list retiring: */ 107 struct work_struct retire_work; 108 109 void __iomem *mmio; 110 int irq; 111 112 struct msm_gem_address_space *aspace; 113 114 /* Power Control: */ 115 struct regulator *gpu_reg, *gpu_cx; 116 struct clk_bulk_data *grp_clks; 117 int nr_clocks; 118 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; 119 uint32_t fast_rate; 120 121 /* The gfx-mem interconnect path that's used by all GPU types. */ 122 struct icc_path *icc_path; 123 124 /* 125 * Second interconnect path for some A3xx and all A4xx GPUs to the 126 * On Chip MEMory (OCMEM). 127 */ 128 struct icc_path *ocmem_icc_path; 129 130 /* Hang and Inactivity Detection: 131 */ 132 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ 133 134 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ 135 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) 136 struct timer_list hangcheck_timer; 137 struct work_struct recover_work; 138 139 struct drm_gem_object *memptrs_bo; 140 141 struct { 142 struct devfreq *devfreq; 143 u64 busy_cycles; 144 ktime_t time; 145 } devfreq; 146 147 struct msm_gpu_state *crashstate; 148 /* True if the hardware supports expanded apriv (a650 and newer) */ 149 bool hw_apriv; 150 }; 151 152 static inline struct msm_gpu *dev_to_gpu(struct device *dev) 153 { 154 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev); 155 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu); 156 } 157 158 /* It turns out that all targets use the same ringbuffer size */ 159 #define MSM_GPU_RINGBUFFER_SZ SZ_32K 160 #define MSM_GPU_RINGBUFFER_BLKSIZE 32 161 162 #define MSM_GPU_RB_CNTL_DEFAULT \ 163 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \ 164 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8))) 165 166 static inline bool msm_gpu_active(struct msm_gpu *gpu) 167 { 168 int i; 169 170 for (i = 0; i < gpu->nr_rings; i++) { 171 struct msm_ringbuffer *ring = gpu->rb[i]; 172 173 if (ring->seqno > ring->memptrs->fence) 174 return true; 175 } 176 177 return false; 178 } 179 180 /* Perf-Counters: 181 * The select_reg and select_val are just there for the benefit of the child 182 * class that actually enables the perf counter.. but msm_gpu base class 183 * will handle sampling/displaying the counters. 184 */ 185 186 struct msm_gpu_perfcntr { 187 uint32_t select_reg; 188 uint32_t sample_reg; 189 uint32_t select_val; 190 const char *name; 191 }; 192 193 struct msm_gpu_submitqueue { 194 int id; 195 u32 flags; 196 u32 prio; 197 int faults; 198 struct msm_file_private *ctx; 199 struct list_head node; 200 struct kref ref; 201 }; 202 203 struct msm_gpu_state_bo { 204 u64 iova; 205 size_t size; 206 void *data; 207 bool encoded; 208 }; 209 210 struct msm_gpu_state { 211 struct kref ref; 212 struct timespec64 time; 213 214 struct { 215 u64 iova; 216 u32 fence; 217 u32 seqno; 218 u32 rptr; 219 u32 wptr; 220 void *data; 221 int data_size; 222 bool encoded; 223 } ring[MSM_GPU_MAX_RINGS]; 224 225 int nr_registers; 226 u32 *registers; 227 228 u32 rbbm_status; 229 230 char *comm; 231 char *cmd; 232 233 int nr_bos; 234 struct msm_gpu_state_bo *bos; 235 }; 236 237 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) 238 { 239 msm_writel(data, gpu->mmio + (reg << 2)); 240 } 241 242 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) 243 { 244 return msm_readl(gpu->mmio + (reg << 2)); 245 } 246 247 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) 248 { 249 uint32_t val = gpu_read(gpu, reg); 250 251 val &= ~mask; 252 gpu_write(gpu, reg, val | or); 253 } 254 255 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) 256 { 257 u64 val; 258 259 /* 260 * Why not a readq here? Two reasons: 1) many of the LO registers are 261 * not quad word aligned and 2) the GPU hardware designers have a bit 262 * of a history of putting registers where they fit, especially in 263 * spins. The longer a GPU family goes the higher the chance that 264 * we'll get burned. We could do a series of validity checks if we 265 * wanted to, but really is a readq() that much better? Nah. 266 */ 267 268 /* 269 * For some lo/hi registers (like perfcounters), the hi value is latched 270 * when the lo is read, so make sure to read the lo first to trigger 271 * that 272 */ 273 val = (u64) msm_readl(gpu->mmio + (lo << 2)); 274 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); 275 276 return val; 277 } 278 279 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) 280 { 281 /* Why not a writeq here? Read the screed above */ 282 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); 283 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); 284 } 285 286 int msm_gpu_pm_suspend(struct msm_gpu *gpu); 287 int msm_gpu_pm_resume(struct msm_gpu *gpu); 288 void msm_gpu_resume_devfreq(struct msm_gpu *gpu); 289 290 int msm_gpu_hw_init(struct msm_gpu *gpu); 291 292 void msm_gpu_perfcntr_start(struct msm_gpu *gpu); 293 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); 294 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 295 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); 296 297 void msm_gpu_retire(struct msm_gpu *gpu); 298 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); 299 300 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 301 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 302 const char *name, struct msm_gpu_config *config); 303 304 struct msm_gem_address_space * 305 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task); 306 307 void msm_gpu_cleanup(struct msm_gpu *gpu); 308 309 struct msm_gpu *adreno_load_gpu(struct drm_device *dev); 310 void __init adreno_register(void); 311 void __exit adreno_unregister(void); 312 313 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) 314 { 315 if (queue) 316 kref_put(&queue->ref, msm_submitqueue_destroy); 317 } 318 319 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu) 320 { 321 struct msm_gpu_state *state = NULL; 322 323 mutex_lock(&gpu->dev->struct_mutex); 324 325 if (gpu->crashstate) { 326 kref_get(&gpu->crashstate->ref); 327 state = gpu->crashstate; 328 } 329 330 mutex_unlock(&gpu->dev->struct_mutex); 331 332 return state; 333 } 334 335 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) 336 { 337 mutex_lock(&gpu->dev->struct_mutex); 338 339 if (gpu->crashstate) { 340 if (gpu->funcs->gpu_state_put(gpu->crashstate)) 341 gpu->crashstate = NULL; 342 } 343 344 mutex_unlock(&gpu->dev->struct_mutex); 345 } 346 347 /* 348 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can 349 * support expanded privileges 350 */ 351 #define check_apriv(gpu, flags) \ 352 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags)) 353 354 355 #endif /* __MSM_GPU_H__ */ 356