1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "msm_gpu.h" 19 #include "msm_gem.h" 20 21 22 /* 23 * Power Management: 24 */ 25 26 #ifdef CONFIG_MSM_BUS_SCALING 27 #include <mach/board.h> 28 #include <mach/kgsl.h> 29 static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev) 30 { 31 struct drm_device *dev = gpu->dev; 32 struct kgsl_device_platform_data *pdata = pdev->dev.platform_data; 33 34 if (!pdev) { 35 dev_err(dev->dev, "could not find dtv pdata\n"); 36 return; 37 } 38 39 if (pdata->bus_scale_table) { 40 gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table); 41 DBG("bus scale client: %08x", gpu->bsc); 42 } 43 } 44 45 static void bs_fini(struct msm_gpu *gpu) 46 { 47 if (gpu->bsc) { 48 msm_bus_scale_unregister_client(gpu->bsc); 49 gpu->bsc = 0; 50 } 51 } 52 53 static void bs_set(struct msm_gpu *gpu, int idx) 54 { 55 if (gpu->bsc) { 56 DBG("set bus scaling: %d", idx); 57 msm_bus_scale_client_update_request(gpu->bsc, idx); 58 } 59 } 60 #else 61 static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev) {} 62 static void bs_fini(struct msm_gpu *gpu) {} 63 static void bs_set(struct msm_gpu *gpu, int idx) {} 64 #endif 65 66 static int enable_pwrrail(struct msm_gpu *gpu) 67 { 68 struct drm_device *dev = gpu->dev; 69 int ret = 0; 70 71 if (gpu->gpu_reg) { 72 ret = regulator_enable(gpu->gpu_reg); 73 if (ret) { 74 dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 75 return ret; 76 } 77 } 78 79 if (gpu->gpu_cx) { 80 ret = regulator_enable(gpu->gpu_cx); 81 if (ret) { 82 dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 83 return ret; 84 } 85 } 86 87 return 0; 88 } 89 90 static int disable_pwrrail(struct msm_gpu *gpu) 91 { 92 if (gpu->gpu_cx) 93 regulator_disable(gpu->gpu_cx); 94 if (gpu->gpu_reg) 95 regulator_disable(gpu->gpu_reg); 96 return 0; 97 } 98 99 static int enable_clk(struct msm_gpu *gpu) 100 { 101 struct clk *rate_clk = NULL; 102 int i; 103 104 /* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */ 105 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) { 106 if (gpu->grp_clks[i]) { 107 clk_prepare(gpu->grp_clks[i]); 108 rate_clk = gpu->grp_clks[i]; 109 } 110 } 111 112 if (rate_clk && gpu->fast_rate) 113 clk_set_rate(rate_clk, gpu->fast_rate); 114 115 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) 116 if (gpu->grp_clks[i]) 117 clk_enable(gpu->grp_clks[i]); 118 119 return 0; 120 } 121 122 static int disable_clk(struct msm_gpu *gpu) 123 { 124 struct clk *rate_clk = NULL; 125 int i; 126 127 /* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */ 128 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) { 129 if (gpu->grp_clks[i]) { 130 clk_disable(gpu->grp_clks[i]); 131 rate_clk = gpu->grp_clks[i]; 132 } 133 } 134 135 if (rate_clk && gpu->slow_rate) 136 clk_set_rate(rate_clk, gpu->slow_rate); 137 138 for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) 139 if (gpu->grp_clks[i]) 140 clk_unprepare(gpu->grp_clks[i]); 141 142 return 0; 143 } 144 145 static int enable_axi(struct msm_gpu *gpu) 146 { 147 if (gpu->ebi1_clk) 148 clk_prepare_enable(gpu->ebi1_clk); 149 if (gpu->bus_freq) 150 bs_set(gpu, gpu->bus_freq); 151 return 0; 152 } 153 154 static int disable_axi(struct msm_gpu *gpu) 155 { 156 if (gpu->ebi1_clk) 157 clk_disable_unprepare(gpu->ebi1_clk); 158 if (gpu->bus_freq) 159 bs_set(gpu, 0); 160 return 0; 161 } 162 163 int msm_gpu_pm_resume(struct msm_gpu *gpu) 164 { 165 int ret; 166 167 DBG("%s", gpu->name); 168 169 ret = enable_pwrrail(gpu); 170 if (ret) 171 return ret; 172 173 ret = enable_clk(gpu); 174 if (ret) 175 return ret; 176 177 ret = enable_axi(gpu); 178 if (ret) 179 return ret; 180 181 return 0; 182 } 183 184 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 185 { 186 int ret; 187 188 DBG("%s", gpu->name); 189 190 ret = disable_axi(gpu); 191 if (ret) 192 return ret; 193 194 ret = disable_clk(gpu); 195 if (ret) 196 return ret; 197 198 ret = disable_pwrrail(gpu); 199 if (ret) 200 return ret; 201 202 return 0; 203 } 204 205 /* 206 * Hangcheck detection for locked gpu: 207 */ 208 209 static void recover_worker(struct work_struct *work) 210 { 211 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 212 struct drm_device *dev = gpu->dev; 213 214 dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name); 215 216 mutex_lock(&dev->struct_mutex); 217 gpu->funcs->recover(gpu); 218 mutex_unlock(&dev->struct_mutex); 219 220 msm_gpu_retire(gpu); 221 } 222 223 static void hangcheck_timer_reset(struct msm_gpu *gpu) 224 { 225 DBG("%s", gpu->name); 226 mod_timer(&gpu->hangcheck_timer, 227 round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES)); 228 } 229 230 static void hangcheck_handler(unsigned long data) 231 { 232 struct msm_gpu *gpu = (struct msm_gpu *)data; 233 uint32_t fence = gpu->funcs->last_fence(gpu); 234 235 if (fence != gpu->hangcheck_fence) { 236 /* some progress has been made.. ya! */ 237 gpu->hangcheck_fence = fence; 238 } else if (fence < gpu->submitted_fence) { 239 /* no progress and not done.. hung! */ 240 struct msm_drm_private *priv = gpu->dev->dev_private; 241 gpu->hangcheck_fence = fence; 242 queue_work(priv->wq, &gpu->recover_work); 243 } 244 245 /* if still more pending work, reset the hangcheck timer: */ 246 if (gpu->submitted_fence > gpu->hangcheck_fence) 247 hangcheck_timer_reset(gpu); 248 } 249 250 /* 251 * Cmdstream submission/retirement: 252 */ 253 254 static void retire_worker(struct work_struct *work) 255 { 256 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 257 struct drm_device *dev = gpu->dev; 258 uint32_t fence = gpu->funcs->last_fence(gpu); 259 260 mutex_lock(&dev->struct_mutex); 261 262 while (!list_empty(&gpu->active_list)) { 263 struct msm_gem_object *obj; 264 265 obj = list_first_entry(&gpu->active_list, 266 struct msm_gem_object, mm_list); 267 268 if (obj->fence <= fence) { 269 /* move to inactive: */ 270 msm_gem_move_to_inactive(&obj->base); 271 msm_gem_put_iova(&obj->base, gpu->id); 272 drm_gem_object_unreference(&obj->base); 273 } else { 274 break; 275 } 276 } 277 278 msm_update_fence(gpu->dev, fence); 279 280 mutex_unlock(&dev->struct_mutex); 281 } 282 283 /* call from irq handler to schedule work to retire bo's */ 284 void msm_gpu_retire(struct msm_gpu *gpu) 285 { 286 struct msm_drm_private *priv = gpu->dev->dev_private; 287 queue_work(priv->wq, &gpu->retire_work); 288 } 289 290 /* add bo's to gpu's ring, and kick gpu: */ 291 int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 292 struct msm_file_private *ctx) 293 { 294 struct drm_device *dev = gpu->dev; 295 struct msm_drm_private *priv = dev->dev_private; 296 int i, ret; 297 298 mutex_lock(&dev->struct_mutex); 299 300 submit->fence = ++priv->next_fence; 301 302 gpu->submitted_fence = submit->fence; 303 304 ret = gpu->funcs->submit(gpu, submit, ctx); 305 priv->lastctx = ctx; 306 307 for (i = 0; i < submit->nr_bos; i++) { 308 struct msm_gem_object *msm_obj = submit->bos[i].obj; 309 310 /* can't happen yet.. but when we add 2d support we'll have 311 * to deal w/ cross-ring synchronization: 312 */ 313 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); 314 315 if (!is_active(msm_obj)) { 316 uint32_t iova; 317 318 /* ring takes a reference to the bo and iova: */ 319 drm_gem_object_reference(&msm_obj->base); 320 msm_gem_get_iova_locked(&msm_obj->base, 321 submit->gpu->id, &iova); 322 } 323 324 msm_gem_move_to_active(&msm_obj->base, gpu, submit->fence); 325 } 326 hangcheck_timer_reset(gpu); 327 mutex_unlock(&dev->struct_mutex); 328 329 return ret; 330 } 331 332 /* 333 * Init/Cleanup: 334 */ 335 336 static irqreturn_t irq_handler(int irq, void *data) 337 { 338 struct msm_gpu *gpu = data; 339 return gpu->funcs->irq(gpu); 340 } 341 342 static const char *clk_names[] = { 343 "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", 344 }; 345 346 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 347 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 348 const char *name, const char *ioname, const char *irqname, int ringsz) 349 { 350 int i, ret; 351 352 gpu->dev = drm; 353 gpu->funcs = funcs; 354 gpu->name = name; 355 356 INIT_LIST_HEAD(&gpu->active_list); 357 INIT_WORK(&gpu->retire_work, retire_worker); 358 INIT_WORK(&gpu->recover_work, recover_worker); 359 360 setup_timer(&gpu->hangcheck_timer, hangcheck_handler, 361 (unsigned long)gpu); 362 363 BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks)); 364 365 /* Map registers: */ 366 gpu->mmio = msm_ioremap(pdev, ioname, name); 367 if (IS_ERR(gpu->mmio)) { 368 ret = PTR_ERR(gpu->mmio); 369 goto fail; 370 } 371 372 /* Get Interrupt: */ 373 gpu->irq = platform_get_irq_byname(pdev, irqname); 374 if (gpu->irq < 0) { 375 ret = gpu->irq; 376 dev_err(drm->dev, "failed to get irq: %d\n", ret); 377 goto fail; 378 } 379 380 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 381 IRQF_TRIGGER_HIGH, gpu->name, gpu); 382 if (ret) { 383 dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 384 goto fail; 385 } 386 387 /* Acquire clocks: */ 388 for (i = 0; i < ARRAY_SIZE(clk_names); i++) { 389 gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]); 390 DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]); 391 if (IS_ERR(gpu->grp_clks[i])) 392 gpu->grp_clks[i] = NULL; 393 } 394 395 gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk"); 396 DBG("ebi1_clk: %p", gpu->ebi1_clk); 397 if (IS_ERR(gpu->ebi1_clk)) 398 gpu->ebi1_clk = NULL; 399 400 /* Acquire regulators: */ 401 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 402 DBG("gpu_reg: %p", gpu->gpu_reg); 403 if (IS_ERR(gpu->gpu_reg)) 404 gpu->gpu_reg = NULL; 405 406 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 407 DBG("gpu_cx: %p", gpu->gpu_cx); 408 if (IS_ERR(gpu->gpu_cx)) 409 gpu->gpu_cx = NULL; 410 411 /* Setup IOMMU.. eventually we will (I think) do this once per context 412 * and have separate page tables per context. For now, to keep things 413 * simple and to get something working, just use a single address space: 414 */ 415 gpu->iommu = iommu_domain_alloc(&platform_bus_type); 416 if (!gpu->iommu) { 417 dev_err(drm->dev, "failed to allocate IOMMU\n"); 418 ret = -ENOMEM; 419 goto fail; 420 } 421 gpu->id = msm_register_iommu(drm, gpu->iommu); 422 423 /* Create ringbuffer: */ 424 gpu->rb = msm_ringbuffer_new(gpu, ringsz); 425 if (IS_ERR(gpu->rb)) { 426 ret = PTR_ERR(gpu->rb); 427 gpu->rb = NULL; 428 dev_err(drm->dev, "could not create ringbuffer: %d\n", ret); 429 goto fail; 430 } 431 432 ret = msm_gem_get_iova_locked(gpu->rb->bo, gpu->id, &gpu->rb_iova); 433 if (ret) { 434 gpu->rb_iova = 0; 435 dev_err(drm->dev, "could not map ringbuffer: %d\n", ret); 436 goto fail; 437 } 438 439 bs_init(gpu, pdev); 440 441 return 0; 442 443 fail: 444 return ret; 445 } 446 447 void msm_gpu_cleanup(struct msm_gpu *gpu) 448 { 449 DBG("%s", gpu->name); 450 451 WARN_ON(!list_empty(&gpu->active_list)); 452 453 bs_fini(gpu); 454 455 if (gpu->rb) { 456 if (gpu->rb_iova) 457 msm_gem_put_iova(gpu->rb->bo, gpu->id); 458 msm_ringbuffer_destroy(gpu->rb); 459 } 460 461 if (gpu->iommu) 462 iommu_domain_free(gpu->iommu); 463 } 464