1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "msm_gpu.h" 19 #include "msm_gem.h" 20 #include "msm_mmu.h" 21 #include "msm_fence.h" 22 23 #include <generated/utsrelease.h> 24 #include <linux/string_helpers.h> 25 #include <linux/pm_opp.h> 26 #include <linux/devfreq.h> 27 #include <linux/devcoredump.h> 28 29 /* 30 * Power Management: 31 */ 32 33 static int msm_devfreq_target(struct device *dev, unsigned long *freq, 34 u32 flags) 35 { 36 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); 37 struct dev_pm_opp *opp; 38 39 opp = devfreq_recommended_opp(dev, freq, flags); 40 41 if (IS_ERR(opp)) 42 return PTR_ERR(opp); 43 44 clk_set_rate(gpu->core_clk, *freq); 45 dev_pm_opp_put(opp); 46 47 return 0; 48 } 49 50 static int msm_devfreq_get_dev_status(struct device *dev, 51 struct devfreq_dev_status *status) 52 { 53 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); 54 u64 cycles; 55 u32 freq = ((u32) status->current_frequency) / 1000000; 56 ktime_t time; 57 58 status->current_frequency = (unsigned long) clk_get_rate(gpu->core_clk); 59 gpu->funcs->gpu_busy(gpu, &cycles); 60 61 status->busy_time = ((u32) (cycles - gpu->devfreq.busy_cycles)) / freq; 62 63 gpu->devfreq.busy_cycles = cycles; 64 65 time = ktime_get(); 66 status->total_time = ktime_us_delta(time, gpu->devfreq.time); 67 gpu->devfreq.time = time; 68 69 return 0; 70 } 71 72 static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) 73 { 74 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); 75 76 *freq = (unsigned long) clk_get_rate(gpu->core_clk); 77 78 return 0; 79 } 80 81 static struct devfreq_dev_profile msm_devfreq_profile = { 82 .polling_ms = 10, 83 .target = msm_devfreq_target, 84 .get_dev_status = msm_devfreq_get_dev_status, 85 .get_cur_freq = msm_devfreq_get_cur_freq, 86 }; 87 88 static void msm_devfreq_init(struct msm_gpu *gpu) 89 { 90 /* We need target support to do devfreq */ 91 if (!gpu->funcs->gpu_busy || !gpu->core_clk) 92 return; 93 94 msm_devfreq_profile.initial_freq = gpu->fast_rate; 95 96 /* 97 * Don't set the freq_table or max_state and let devfreq build the table 98 * from OPP 99 */ 100 101 gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev, 102 &msm_devfreq_profile, "simple_ondemand", NULL); 103 104 if (IS_ERR(gpu->devfreq.devfreq)) { 105 dev_err(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n"); 106 gpu->devfreq.devfreq = NULL; 107 } 108 } 109 110 static int enable_pwrrail(struct msm_gpu *gpu) 111 { 112 struct drm_device *dev = gpu->dev; 113 int ret = 0; 114 115 if (gpu->gpu_reg) { 116 ret = regulator_enable(gpu->gpu_reg); 117 if (ret) { 118 dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 119 return ret; 120 } 121 } 122 123 if (gpu->gpu_cx) { 124 ret = regulator_enable(gpu->gpu_cx); 125 if (ret) { 126 dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 127 return ret; 128 } 129 } 130 131 return 0; 132 } 133 134 static int disable_pwrrail(struct msm_gpu *gpu) 135 { 136 if (gpu->gpu_cx) 137 regulator_disable(gpu->gpu_cx); 138 if (gpu->gpu_reg) 139 regulator_disable(gpu->gpu_reg); 140 return 0; 141 } 142 143 static int enable_clk(struct msm_gpu *gpu) 144 { 145 if (gpu->core_clk && gpu->fast_rate) 146 clk_set_rate(gpu->core_clk, gpu->fast_rate); 147 148 /* Set the RBBM timer rate to 19.2Mhz */ 149 if (gpu->rbbmtimer_clk) 150 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 151 152 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 153 } 154 155 static int disable_clk(struct msm_gpu *gpu) 156 { 157 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 158 159 /* 160 * Set the clock to a deliberately low rate. On older targets the clock 161 * speed had to be non zero to avoid problems. On newer targets this 162 * will be rounded down to zero anyway so it all works out. 163 */ 164 if (gpu->core_clk) 165 clk_set_rate(gpu->core_clk, 27000000); 166 167 if (gpu->rbbmtimer_clk) 168 clk_set_rate(gpu->rbbmtimer_clk, 0); 169 170 return 0; 171 } 172 173 static int enable_axi(struct msm_gpu *gpu) 174 { 175 if (gpu->ebi1_clk) 176 clk_prepare_enable(gpu->ebi1_clk); 177 return 0; 178 } 179 180 static int disable_axi(struct msm_gpu *gpu) 181 { 182 if (gpu->ebi1_clk) 183 clk_disable_unprepare(gpu->ebi1_clk); 184 return 0; 185 } 186 187 int msm_gpu_pm_resume(struct msm_gpu *gpu) 188 { 189 int ret; 190 191 DBG("%s", gpu->name); 192 193 ret = enable_pwrrail(gpu); 194 if (ret) 195 return ret; 196 197 ret = enable_clk(gpu); 198 if (ret) 199 return ret; 200 201 ret = enable_axi(gpu); 202 if (ret) 203 return ret; 204 205 if (gpu->devfreq.devfreq) { 206 gpu->devfreq.busy_cycles = 0; 207 gpu->devfreq.time = ktime_get(); 208 209 devfreq_resume_device(gpu->devfreq.devfreq); 210 } 211 212 gpu->needs_hw_init = true; 213 214 return 0; 215 } 216 217 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 218 { 219 int ret; 220 221 DBG("%s", gpu->name); 222 223 if (gpu->devfreq.devfreq) 224 devfreq_suspend_device(gpu->devfreq.devfreq); 225 226 ret = disable_axi(gpu); 227 if (ret) 228 return ret; 229 230 ret = disable_clk(gpu); 231 if (ret) 232 return ret; 233 234 ret = disable_pwrrail(gpu); 235 if (ret) 236 return ret; 237 238 return 0; 239 } 240 241 int msm_gpu_hw_init(struct msm_gpu *gpu) 242 { 243 int ret; 244 245 WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex)); 246 247 if (!gpu->needs_hw_init) 248 return 0; 249 250 disable_irq(gpu->irq); 251 ret = gpu->funcs->hw_init(gpu); 252 if (!ret) 253 gpu->needs_hw_init = false; 254 enable_irq(gpu->irq); 255 256 return ret; 257 } 258 259 #ifdef CONFIG_DEV_COREDUMP 260 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 261 size_t count, void *data, size_t datalen) 262 { 263 struct msm_gpu *gpu = data; 264 struct drm_print_iterator iter; 265 struct drm_printer p; 266 struct msm_gpu_state *state; 267 268 state = msm_gpu_crashstate_get(gpu); 269 if (!state) 270 return 0; 271 272 iter.data = buffer; 273 iter.offset = 0; 274 iter.start = offset; 275 iter.remain = count; 276 277 p = drm_coredump_printer(&iter); 278 279 drm_printf(&p, "---\n"); 280 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 281 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 282 drm_printf(&p, "time: %lld.%09ld\n", 283 state->time.tv_sec, state->time.tv_nsec); 284 if (state->comm) 285 drm_printf(&p, "comm: %s\n", state->comm); 286 if (state->cmd) 287 drm_printf(&p, "cmdline: %s\n", state->cmd); 288 289 gpu->funcs->show(gpu, state, &p); 290 291 msm_gpu_crashstate_put(gpu); 292 293 return count - iter.remain; 294 } 295 296 static void msm_gpu_devcoredump_free(void *data) 297 { 298 struct msm_gpu *gpu = data; 299 300 msm_gpu_crashstate_put(gpu); 301 } 302 303 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 304 struct msm_gem_object *obj, u64 iova, u32 flags) 305 { 306 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 307 308 /* Don't record write only objects */ 309 310 state_bo->size = obj->base.size; 311 state_bo->iova = iova; 312 313 /* Only store the data for buffer objects marked for read */ 314 if ((flags & MSM_SUBMIT_BO_READ)) { 315 void *ptr; 316 317 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); 318 if (!state_bo->data) 319 return; 320 321 ptr = msm_gem_get_vaddr_active(&obj->base); 322 if (IS_ERR(ptr)) { 323 kvfree(state_bo->data); 324 return; 325 } 326 327 memcpy(state_bo->data, ptr, obj->base.size); 328 msm_gem_put_vaddr(&obj->base); 329 } 330 331 state->nr_bos++; 332 } 333 334 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 335 struct msm_gem_submit *submit, char *comm, char *cmd) 336 { 337 struct msm_gpu_state *state; 338 339 /* Only save one crash state at a time */ 340 if (gpu->crashstate) 341 return; 342 343 state = gpu->funcs->gpu_state_get(gpu); 344 if (IS_ERR_OR_NULL(state)) 345 return; 346 347 /* Fill in the additional crash state information */ 348 state->comm = kstrdup(comm, GFP_KERNEL); 349 state->cmd = kstrdup(cmd, GFP_KERNEL); 350 351 if (submit) { 352 int i; 353 354 state->bos = kcalloc(submit->nr_bos, 355 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 356 357 for (i = 0; state->bos && i < submit->nr_bos; i++) 358 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj, 359 submit->bos[i].iova, submit->bos[i].flags); 360 } 361 362 /* Set the active crash state to be dumped on failure */ 363 gpu->crashstate = state; 364 365 /* FIXME: Release the crashstate if this errors out? */ 366 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 367 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 368 } 369 #else 370 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm, 371 char *cmd) 372 { 373 } 374 #endif 375 376 /* 377 * Hangcheck detection for locked gpu: 378 */ 379 380 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 381 uint32_t fence) 382 { 383 struct msm_gem_submit *submit; 384 385 list_for_each_entry(submit, &ring->submits, node) { 386 if (submit->seqno > fence) 387 break; 388 389 msm_update_fence(submit->ring->fctx, 390 submit->fence->seqno); 391 } 392 } 393 394 static struct msm_gem_submit * 395 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 396 { 397 struct msm_gem_submit *submit; 398 399 WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex)); 400 401 list_for_each_entry(submit, &ring->submits, node) 402 if (submit->seqno == fence) 403 return submit; 404 405 return NULL; 406 } 407 408 static void retire_submits(struct msm_gpu *gpu); 409 410 static void recover_worker(struct work_struct *work) 411 { 412 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 413 struct drm_device *dev = gpu->dev; 414 struct msm_drm_private *priv = dev->dev_private; 415 struct msm_gem_submit *submit; 416 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 417 char *comm = NULL, *cmd = NULL; 418 int i; 419 420 mutex_lock(&dev->struct_mutex); 421 422 dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name); 423 424 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 425 if (submit) { 426 struct task_struct *task; 427 428 rcu_read_lock(); 429 task = pid_task(submit->pid, PIDTYPE_PID); 430 if (task) { 431 comm = kstrdup(task->comm, GFP_ATOMIC); 432 433 /* 434 * So slightly annoying, in other paths like 435 * mmap'ing gem buffers, mmap_sem is acquired 436 * before struct_mutex, which means we can't 437 * hold struct_mutex across the call to 438 * get_cmdline(). But submits are retired 439 * from the same in-order workqueue, so we can 440 * safely drop the lock here without worrying 441 * about the submit going away. 442 */ 443 mutex_unlock(&dev->struct_mutex); 444 cmd = kstrdup_quotable_cmdline(task, GFP_ATOMIC); 445 mutex_lock(&dev->struct_mutex); 446 } 447 rcu_read_unlock(); 448 449 if (comm && cmd) { 450 dev_err(dev->dev, "%s: offending task: %s (%s)\n", 451 gpu->name, comm, cmd); 452 453 msm_rd_dump_submit(priv->hangrd, submit, 454 "offending task: %s (%s)", comm, cmd); 455 } else 456 msm_rd_dump_submit(priv->hangrd, submit, NULL); 457 } 458 459 /* Record the crash state */ 460 pm_runtime_get_sync(&gpu->pdev->dev); 461 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); 462 pm_runtime_put_sync(&gpu->pdev->dev); 463 464 kfree(cmd); 465 kfree(comm); 466 467 /* 468 * Update all the rings with the latest and greatest fence.. this 469 * needs to happen after msm_rd_dump_submit() to ensure that the 470 * bo's referenced by the offending submit are still around. 471 */ 472 for (i = 0; i < gpu->nr_rings; i++) { 473 struct msm_ringbuffer *ring = gpu->rb[i]; 474 475 uint32_t fence = ring->memptrs->fence; 476 477 /* 478 * For the current (faulting?) ring/submit advance the fence by 479 * one more to clear the faulting submit 480 */ 481 if (ring == cur_ring) 482 fence++; 483 484 update_fences(gpu, ring, fence); 485 } 486 487 if (msm_gpu_active(gpu)) { 488 /* retire completed submits, plus the one that hung: */ 489 retire_submits(gpu); 490 491 pm_runtime_get_sync(&gpu->pdev->dev); 492 gpu->funcs->recover(gpu); 493 pm_runtime_put_sync(&gpu->pdev->dev); 494 495 /* 496 * Replay all remaining submits starting with highest priority 497 * ring 498 */ 499 for (i = 0; i < gpu->nr_rings; i++) { 500 struct msm_ringbuffer *ring = gpu->rb[i]; 501 502 list_for_each_entry(submit, &ring->submits, node) 503 gpu->funcs->submit(gpu, submit, NULL); 504 } 505 } 506 507 mutex_unlock(&dev->struct_mutex); 508 509 msm_gpu_retire(gpu); 510 } 511 512 static void hangcheck_timer_reset(struct msm_gpu *gpu) 513 { 514 DBG("%s", gpu->name); 515 mod_timer(&gpu->hangcheck_timer, 516 round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES)); 517 } 518 519 static void hangcheck_handler(struct timer_list *t) 520 { 521 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); 522 struct drm_device *dev = gpu->dev; 523 struct msm_drm_private *priv = dev->dev_private; 524 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 525 uint32_t fence = ring->memptrs->fence; 526 527 if (fence != ring->hangcheck_fence) { 528 /* some progress has been made.. ya! */ 529 ring->hangcheck_fence = fence; 530 } else if (fence < ring->seqno) { 531 /* no progress and not done.. hung! */ 532 ring->hangcheck_fence = fence; 533 dev_err(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 534 gpu->name, ring->id); 535 dev_err(dev->dev, "%s: completed fence: %u\n", 536 gpu->name, fence); 537 dev_err(dev->dev, "%s: submitted fence: %u\n", 538 gpu->name, ring->seqno); 539 540 queue_work(priv->wq, &gpu->recover_work); 541 } 542 543 /* if still more pending work, reset the hangcheck timer: */ 544 if (ring->seqno > ring->hangcheck_fence) 545 hangcheck_timer_reset(gpu); 546 547 /* workaround for missing irq: */ 548 queue_work(priv->wq, &gpu->retire_work); 549 } 550 551 /* 552 * Performance Counters: 553 */ 554 555 /* called under perf_lock */ 556 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 557 { 558 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 559 int i, n = min(ncntrs, gpu->num_perfcntrs); 560 561 /* read current values: */ 562 for (i = 0; i < gpu->num_perfcntrs; i++) 563 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 564 565 /* update cntrs: */ 566 for (i = 0; i < n; i++) 567 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 568 569 /* save current values: */ 570 for (i = 0; i < gpu->num_perfcntrs; i++) 571 gpu->last_cntrs[i] = current_cntrs[i]; 572 573 return n; 574 } 575 576 static void update_sw_cntrs(struct msm_gpu *gpu) 577 { 578 ktime_t time; 579 uint32_t elapsed; 580 unsigned long flags; 581 582 spin_lock_irqsave(&gpu->perf_lock, flags); 583 if (!gpu->perfcntr_active) 584 goto out; 585 586 time = ktime_get(); 587 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 588 589 gpu->totaltime += elapsed; 590 if (gpu->last_sample.active) 591 gpu->activetime += elapsed; 592 593 gpu->last_sample.active = msm_gpu_active(gpu); 594 gpu->last_sample.time = time; 595 596 out: 597 spin_unlock_irqrestore(&gpu->perf_lock, flags); 598 } 599 600 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 601 { 602 unsigned long flags; 603 604 pm_runtime_get_sync(&gpu->pdev->dev); 605 606 spin_lock_irqsave(&gpu->perf_lock, flags); 607 /* we could dynamically enable/disable perfcntr registers too.. */ 608 gpu->last_sample.active = msm_gpu_active(gpu); 609 gpu->last_sample.time = ktime_get(); 610 gpu->activetime = gpu->totaltime = 0; 611 gpu->perfcntr_active = true; 612 update_hw_cntrs(gpu, 0, NULL); 613 spin_unlock_irqrestore(&gpu->perf_lock, flags); 614 } 615 616 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 617 { 618 gpu->perfcntr_active = false; 619 pm_runtime_put_sync(&gpu->pdev->dev); 620 } 621 622 /* returns -errno or # of cntrs sampled */ 623 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 624 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 625 { 626 unsigned long flags; 627 int ret; 628 629 spin_lock_irqsave(&gpu->perf_lock, flags); 630 631 if (!gpu->perfcntr_active) { 632 ret = -EINVAL; 633 goto out; 634 } 635 636 *activetime = gpu->activetime; 637 *totaltime = gpu->totaltime; 638 639 gpu->activetime = gpu->totaltime = 0; 640 641 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 642 643 out: 644 spin_unlock_irqrestore(&gpu->perf_lock, flags); 645 646 return ret; 647 } 648 649 /* 650 * Cmdstream submission/retirement: 651 */ 652 653 static void retire_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 654 { 655 int i; 656 657 for (i = 0; i < submit->nr_bos; i++) { 658 struct msm_gem_object *msm_obj = submit->bos[i].obj; 659 /* move to inactive: */ 660 msm_gem_move_to_inactive(&msm_obj->base); 661 msm_gem_put_iova(&msm_obj->base, gpu->aspace); 662 drm_gem_object_put(&msm_obj->base); 663 } 664 665 pm_runtime_mark_last_busy(&gpu->pdev->dev); 666 pm_runtime_put_autosuspend(&gpu->pdev->dev); 667 msm_gem_submit_free(submit); 668 } 669 670 static void retire_submits(struct msm_gpu *gpu) 671 { 672 struct drm_device *dev = gpu->dev; 673 struct msm_gem_submit *submit, *tmp; 674 int i; 675 676 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 677 678 /* Retire the commits starting with highest priority */ 679 for (i = 0; i < gpu->nr_rings; i++) { 680 struct msm_ringbuffer *ring = gpu->rb[i]; 681 682 list_for_each_entry_safe(submit, tmp, &ring->submits, node) { 683 if (dma_fence_is_signaled(submit->fence)) 684 retire_submit(gpu, submit); 685 } 686 } 687 } 688 689 static void retire_worker(struct work_struct *work) 690 { 691 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 692 struct drm_device *dev = gpu->dev; 693 int i; 694 695 for (i = 0; i < gpu->nr_rings; i++) 696 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); 697 698 mutex_lock(&dev->struct_mutex); 699 retire_submits(gpu); 700 mutex_unlock(&dev->struct_mutex); 701 } 702 703 /* call from irq handler to schedule work to retire bo's */ 704 void msm_gpu_retire(struct msm_gpu *gpu) 705 { 706 struct msm_drm_private *priv = gpu->dev->dev_private; 707 queue_work(priv->wq, &gpu->retire_work); 708 update_sw_cntrs(gpu); 709 } 710 711 /* add bo's to gpu's ring, and kick gpu: */ 712 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 713 struct msm_file_private *ctx) 714 { 715 struct drm_device *dev = gpu->dev; 716 struct msm_drm_private *priv = dev->dev_private; 717 struct msm_ringbuffer *ring = submit->ring; 718 int i; 719 720 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 721 722 pm_runtime_get_sync(&gpu->pdev->dev); 723 724 msm_gpu_hw_init(gpu); 725 726 submit->seqno = ++ring->seqno; 727 728 list_add_tail(&submit->node, &ring->submits); 729 730 msm_rd_dump_submit(priv->rd, submit, NULL); 731 732 update_sw_cntrs(gpu); 733 734 for (i = 0; i < submit->nr_bos; i++) { 735 struct msm_gem_object *msm_obj = submit->bos[i].obj; 736 uint64_t iova; 737 738 /* can't happen yet.. but when we add 2d support we'll have 739 * to deal w/ cross-ring synchronization: 740 */ 741 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); 742 743 /* submit takes a reference to the bo and iova until retired: */ 744 drm_gem_object_get(&msm_obj->base); 745 msm_gem_get_iova(&msm_obj->base, 746 submit->gpu->aspace, &iova); 747 748 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) 749 msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); 750 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ) 751 msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); 752 } 753 754 gpu->funcs->submit(gpu, submit, ctx); 755 priv->lastctx = ctx; 756 757 hangcheck_timer_reset(gpu); 758 } 759 760 /* 761 * Init/Cleanup: 762 */ 763 764 static irqreturn_t irq_handler(int irq, void *data) 765 { 766 struct msm_gpu *gpu = data; 767 return gpu->funcs->irq(gpu); 768 } 769 770 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 771 { 772 int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks); 773 774 if (ret < 1) { 775 gpu->nr_clocks = 0; 776 return ret; 777 } 778 779 gpu->nr_clocks = ret; 780 781 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 782 gpu->nr_clocks, "core"); 783 784 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 785 gpu->nr_clocks, "rbbmtimer"); 786 787 return 0; 788 } 789 790 static struct msm_gem_address_space * 791 msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, 792 uint64_t va_start, uint64_t va_end) 793 { 794 struct iommu_domain *iommu; 795 struct msm_gem_address_space *aspace; 796 int ret; 797 798 /* 799 * Setup IOMMU.. eventually we will (I think) do this once per context 800 * and have separate page tables per context. For now, to keep things 801 * simple and to get something working, just use a single address space: 802 */ 803 iommu = iommu_domain_alloc(&platform_bus_type); 804 if (!iommu) 805 return NULL; 806 807 iommu->geometry.aperture_start = va_start; 808 iommu->geometry.aperture_end = va_end; 809 810 dev_info(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); 811 812 aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu"); 813 if (IS_ERR(aspace)) { 814 dev_err(gpu->dev->dev, "failed to init iommu: %ld\n", 815 PTR_ERR(aspace)); 816 iommu_domain_free(iommu); 817 return ERR_CAST(aspace); 818 } 819 820 ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); 821 if (ret) { 822 msm_gem_address_space_put(aspace); 823 return ERR_PTR(ret); 824 } 825 826 return aspace; 827 } 828 829 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 830 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 831 const char *name, struct msm_gpu_config *config) 832 { 833 int i, ret, nr_rings = config->nr_rings; 834 void *memptrs; 835 uint64_t memptrs_iova; 836 837 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 838 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 839 840 gpu->dev = drm; 841 gpu->funcs = funcs; 842 gpu->name = name; 843 844 INIT_LIST_HEAD(&gpu->active_list); 845 INIT_WORK(&gpu->retire_work, retire_worker); 846 INIT_WORK(&gpu->recover_work, recover_worker); 847 848 849 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 850 851 spin_lock_init(&gpu->perf_lock); 852 853 854 /* Map registers: */ 855 gpu->mmio = msm_ioremap(pdev, config->ioname, name); 856 if (IS_ERR(gpu->mmio)) { 857 ret = PTR_ERR(gpu->mmio); 858 goto fail; 859 } 860 861 /* Get Interrupt: */ 862 gpu->irq = platform_get_irq_byname(pdev, config->irqname); 863 if (gpu->irq < 0) { 864 ret = gpu->irq; 865 dev_err(drm->dev, "failed to get irq: %d\n", ret); 866 goto fail; 867 } 868 869 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 870 IRQF_TRIGGER_HIGH, gpu->name, gpu); 871 if (ret) { 872 dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 873 goto fail; 874 } 875 876 ret = get_clocks(pdev, gpu); 877 if (ret) 878 goto fail; 879 880 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 881 DBG("ebi1_clk: %p", gpu->ebi1_clk); 882 if (IS_ERR(gpu->ebi1_clk)) 883 gpu->ebi1_clk = NULL; 884 885 /* Acquire regulators: */ 886 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 887 DBG("gpu_reg: %p", gpu->gpu_reg); 888 if (IS_ERR(gpu->gpu_reg)) 889 gpu->gpu_reg = NULL; 890 891 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 892 DBG("gpu_cx: %p", gpu->gpu_cx); 893 if (IS_ERR(gpu->gpu_cx)) 894 gpu->gpu_cx = NULL; 895 896 gpu->pdev = pdev; 897 platform_set_drvdata(pdev, gpu); 898 899 msm_devfreq_init(gpu); 900 901 gpu->aspace = msm_gpu_create_address_space(gpu, pdev, 902 config->va_start, config->va_end); 903 904 if (gpu->aspace == NULL) 905 dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); 906 else if (IS_ERR(gpu->aspace)) { 907 ret = PTR_ERR(gpu->aspace); 908 goto fail; 909 } 910 911 memptrs = msm_gem_kernel_new(drm, sizeof(*gpu->memptrs_bo), 912 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, 913 &memptrs_iova); 914 915 if (IS_ERR(memptrs)) { 916 ret = PTR_ERR(memptrs); 917 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); 918 goto fail; 919 } 920 921 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 922 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 923 ARRAY_SIZE(gpu->rb)); 924 nr_rings = ARRAY_SIZE(gpu->rb); 925 } 926 927 /* Create ringbuffer(s): */ 928 for (i = 0; i < nr_rings; i++) { 929 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 930 931 if (IS_ERR(gpu->rb[i])) { 932 ret = PTR_ERR(gpu->rb[i]); 933 dev_err(drm->dev, 934 "could not create ringbuffer %d: %d\n", i, ret); 935 goto fail; 936 } 937 938 memptrs += sizeof(struct msm_rbmemptrs); 939 memptrs_iova += sizeof(struct msm_rbmemptrs); 940 } 941 942 gpu->nr_rings = nr_rings; 943 944 return 0; 945 946 fail: 947 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 948 msm_ringbuffer_destroy(gpu->rb[i]); 949 gpu->rb[i] = NULL; 950 } 951 952 if (gpu->memptrs_bo) { 953 msm_gem_put_vaddr(gpu->memptrs_bo); 954 msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace); 955 drm_gem_object_put_unlocked(gpu->memptrs_bo); 956 } 957 958 platform_set_drvdata(pdev, NULL); 959 return ret; 960 } 961 962 void msm_gpu_cleanup(struct msm_gpu *gpu) 963 { 964 int i; 965 966 DBG("%s", gpu->name); 967 968 WARN_ON(!list_empty(&gpu->active_list)); 969 970 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 971 msm_ringbuffer_destroy(gpu->rb[i]); 972 gpu->rb[i] = NULL; 973 } 974 975 if (gpu->memptrs_bo) { 976 msm_gem_put_vaddr(gpu->memptrs_bo); 977 msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace); 978 drm_gem_object_put_unlocked(gpu->memptrs_bo); 979 } 980 981 if (!IS_ERR_OR_NULL(gpu->aspace)) { 982 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, 983 NULL, 0); 984 msm_gem_address_space_put(gpu->aspace); 985 } 986 } 987