1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "drm/drm_drv.h" 8 9 #include "msm_gpu.h" 10 #include "msm_gem.h" 11 #include "msm_mmu.h" 12 #include "msm_fence.h" 13 #include "msm_gpu_trace.h" 14 #include "adreno/adreno_gpu.h" 15 16 #include <generated/utsrelease.h> 17 #include <linux/string_helpers.h> 18 #include <linux/devcoredump.h> 19 #include <linux/sched/task.h> 20 21 /* 22 * Power Management: 23 */ 24 25 static int enable_pwrrail(struct msm_gpu *gpu) 26 { 27 struct drm_device *dev = gpu->dev; 28 int ret = 0; 29 30 if (gpu->gpu_reg) { 31 ret = regulator_enable(gpu->gpu_reg); 32 if (ret) { 33 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 34 return ret; 35 } 36 } 37 38 if (gpu->gpu_cx) { 39 ret = regulator_enable(gpu->gpu_cx); 40 if (ret) { 41 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 42 return ret; 43 } 44 } 45 46 return 0; 47 } 48 49 static int disable_pwrrail(struct msm_gpu *gpu) 50 { 51 if (gpu->gpu_cx) 52 regulator_disable(gpu->gpu_cx); 53 if (gpu->gpu_reg) 54 regulator_disable(gpu->gpu_reg); 55 return 0; 56 } 57 58 static int enable_clk(struct msm_gpu *gpu) 59 { 60 if (gpu->core_clk && gpu->fast_rate) 61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); 62 63 /* Set the RBBM timer rate to 19.2Mhz */ 64 if (gpu->rbbmtimer_clk) 65 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 66 67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 68 } 69 70 static int disable_clk(struct msm_gpu *gpu) 71 { 72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 73 74 /* 75 * Set the clock to a deliberately low rate. On older targets the clock 76 * speed had to be non zero to avoid problems. On newer targets this 77 * will be rounded down to zero anyway so it all works out. 78 */ 79 if (gpu->core_clk) 80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); 81 82 if (gpu->rbbmtimer_clk) 83 clk_set_rate(gpu->rbbmtimer_clk, 0); 84 85 return 0; 86 } 87 88 static int enable_axi(struct msm_gpu *gpu) 89 { 90 return clk_prepare_enable(gpu->ebi1_clk); 91 } 92 93 static int disable_axi(struct msm_gpu *gpu) 94 { 95 clk_disable_unprepare(gpu->ebi1_clk); 96 return 0; 97 } 98 99 int msm_gpu_pm_resume(struct msm_gpu *gpu) 100 { 101 int ret; 102 103 DBG("%s", gpu->name); 104 trace_msm_gpu_resume(0); 105 106 ret = enable_pwrrail(gpu); 107 if (ret) 108 return ret; 109 110 ret = enable_clk(gpu); 111 if (ret) 112 return ret; 113 114 ret = enable_axi(gpu); 115 if (ret) 116 return ret; 117 118 msm_devfreq_resume(gpu); 119 120 gpu->needs_hw_init = true; 121 122 return 0; 123 } 124 125 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 126 { 127 int ret; 128 129 DBG("%s", gpu->name); 130 trace_msm_gpu_suspend(0); 131 132 msm_devfreq_suspend(gpu); 133 134 ret = disable_axi(gpu); 135 if (ret) 136 return ret; 137 138 ret = disable_clk(gpu); 139 if (ret) 140 return ret; 141 142 ret = disable_pwrrail(gpu); 143 if (ret) 144 return ret; 145 146 gpu->suspend_count++; 147 148 return 0; 149 } 150 151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx, 152 struct drm_printer *p) 153 { 154 drm_printf(p, "drm-driver:\t%s\n", gpu->dev->driver->name); 155 drm_printf(p, "drm-client-id:\t%u\n", ctx->seqno); 156 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns); 157 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles); 158 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate); 159 } 160 161 int msm_gpu_hw_init(struct msm_gpu *gpu) 162 { 163 int ret; 164 165 WARN_ON(!mutex_is_locked(&gpu->lock)); 166 167 if (!gpu->needs_hw_init) 168 return 0; 169 170 disable_irq(gpu->irq); 171 ret = gpu->funcs->hw_init(gpu); 172 if (!ret) 173 gpu->needs_hw_init = false; 174 enable_irq(gpu->irq); 175 176 return ret; 177 } 178 179 #ifdef CONFIG_DEV_COREDUMP 180 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 181 size_t count, void *data, size_t datalen) 182 { 183 struct msm_gpu *gpu = data; 184 struct drm_print_iterator iter; 185 struct drm_printer p; 186 struct msm_gpu_state *state; 187 188 state = msm_gpu_crashstate_get(gpu); 189 if (!state) 190 return 0; 191 192 iter.data = buffer; 193 iter.offset = 0; 194 iter.start = offset; 195 iter.remain = count; 196 197 p = drm_coredump_printer(&iter); 198 199 drm_printf(&p, "---\n"); 200 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 201 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 202 drm_printf(&p, "time: %lld.%09ld\n", 203 state->time.tv_sec, state->time.tv_nsec); 204 if (state->comm) 205 drm_printf(&p, "comm: %s\n", state->comm); 206 if (state->cmd) 207 drm_printf(&p, "cmdline: %s\n", state->cmd); 208 209 gpu->funcs->show(gpu, state, &p); 210 211 msm_gpu_crashstate_put(gpu); 212 213 return count - iter.remain; 214 } 215 216 static void msm_gpu_devcoredump_free(void *data) 217 { 218 struct msm_gpu *gpu = data; 219 220 msm_gpu_crashstate_put(gpu); 221 } 222 223 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 224 struct msm_gem_object *obj, u64 iova, bool full) 225 { 226 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 227 228 /* Don't record write only objects */ 229 state_bo->size = obj->base.size; 230 state_bo->iova = iova; 231 232 BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(obj->name)); 233 234 memcpy(state_bo->name, obj->name, sizeof(state_bo->name)); 235 236 if (full) { 237 void *ptr; 238 239 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); 240 if (!state_bo->data) 241 goto out; 242 243 msm_gem_lock(&obj->base); 244 ptr = msm_gem_get_vaddr_active(&obj->base); 245 msm_gem_unlock(&obj->base); 246 if (IS_ERR(ptr)) { 247 kvfree(state_bo->data); 248 state_bo->data = NULL; 249 goto out; 250 } 251 252 memcpy(state_bo->data, ptr, obj->base.size); 253 msm_gem_put_vaddr(&obj->base); 254 } 255 out: 256 state->nr_bos++; 257 } 258 259 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 260 struct msm_gem_submit *submit, char *comm, char *cmd) 261 { 262 struct msm_gpu_state *state; 263 264 /* Check if the target supports capturing crash state */ 265 if (!gpu->funcs->gpu_state_get) 266 return; 267 268 /* Only save one crash state at a time */ 269 if (gpu->crashstate) 270 return; 271 272 state = gpu->funcs->gpu_state_get(gpu); 273 if (IS_ERR_OR_NULL(state)) 274 return; 275 276 /* Fill in the additional crash state information */ 277 state->comm = kstrdup(comm, GFP_KERNEL); 278 state->cmd = kstrdup(cmd, GFP_KERNEL); 279 state->fault_info = gpu->fault_info; 280 281 if (submit) { 282 int i; 283 284 state->bos = kcalloc(submit->nr_bos, 285 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 286 287 for (i = 0; state->bos && i < submit->nr_bos; i++) { 288 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj, 289 submit->bos[i].iova, 290 should_dump(submit, i)); 291 } 292 } 293 294 /* Set the active crash state to be dumped on failure */ 295 gpu->crashstate = state; 296 297 /* FIXME: Release the crashstate if this errors out? */ 298 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 299 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 300 } 301 #else 302 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 303 struct msm_gem_submit *submit, char *comm, char *cmd) 304 { 305 } 306 #endif 307 308 /* 309 * Hangcheck detection for locked gpu: 310 */ 311 312 static struct msm_gem_submit * 313 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 314 { 315 struct msm_gem_submit *submit; 316 unsigned long flags; 317 318 spin_lock_irqsave(&ring->submit_lock, flags); 319 list_for_each_entry(submit, &ring->submits, node) { 320 if (submit->seqno == fence) { 321 spin_unlock_irqrestore(&ring->submit_lock, flags); 322 return submit; 323 } 324 } 325 spin_unlock_irqrestore(&ring->submit_lock, flags); 326 327 return NULL; 328 } 329 330 static void retire_submits(struct msm_gpu *gpu); 331 332 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd) 333 { 334 struct msm_file_private *ctx = submit->queue->ctx; 335 struct task_struct *task; 336 337 WARN_ON(!mutex_is_locked(&submit->gpu->lock)); 338 339 /* Note that kstrdup will return NULL if argument is NULL: */ 340 *comm = kstrdup(ctx->comm, GFP_KERNEL); 341 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL); 342 343 task = get_pid_task(submit->pid, PIDTYPE_PID); 344 if (!task) 345 return; 346 347 if (!*comm) 348 *comm = kstrdup(task->comm, GFP_KERNEL); 349 350 if (!*cmd) 351 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 352 353 put_task_struct(task); 354 } 355 356 static void recover_worker(struct kthread_work *work) 357 { 358 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 359 struct drm_device *dev = gpu->dev; 360 struct msm_drm_private *priv = dev->dev_private; 361 struct msm_gem_submit *submit; 362 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 363 char *comm = NULL, *cmd = NULL; 364 int i; 365 366 mutex_lock(&gpu->lock); 367 368 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); 369 370 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 371 if (submit) { 372 /* Increment the fault counts */ 373 submit->queue->faults++; 374 if (submit->aspace) 375 submit->aspace->faults++; 376 377 get_comm_cmdline(submit, &comm, &cmd); 378 379 if (comm && cmd) { 380 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", 381 gpu->name, comm, cmd); 382 383 msm_rd_dump_submit(priv->hangrd, submit, 384 "offending task: %s (%s)", comm, cmd); 385 } else { 386 msm_rd_dump_submit(priv->hangrd, submit, NULL); 387 } 388 } else { 389 /* 390 * We couldn't attribute this fault to any particular context, 391 * so increment the global fault count instead. 392 */ 393 gpu->global_faults++; 394 } 395 396 /* Record the crash state */ 397 pm_runtime_get_sync(&gpu->pdev->dev); 398 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); 399 400 kfree(cmd); 401 kfree(comm); 402 403 /* 404 * Update all the rings with the latest and greatest fence.. this 405 * needs to happen after msm_rd_dump_submit() to ensure that the 406 * bo's referenced by the offending submit are still around. 407 */ 408 for (i = 0; i < gpu->nr_rings; i++) { 409 struct msm_ringbuffer *ring = gpu->rb[i]; 410 411 uint32_t fence = ring->memptrs->fence; 412 413 /* 414 * For the current (faulting?) ring/submit advance the fence by 415 * one more to clear the faulting submit 416 */ 417 if (ring == cur_ring) 418 ring->memptrs->fence = ++fence; 419 420 msm_update_fence(ring->fctx, fence); 421 } 422 423 if (msm_gpu_active(gpu)) { 424 /* retire completed submits, plus the one that hung: */ 425 retire_submits(gpu); 426 427 gpu->funcs->recover(gpu); 428 429 /* 430 * Replay all remaining submits starting with highest priority 431 * ring 432 */ 433 for (i = 0; i < gpu->nr_rings; i++) { 434 struct msm_ringbuffer *ring = gpu->rb[i]; 435 unsigned long flags; 436 437 spin_lock_irqsave(&ring->submit_lock, flags); 438 list_for_each_entry(submit, &ring->submits, node) 439 gpu->funcs->submit(gpu, submit); 440 spin_unlock_irqrestore(&ring->submit_lock, flags); 441 } 442 } 443 444 pm_runtime_put(&gpu->pdev->dev); 445 446 mutex_unlock(&gpu->lock); 447 448 msm_gpu_retire(gpu); 449 } 450 451 static void fault_worker(struct kthread_work *work) 452 { 453 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work); 454 struct msm_gem_submit *submit; 455 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 456 char *comm = NULL, *cmd = NULL; 457 458 mutex_lock(&gpu->lock); 459 460 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 461 if (submit && submit->fault_dumped) 462 goto resume_smmu; 463 464 if (submit) { 465 get_comm_cmdline(submit, &comm, &cmd); 466 467 /* 468 * When we get GPU iova faults, we can get 1000s of them, 469 * but we really only want to log the first one. 470 */ 471 submit->fault_dumped = true; 472 } 473 474 /* Record the crash state */ 475 pm_runtime_get_sync(&gpu->pdev->dev); 476 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); 477 pm_runtime_put_sync(&gpu->pdev->dev); 478 479 kfree(cmd); 480 kfree(comm); 481 482 resume_smmu: 483 memset(&gpu->fault_info, 0, sizeof(gpu->fault_info)); 484 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); 485 486 mutex_unlock(&gpu->lock); 487 } 488 489 static void hangcheck_timer_reset(struct msm_gpu *gpu) 490 { 491 struct msm_drm_private *priv = gpu->dev->dev_private; 492 mod_timer(&gpu->hangcheck_timer, 493 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period))); 494 } 495 496 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 497 { 498 if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES) 499 return false; 500 501 if (!gpu->funcs->progress) 502 return false; 503 504 if (!gpu->funcs->progress(gpu, ring)) 505 return false; 506 507 ring->hangcheck_progress_retries++; 508 return true; 509 } 510 511 static void hangcheck_handler(struct timer_list *t) 512 { 513 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); 514 struct drm_device *dev = gpu->dev; 515 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 516 uint32_t fence = ring->memptrs->fence; 517 518 if (fence != ring->hangcheck_fence) { 519 /* some progress has been made.. ya! */ 520 ring->hangcheck_fence = fence; 521 ring->hangcheck_progress_retries = 0; 522 } else if (fence_before(fence, ring->fctx->last_fence) && 523 !made_progress(gpu, ring)) { 524 /* no progress and not done.. hung! */ 525 ring->hangcheck_fence = fence; 526 ring->hangcheck_progress_retries = 0; 527 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 528 gpu->name, ring->id); 529 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", 530 gpu->name, fence); 531 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", 532 gpu->name, ring->fctx->last_fence); 533 534 kthread_queue_work(gpu->worker, &gpu->recover_work); 535 } 536 537 /* if still more pending work, reset the hangcheck timer: */ 538 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence)) 539 hangcheck_timer_reset(gpu); 540 541 /* workaround for missing irq: */ 542 msm_gpu_retire(gpu); 543 } 544 545 /* 546 * Performance Counters: 547 */ 548 549 /* called under perf_lock */ 550 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 551 { 552 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 553 int i, n = min(ncntrs, gpu->num_perfcntrs); 554 555 /* read current values: */ 556 for (i = 0; i < gpu->num_perfcntrs; i++) 557 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 558 559 /* update cntrs: */ 560 for (i = 0; i < n; i++) 561 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 562 563 /* save current values: */ 564 for (i = 0; i < gpu->num_perfcntrs; i++) 565 gpu->last_cntrs[i] = current_cntrs[i]; 566 567 return n; 568 } 569 570 static void update_sw_cntrs(struct msm_gpu *gpu) 571 { 572 ktime_t time; 573 uint32_t elapsed; 574 unsigned long flags; 575 576 spin_lock_irqsave(&gpu->perf_lock, flags); 577 if (!gpu->perfcntr_active) 578 goto out; 579 580 time = ktime_get(); 581 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 582 583 gpu->totaltime += elapsed; 584 if (gpu->last_sample.active) 585 gpu->activetime += elapsed; 586 587 gpu->last_sample.active = msm_gpu_active(gpu); 588 gpu->last_sample.time = time; 589 590 out: 591 spin_unlock_irqrestore(&gpu->perf_lock, flags); 592 } 593 594 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 595 { 596 unsigned long flags; 597 598 pm_runtime_get_sync(&gpu->pdev->dev); 599 600 spin_lock_irqsave(&gpu->perf_lock, flags); 601 /* we could dynamically enable/disable perfcntr registers too.. */ 602 gpu->last_sample.active = msm_gpu_active(gpu); 603 gpu->last_sample.time = ktime_get(); 604 gpu->activetime = gpu->totaltime = 0; 605 gpu->perfcntr_active = true; 606 update_hw_cntrs(gpu, 0, NULL); 607 spin_unlock_irqrestore(&gpu->perf_lock, flags); 608 } 609 610 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 611 { 612 gpu->perfcntr_active = false; 613 pm_runtime_put_sync(&gpu->pdev->dev); 614 } 615 616 /* returns -errno or # of cntrs sampled */ 617 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 618 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 619 { 620 unsigned long flags; 621 int ret; 622 623 spin_lock_irqsave(&gpu->perf_lock, flags); 624 625 if (!gpu->perfcntr_active) { 626 ret = -EINVAL; 627 goto out; 628 } 629 630 *activetime = gpu->activetime; 631 *totaltime = gpu->totaltime; 632 633 gpu->activetime = gpu->totaltime = 0; 634 635 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 636 637 out: 638 spin_unlock_irqrestore(&gpu->perf_lock, flags); 639 640 return ret; 641 } 642 643 /* 644 * Cmdstream submission/retirement: 645 */ 646 647 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 648 struct msm_gem_submit *submit) 649 { 650 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 651 volatile struct msm_gpu_submit_stats *stats; 652 u64 elapsed, clock = 0, cycles; 653 unsigned long flags; 654 655 stats = &ring->memptrs->stats[index]; 656 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ 657 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; 658 do_div(elapsed, 192); 659 660 cycles = stats->cpcycles_end - stats->cpcycles_start; 661 662 /* Calculate the clock frequency from the number of CP cycles */ 663 if (elapsed) { 664 clock = cycles * 1000; 665 do_div(clock, elapsed); 666 } 667 668 submit->queue->ctx->elapsed_ns += elapsed; 669 submit->queue->ctx->cycles += cycles; 670 671 trace_msm_gpu_submit_retired(submit, elapsed, clock, 672 stats->alwayson_start, stats->alwayson_end); 673 674 msm_submit_retire(submit); 675 676 pm_runtime_mark_last_busy(&gpu->pdev->dev); 677 678 spin_lock_irqsave(&ring->submit_lock, flags); 679 list_del(&submit->node); 680 spin_unlock_irqrestore(&ring->submit_lock, flags); 681 682 /* Update devfreq on transition from active->idle: */ 683 mutex_lock(&gpu->active_lock); 684 gpu->active_submits--; 685 WARN_ON(gpu->active_submits < 0); 686 if (!gpu->active_submits) { 687 msm_devfreq_idle(gpu); 688 pm_runtime_put_autosuspend(&gpu->pdev->dev); 689 } 690 691 mutex_unlock(&gpu->active_lock); 692 693 msm_gem_submit_put(submit); 694 } 695 696 static void retire_submits(struct msm_gpu *gpu) 697 { 698 int i; 699 700 /* Retire the commits starting with highest priority */ 701 for (i = 0; i < gpu->nr_rings; i++) { 702 struct msm_ringbuffer *ring = gpu->rb[i]; 703 704 while (true) { 705 struct msm_gem_submit *submit = NULL; 706 unsigned long flags; 707 708 spin_lock_irqsave(&ring->submit_lock, flags); 709 submit = list_first_entry_or_null(&ring->submits, 710 struct msm_gem_submit, node); 711 spin_unlock_irqrestore(&ring->submit_lock, flags); 712 713 /* 714 * If no submit, we are done. If submit->fence hasn't 715 * been signalled, then later submits are not signalled 716 * either, so we are also done. 717 */ 718 if (submit && dma_fence_is_signaled(submit->hw_fence)) { 719 retire_submit(gpu, ring, submit); 720 } else { 721 break; 722 } 723 } 724 } 725 726 wake_up_all(&gpu->retire_event); 727 } 728 729 static void retire_worker(struct kthread_work *work) 730 { 731 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 732 733 retire_submits(gpu); 734 } 735 736 /* call from irq handler to schedule work to retire bo's */ 737 void msm_gpu_retire(struct msm_gpu *gpu) 738 { 739 int i; 740 741 for (i = 0; i < gpu->nr_rings; i++) 742 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); 743 744 kthread_queue_work(gpu->worker, &gpu->retire_work); 745 update_sw_cntrs(gpu); 746 } 747 748 /* add bo's to gpu's ring, and kick gpu: */ 749 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 750 { 751 struct drm_device *dev = gpu->dev; 752 struct msm_drm_private *priv = dev->dev_private; 753 struct msm_ringbuffer *ring = submit->ring; 754 unsigned long flags; 755 756 WARN_ON(!mutex_is_locked(&gpu->lock)); 757 758 pm_runtime_get_sync(&gpu->pdev->dev); 759 760 msm_gpu_hw_init(gpu); 761 762 submit->seqno = submit->hw_fence->seqno; 763 764 msm_rd_dump_submit(priv->rd, submit, NULL); 765 766 update_sw_cntrs(gpu); 767 768 /* 769 * ring->submits holds a ref to the submit, to deal with the case 770 * that a submit completes before msm_ioctl_gem_submit() returns. 771 */ 772 msm_gem_submit_get(submit); 773 774 spin_lock_irqsave(&ring->submit_lock, flags); 775 list_add_tail(&submit->node, &ring->submits); 776 spin_unlock_irqrestore(&ring->submit_lock, flags); 777 778 /* Update devfreq on transition from idle->active: */ 779 mutex_lock(&gpu->active_lock); 780 if (!gpu->active_submits) { 781 pm_runtime_get(&gpu->pdev->dev); 782 msm_devfreq_active(gpu); 783 } 784 gpu->active_submits++; 785 mutex_unlock(&gpu->active_lock); 786 787 gpu->funcs->submit(gpu, submit); 788 gpu->cur_ctx_seqno = submit->queue->ctx->seqno; 789 790 pm_runtime_put(&gpu->pdev->dev); 791 hangcheck_timer_reset(gpu); 792 } 793 794 /* 795 * Init/Cleanup: 796 */ 797 798 static irqreturn_t irq_handler(int irq, void *data) 799 { 800 struct msm_gpu *gpu = data; 801 return gpu->funcs->irq(gpu); 802 } 803 804 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 805 { 806 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); 807 808 if (ret < 1) { 809 gpu->nr_clocks = 0; 810 return ret; 811 } 812 813 gpu->nr_clocks = ret; 814 815 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 816 gpu->nr_clocks, "core"); 817 818 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 819 gpu->nr_clocks, "rbbmtimer"); 820 821 return 0; 822 } 823 824 /* Return a new address space for a msm_drm_private instance */ 825 struct msm_gem_address_space * 826 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) 827 { 828 struct msm_gem_address_space *aspace = NULL; 829 if (!gpu) 830 return NULL; 831 832 /* 833 * If the target doesn't support private address spaces then return 834 * the global one 835 */ 836 if (gpu->funcs->create_private_address_space) { 837 aspace = gpu->funcs->create_private_address_space(gpu); 838 if (!IS_ERR(aspace)) 839 aspace->pid = get_pid(task_pid(task)); 840 } 841 842 if (IS_ERR_OR_NULL(aspace)) 843 aspace = msm_gem_address_space_get(gpu->aspace); 844 845 return aspace; 846 } 847 848 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 849 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 850 const char *name, struct msm_gpu_config *config) 851 { 852 struct msm_drm_private *priv = drm->dev_private; 853 int i, ret, nr_rings = config->nr_rings; 854 void *memptrs; 855 uint64_t memptrs_iova; 856 857 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 858 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 859 860 gpu->dev = drm; 861 gpu->funcs = funcs; 862 gpu->name = name; 863 864 gpu->worker = kthread_create_worker(0, "gpu-worker"); 865 if (IS_ERR(gpu->worker)) { 866 ret = PTR_ERR(gpu->worker); 867 gpu->worker = NULL; 868 goto fail; 869 } 870 871 sched_set_fifo_low(gpu->worker->task); 872 873 mutex_init(&gpu->active_lock); 874 mutex_init(&gpu->lock); 875 init_waitqueue_head(&gpu->retire_event); 876 kthread_init_work(&gpu->retire_work, retire_worker); 877 kthread_init_work(&gpu->recover_work, recover_worker); 878 kthread_init_work(&gpu->fault_work, fault_worker); 879 880 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 881 882 /* 883 * If progress detection is supported, halve the hangcheck timer 884 * duration, as it takes two iterations of the hangcheck handler 885 * to detect a hang. 886 */ 887 if (funcs->progress) 888 priv->hangcheck_period /= 2; 889 890 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 891 892 spin_lock_init(&gpu->perf_lock); 893 894 895 /* Map registers: */ 896 gpu->mmio = msm_ioremap(pdev, config->ioname); 897 if (IS_ERR(gpu->mmio)) { 898 ret = PTR_ERR(gpu->mmio); 899 goto fail; 900 } 901 902 /* Get Interrupt: */ 903 gpu->irq = platform_get_irq(pdev, 0); 904 if (gpu->irq < 0) { 905 ret = gpu->irq; 906 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret); 907 goto fail; 908 } 909 910 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 911 IRQF_TRIGGER_HIGH, "gpu-irq", gpu); 912 if (ret) { 913 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 914 goto fail; 915 } 916 917 ret = get_clocks(pdev, gpu); 918 if (ret) 919 goto fail; 920 921 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 922 DBG("ebi1_clk: %p", gpu->ebi1_clk); 923 if (IS_ERR(gpu->ebi1_clk)) 924 gpu->ebi1_clk = NULL; 925 926 /* Acquire regulators: */ 927 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 928 DBG("gpu_reg: %p", gpu->gpu_reg); 929 if (IS_ERR(gpu->gpu_reg)) 930 gpu->gpu_reg = NULL; 931 932 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 933 DBG("gpu_cx: %p", gpu->gpu_cx); 934 if (IS_ERR(gpu->gpu_cx)) 935 gpu->gpu_cx = NULL; 936 937 gpu->pdev = pdev; 938 platform_set_drvdata(pdev, &gpu->adreno_smmu); 939 940 msm_devfreq_init(gpu); 941 942 943 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev); 944 945 if (gpu->aspace == NULL) 946 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); 947 else if (IS_ERR(gpu->aspace)) { 948 ret = PTR_ERR(gpu->aspace); 949 goto fail; 950 } 951 952 memptrs = msm_gem_kernel_new(drm, 953 sizeof(struct msm_rbmemptrs) * nr_rings, 954 check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo, 955 &memptrs_iova); 956 957 if (IS_ERR(memptrs)) { 958 ret = PTR_ERR(memptrs); 959 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); 960 goto fail; 961 } 962 963 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); 964 965 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 966 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 967 ARRAY_SIZE(gpu->rb)); 968 nr_rings = ARRAY_SIZE(gpu->rb); 969 } 970 971 /* Create ringbuffer(s): */ 972 for (i = 0; i < nr_rings; i++) { 973 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 974 975 if (IS_ERR(gpu->rb[i])) { 976 ret = PTR_ERR(gpu->rb[i]); 977 DRM_DEV_ERROR(drm->dev, 978 "could not create ringbuffer %d: %d\n", i, ret); 979 goto fail; 980 } 981 982 memptrs += sizeof(struct msm_rbmemptrs); 983 memptrs_iova += sizeof(struct msm_rbmemptrs); 984 } 985 986 gpu->nr_rings = nr_rings; 987 988 refcount_set(&gpu->sysprof_active, 1); 989 990 return 0; 991 992 fail: 993 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 994 msm_ringbuffer_destroy(gpu->rb[i]); 995 gpu->rb[i] = NULL; 996 } 997 998 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace); 999 1000 platform_set_drvdata(pdev, NULL); 1001 return ret; 1002 } 1003 1004 void msm_gpu_cleanup(struct msm_gpu *gpu) 1005 { 1006 int i; 1007 1008 DBG("%s", gpu->name); 1009 1010 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 1011 msm_ringbuffer_destroy(gpu->rb[i]); 1012 gpu->rb[i] = NULL; 1013 } 1014 1015 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace); 1016 1017 if (!IS_ERR_OR_NULL(gpu->aspace)) { 1018 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu); 1019 msm_gem_address_space_put(gpu->aspace); 1020 } 1021 1022 if (gpu->worker) { 1023 kthread_destroy_worker(gpu->worker); 1024 } 1025 1026 msm_devfreq_cleanup(gpu); 1027 1028 platform_set_drvdata(gpu->pdev, NULL); 1029 } 1030