1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "msm_gpu.h" 8 #include "msm_gem.h" 9 #include "msm_mmu.h" 10 #include "msm_fence.h" 11 #include "msm_gpu_trace.h" 12 #include "adreno/adreno_gpu.h" 13 14 #include <generated/utsrelease.h> 15 #include <linux/string_helpers.h> 16 #include <linux/devcoredump.h> 17 #include <linux/sched/task.h> 18 19 /* 20 * Power Management: 21 */ 22 23 static int enable_pwrrail(struct msm_gpu *gpu) 24 { 25 struct drm_device *dev = gpu->dev; 26 int ret = 0; 27 28 if (gpu->gpu_reg) { 29 ret = regulator_enable(gpu->gpu_reg); 30 if (ret) { 31 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 32 return ret; 33 } 34 } 35 36 if (gpu->gpu_cx) { 37 ret = regulator_enable(gpu->gpu_cx); 38 if (ret) { 39 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 40 return ret; 41 } 42 } 43 44 return 0; 45 } 46 47 static int disable_pwrrail(struct msm_gpu *gpu) 48 { 49 if (gpu->gpu_cx) 50 regulator_disable(gpu->gpu_cx); 51 if (gpu->gpu_reg) 52 regulator_disable(gpu->gpu_reg); 53 return 0; 54 } 55 56 static int enable_clk(struct msm_gpu *gpu) 57 { 58 if (gpu->core_clk && gpu->fast_rate) 59 clk_set_rate(gpu->core_clk, gpu->fast_rate); 60 61 /* Set the RBBM timer rate to 19.2Mhz */ 62 if (gpu->rbbmtimer_clk) 63 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 64 65 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 66 } 67 68 static int disable_clk(struct msm_gpu *gpu) 69 { 70 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 71 72 /* 73 * Set the clock to a deliberately low rate. On older targets the clock 74 * speed had to be non zero to avoid problems. On newer targets this 75 * will be rounded down to zero anyway so it all works out. 76 */ 77 if (gpu->core_clk) 78 clk_set_rate(gpu->core_clk, 27000000); 79 80 if (gpu->rbbmtimer_clk) 81 clk_set_rate(gpu->rbbmtimer_clk, 0); 82 83 return 0; 84 } 85 86 static int enable_axi(struct msm_gpu *gpu) 87 { 88 return clk_prepare_enable(gpu->ebi1_clk); 89 } 90 91 static int disable_axi(struct msm_gpu *gpu) 92 { 93 clk_disable_unprepare(gpu->ebi1_clk); 94 return 0; 95 } 96 97 int msm_gpu_pm_resume(struct msm_gpu *gpu) 98 { 99 int ret; 100 101 DBG("%s", gpu->name); 102 trace_msm_gpu_resume(0); 103 104 ret = enable_pwrrail(gpu); 105 if (ret) 106 return ret; 107 108 ret = enable_clk(gpu); 109 if (ret) 110 return ret; 111 112 ret = enable_axi(gpu); 113 if (ret) 114 return ret; 115 116 msm_devfreq_resume(gpu); 117 118 gpu->needs_hw_init = true; 119 120 return 0; 121 } 122 123 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 124 { 125 int ret; 126 127 DBG("%s", gpu->name); 128 trace_msm_gpu_suspend(0); 129 130 msm_devfreq_suspend(gpu); 131 132 ret = disable_axi(gpu); 133 if (ret) 134 return ret; 135 136 ret = disable_clk(gpu); 137 if (ret) 138 return ret; 139 140 ret = disable_pwrrail(gpu); 141 if (ret) 142 return ret; 143 144 gpu->suspend_count++; 145 146 return 0; 147 } 148 149 int msm_gpu_hw_init(struct msm_gpu *gpu) 150 { 151 int ret; 152 153 WARN_ON(!mutex_is_locked(&gpu->lock)); 154 155 if (!gpu->needs_hw_init) 156 return 0; 157 158 disable_irq(gpu->irq); 159 ret = gpu->funcs->hw_init(gpu); 160 if (!ret) 161 gpu->needs_hw_init = false; 162 enable_irq(gpu->irq); 163 164 return ret; 165 } 166 167 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 168 uint32_t fence) 169 { 170 struct msm_gem_submit *submit; 171 unsigned long flags; 172 173 spin_lock_irqsave(&ring->submit_lock, flags); 174 list_for_each_entry(submit, &ring->submits, node) { 175 if (fence_after(submit->seqno, fence)) 176 break; 177 178 msm_update_fence(submit->ring->fctx, 179 submit->hw_fence->seqno); 180 dma_fence_signal(submit->hw_fence); 181 } 182 spin_unlock_irqrestore(&ring->submit_lock, flags); 183 } 184 185 #ifdef CONFIG_DEV_COREDUMP 186 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 187 size_t count, void *data, size_t datalen) 188 { 189 struct msm_gpu *gpu = data; 190 struct drm_print_iterator iter; 191 struct drm_printer p; 192 struct msm_gpu_state *state; 193 194 state = msm_gpu_crashstate_get(gpu); 195 if (!state) 196 return 0; 197 198 iter.data = buffer; 199 iter.offset = 0; 200 iter.start = offset; 201 iter.remain = count; 202 203 p = drm_coredump_printer(&iter); 204 205 drm_printf(&p, "---\n"); 206 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 207 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 208 drm_printf(&p, "time: %lld.%09ld\n", 209 state->time.tv_sec, state->time.tv_nsec); 210 if (state->comm) 211 drm_printf(&p, "comm: %s\n", state->comm); 212 if (state->cmd) 213 drm_printf(&p, "cmdline: %s\n", state->cmd); 214 215 gpu->funcs->show(gpu, state, &p); 216 217 msm_gpu_crashstate_put(gpu); 218 219 return count - iter.remain; 220 } 221 222 static void msm_gpu_devcoredump_free(void *data) 223 { 224 struct msm_gpu *gpu = data; 225 226 msm_gpu_crashstate_put(gpu); 227 } 228 229 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 230 struct msm_gem_object *obj, u64 iova, u32 flags) 231 { 232 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 233 234 /* Don't record write only objects */ 235 state_bo->size = obj->base.size; 236 state_bo->iova = iova; 237 238 /* Only store data for non imported buffer objects marked for read */ 239 if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) { 240 void *ptr; 241 242 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); 243 if (!state_bo->data) 244 goto out; 245 246 msm_gem_lock(&obj->base); 247 ptr = msm_gem_get_vaddr_active(&obj->base); 248 msm_gem_unlock(&obj->base); 249 if (IS_ERR(ptr)) { 250 kvfree(state_bo->data); 251 state_bo->data = NULL; 252 goto out; 253 } 254 255 memcpy(state_bo->data, ptr, obj->base.size); 256 msm_gem_put_vaddr(&obj->base); 257 } 258 out: 259 state->nr_bos++; 260 } 261 262 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 263 struct msm_gem_submit *submit, char *comm, char *cmd) 264 { 265 struct msm_gpu_state *state; 266 267 /* Check if the target supports capturing crash state */ 268 if (!gpu->funcs->gpu_state_get) 269 return; 270 271 /* Only save one crash state at a time */ 272 if (gpu->crashstate) 273 return; 274 275 state = gpu->funcs->gpu_state_get(gpu); 276 if (IS_ERR_OR_NULL(state)) 277 return; 278 279 /* Fill in the additional crash state information */ 280 state->comm = kstrdup(comm, GFP_KERNEL); 281 state->cmd = kstrdup(cmd, GFP_KERNEL); 282 state->fault_info = gpu->fault_info; 283 284 if (submit) { 285 int i, nr = 0; 286 287 /* count # of buffers to dump: */ 288 for (i = 0; i < submit->nr_bos; i++) 289 if (should_dump(submit, i)) 290 nr++; 291 /* always dump cmd bo's, but don't double count them: */ 292 for (i = 0; i < submit->nr_cmds; i++) 293 if (!should_dump(submit, submit->cmd[i].idx)) 294 nr++; 295 296 state->bos = kcalloc(nr, 297 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 298 299 for (i = 0; state->bos && i < submit->nr_bos; i++) { 300 if (should_dump(submit, i)) { 301 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj, 302 submit->bos[i].iova, submit->bos[i].flags); 303 } 304 } 305 306 for (i = 0; state->bos && i < submit->nr_cmds; i++) { 307 int idx = submit->cmd[i].idx; 308 309 if (!should_dump(submit, submit->cmd[i].idx)) { 310 msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj, 311 submit->bos[idx].iova, submit->bos[idx].flags); 312 } 313 } 314 } 315 316 /* Set the active crash state to be dumped on failure */ 317 gpu->crashstate = state; 318 319 /* FIXME: Release the crashstate if this errors out? */ 320 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 321 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 322 } 323 #else 324 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 325 struct msm_gem_submit *submit, char *comm, char *cmd) 326 { 327 } 328 #endif 329 330 /* 331 * Hangcheck detection for locked gpu: 332 */ 333 334 static struct msm_gem_submit * 335 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 336 { 337 struct msm_gem_submit *submit; 338 unsigned long flags; 339 340 spin_lock_irqsave(&ring->submit_lock, flags); 341 list_for_each_entry(submit, &ring->submits, node) { 342 if (submit->seqno == fence) { 343 spin_unlock_irqrestore(&ring->submit_lock, flags); 344 return submit; 345 } 346 } 347 spin_unlock_irqrestore(&ring->submit_lock, flags); 348 349 return NULL; 350 } 351 352 static void retire_submits(struct msm_gpu *gpu); 353 354 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd) 355 { 356 struct msm_file_private *ctx = submit->queue->ctx; 357 struct task_struct *task; 358 359 /* Note that kstrdup will return NULL if argument is NULL: */ 360 *comm = kstrdup(ctx->comm, GFP_KERNEL); 361 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL); 362 363 task = get_pid_task(submit->pid, PIDTYPE_PID); 364 if (!task) 365 return; 366 367 if (!*comm) 368 *comm = kstrdup(task->comm, GFP_KERNEL); 369 370 if (!*cmd) 371 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 372 373 put_task_struct(task); 374 } 375 376 static void recover_worker(struct kthread_work *work) 377 { 378 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 379 struct drm_device *dev = gpu->dev; 380 struct msm_drm_private *priv = dev->dev_private; 381 struct msm_gem_submit *submit; 382 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 383 char *comm = NULL, *cmd = NULL; 384 int i; 385 386 mutex_lock(&gpu->lock); 387 388 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); 389 390 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 391 if (submit) { 392 /* Increment the fault counts */ 393 submit->queue->faults++; 394 if (submit->aspace) 395 submit->aspace->faults++; 396 397 get_comm_cmdline(submit, &comm, &cmd); 398 399 if (comm && cmd) { 400 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", 401 gpu->name, comm, cmd); 402 403 msm_rd_dump_submit(priv->hangrd, submit, 404 "offending task: %s (%s)", comm, cmd); 405 } else { 406 msm_rd_dump_submit(priv->hangrd, submit, NULL); 407 } 408 } else { 409 /* 410 * We couldn't attribute this fault to any particular context, 411 * so increment the global fault count instead. 412 */ 413 gpu->global_faults++; 414 } 415 416 /* Record the crash state */ 417 pm_runtime_get_sync(&gpu->pdev->dev); 418 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); 419 pm_runtime_put_sync(&gpu->pdev->dev); 420 421 kfree(cmd); 422 kfree(comm); 423 424 /* 425 * Update all the rings with the latest and greatest fence.. this 426 * needs to happen after msm_rd_dump_submit() to ensure that the 427 * bo's referenced by the offending submit are still around. 428 */ 429 for (i = 0; i < gpu->nr_rings; i++) { 430 struct msm_ringbuffer *ring = gpu->rb[i]; 431 432 uint32_t fence = ring->memptrs->fence; 433 434 /* 435 * For the current (faulting?) ring/submit advance the fence by 436 * one more to clear the faulting submit 437 */ 438 if (ring == cur_ring) 439 fence++; 440 441 update_fences(gpu, ring, fence); 442 } 443 444 if (msm_gpu_active(gpu)) { 445 /* retire completed submits, plus the one that hung: */ 446 retire_submits(gpu); 447 448 pm_runtime_get_sync(&gpu->pdev->dev); 449 gpu->funcs->recover(gpu); 450 pm_runtime_put_sync(&gpu->pdev->dev); 451 452 /* 453 * Replay all remaining submits starting with highest priority 454 * ring 455 */ 456 for (i = 0; i < gpu->nr_rings; i++) { 457 struct msm_ringbuffer *ring = gpu->rb[i]; 458 unsigned long flags; 459 460 spin_lock_irqsave(&ring->submit_lock, flags); 461 list_for_each_entry(submit, &ring->submits, node) 462 gpu->funcs->submit(gpu, submit); 463 spin_unlock_irqrestore(&ring->submit_lock, flags); 464 } 465 } 466 467 mutex_unlock(&gpu->lock); 468 469 msm_gpu_retire(gpu); 470 } 471 472 static void fault_worker(struct kthread_work *work) 473 { 474 struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work); 475 struct msm_gem_submit *submit; 476 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 477 char *comm = NULL, *cmd = NULL; 478 479 mutex_lock(&gpu->lock); 480 481 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 482 if (submit && submit->fault_dumped) 483 goto resume_smmu; 484 485 if (submit) { 486 get_comm_cmdline(submit, &comm, &cmd); 487 488 /* 489 * When we get GPU iova faults, we can get 1000s of them, 490 * but we really only want to log the first one. 491 */ 492 submit->fault_dumped = true; 493 } 494 495 /* Record the crash state */ 496 pm_runtime_get_sync(&gpu->pdev->dev); 497 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); 498 pm_runtime_put_sync(&gpu->pdev->dev); 499 500 kfree(cmd); 501 kfree(comm); 502 503 resume_smmu: 504 memset(&gpu->fault_info, 0, sizeof(gpu->fault_info)); 505 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); 506 507 mutex_unlock(&gpu->lock); 508 } 509 510 static void hangcheck_timer_reset(struct msm_gpu *gpu) 511 { 512 struct msm_drm_private *priv = gpu->dev->dev_private; 513 mod_timer(&gpu->hangcheck_timer, 514 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period))); 515 } 516 517 static void hangcheck_handler(struct timer_list *t) 518 { 519 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); 520 struct drm_device *dev = gpu->dev; 521 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 522 uint32_t fence = ring->memptrs->fence; 523 524 if (fence != ring->hangcheck_fence) { 525 /* some progress has been made.. ya! */ 526 ring->hangcheck_fence = fence; 527 } else if (fence_before(fence, ring->fctx->last_fence)) { 528 /* no progress and not done.. hung! */ 529 ring->hangcheck_fence = fence; 530 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 531 gpu->name, ring->id); 532 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", 533 gpu->name, fence); 534 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", 535 gpu->name, ring->fctx->last_fence); 536 537 kthread_queue_work(gpu->worker, &gpu->recover_work); 538 } 539 540 /* if still more pending work, reset the hangcheck timer: */ 541 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence)) 542 hangcheck_timer_reset(gpu); 543 544 /* workaround for missing irq: */ 545 msm_gpu_retire(gpu); 546 } 547 548 /* 549 * Performance Counters: 550 */ 551 552 /* called under perf_lock */ 553 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 554 { 555 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 556 int i, n = min(ncntrs, gpu->num_perfcntrs); 557 558 /* read current values: */ 559 for (i = 0; i < gpu->num_perfcntrs; i++) 560 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 561 562 /* update cntrs: */ 563 for (i = 0; i < n; i++) 564 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 565 566 /* save current values: */ 567 for (i = 0; i < gpu->num_perfcntrs; i++) 568 gpu->last_cntrs[i] = current_cntrs[i]; 569 570 return n; 571 } 572 573 static void update_sw_cntrs(struct msm_gpu *gpu) 574 { 575 ktime_t time; 576 uint32_t elapsed; 577 unsigned long flags; 578 579 spin_lock_irqsave(&gpu->perf_lock, flags); 580 if (!gpu->perfcntr_active) 581 goto out; 582 583 time = ktime_get(); 584 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 585 586 gpu->totaltime += elapsed; 587 if (gpu->last_sample.active) 588 gpu->activetime += elapsed; 589 590 gpu->last_sample.active = msm_gpu_active(gpu); 591 gpu->last_sample.time = time; 592 593 out: 594 spin_unlock_irqrestore(&gpu->perf_lock, flags); 595 } 596 597 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 598 { 599 unsigned long flags; 600 601 pm_runtime_get_sync(&gpu->pdev->dev); 602 603 spin_lock_irqsave(&gpu->perf_lock, flags); 604 /* we could dynamically enable/disable perfcntr registers too.. */ 605 gpu->last_sample.active = msm_gpu_active(gpu); 606 gpu->last_sample.time = ktime_get(); 607 gpu->activetime = gpu->totaltime = 0; 608 gpu->perfcntr_active = true; 609 update_hw_cntrs(gpu, 0, NULL); 610 spin_unlock_irqrestore(&gpu->perf_lock, flags); 611 } 612 613 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 614 { 615 gpu->perfcntr_active = false; 616 pm_runtime_put_sync(&gpu->pdev->dev); 617 } 618 619 /* returns -errno or # of cntrs sampled */ 620 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 621 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 622 { 623 unsigned long flags; 624 int ret; 625 626 spin_lock_irqsave(&gpu->perf_lock, flags); 627 628 if (!gpu->perfcntr_active) { 629 ret = -EINVAL; 630 goto out; 631 } 632 633 *activetime = gpu->activetime; 634 *totaltime = gpu->totaltime; 635 636 gpu->activetime = gpu->totaltime = 0; 637 638 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 639 640 out: 641 spin_unlock_irqrestore(&gpu->perf_lock, flags); 642 643 return ret; 644 } 645 646 /* 647 * Cmdstream submission/retirement: 648 */ 649 650 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 651 struct msm_gem_submit *submit) 652 { 653 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 654 volatile struct msm_gpu_submit_stats *stats; 655 u64 elapsed, clock = 0; 656 unsigned long flags; 657 658 stats = &ring->memptrs->stats[index]; 659 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ 660 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; 661 do_div(elapsed, 192); 662 663 /* Calculate the clock frequency from the number of CP cycles */ 664 if (elapsed) { 665 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000; 666 do_div(clock, elapsed); 667 } 668 669 trace_msm_gpu_submit_retired(submit, elapsed, clock, 670 stats->alwayson_start, stats->alwayson_end); 671 672 msm_submit_retire(submit); 673 674 pm_runtime_mark_last_busy(&gpu->pdev->dev); 675 pm_runtime_put_autosuspend(&gpu->pdev->dev); 676 677 spin_lock_irqsave(&ring->submit_lock, flags); 678 list_del(&submit->node); 679 spin_unlock_irqrestore(&ring->submit_lock, flags); 680 681 /* Update devfreq on transition from active->idle: */ 682 mutex_lock(&gpu->active_lock); 683 gpu->active_submits--; 684 WARN_ON(gpu->active_submits < 0); 685 if (!gpu->active_submits) 686 msm_devfreq_idle(gpu); 687 mutex_unlock(&gpu->active_lock); 688 689 msm_gem_submit_put(submit); 690 } 691 692 static void retire_submits(struct msm_gpu *gpu) 693 { 694 int i; 695 696 /* Retire the commits starting with highest priority */ 697 for (i = 0; i < gpu->nr_rings; i++) { 698 struct msm_ringbuffer *ring = gpu->rb[i]; 699 700 while (true) { 701 struct msm_gem_submit *submit = NULL; 702 unsigned long flags; 703 704 spin_lock_irqsave(&ring->submit_lock, flags); 705 submit = list_first_entry_or_null(&ring->submits, 706 struct msm_gem_submit, node); 707 spin_unlock_irqrestore(&ring->submit_lock, flags); 708 709 /* 710 * If no submit, we are done. If submit->fence hasn't 711 * been signalled, then later submits are not signalled 712 * either, so we are also done. 713 */ 714 if (submit && dma_fence_is_signaled(submit->hw_fence)) { 715 retire_submit(gpu, ring, submit); 716 } else { 717 break; 718 } 719 } 720 } 721 722 wake_up_all(&gpu->retire_event); 723 } 724 725 static void retire_worker(struct kthread_work *work) 726 { 727 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 728 729 retire_submits(gpu); 730 } 731 732 /* call from irq handler to schedule work to retire bo's */ 733 void msm_gpu_retire(struct msm_gpu *gpu) 734 { 735 int i; 736 737 for (i = 0; i < gpu->nr_rings; i++) 738 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); 739 740 kthread_queue_work(gpu->worker, &gpu->retire_work); 741 update_sw_cntrs(gpu); 742 } 743 744 /* add bo's to gpu's ring, and kick gpu: */ 745 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 746 { 747 struct drm_device *dev = gpu->dev; 748 struct msm_drm_private *priv = dev->dev_private; 749 struct msm_ringbuffer *ring = submit->ring; 750 unsigned long flags; 751 752 WARN_ON(!mutex_is_locked(&gpu->lock)); 753 754 pm_runtime_get_sync(&gpu->pdev->dev); 755 756 msm_gpu_hw_init(gpu); 757 758 submit->seqno = submit->hw_fence->seqno; 759 760 msm_rd_dump_submit(priv->rd, submit, NULL); 761 762 update_sw_cntrs(gpu); 763 764 /* 765 * ring->submits holds a ref to the submit, to deal with the case 766 * that a submit completes before msm_ioctl_gem_submit() returns. 767 */ 768 msm_gem_submit_get(submit); 769 770 spin_lock_irqsave(&ring->submit_lock, flags); 771 list_add_tail(&submit->node, &ring->submits); 772 spin_unlock_irqrestore(&ring->submit_lock, flags); 773 774 /* Update devfreq on transition from idle->active: */ 775 mutex_lock(&gpu->active_lock); 776 if (!gpu->active_submits) 777 msm_devfreq_active(gpu); 778 gpu->active_submits++; 779 mutex_unlock(&gpu->active_lock); 780 781 gpu->funcs->submit(gpu, submit); 782 gpu->cur_ctx_seqno = submit->queue->ctx->seqno; 783 784 hangcheck_timer_reset(gpu); 785 } 786 787 /* 788 * Init/Cleanup: 789 */ 790 791 static irqreturn_t irq_handler(int irq, void *data) 792 { 793 struct msm_gpu *gpu = data; 794 return gpu->funcs->irq(gpu); 795 } 796 797 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 798 { 799 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); 800 801 if (ret < 1) { 802 gpu->nr_clocks = 0; 803 return ret; 804 } 805 806 gpu->nr_clocks = ret; 807 808 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 809 gpu->nr_clocks, "core"); 810 811 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 812 gpu->nr_clocks, "rbbmtimer"); 813 814 return 0; 815 } 816 817 /* Return a new address space for a msm_drm_private instance */ 818 struct msm_gem_address_space * 819 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) 820 { 821 struct msm_gem_address_space *aspace = NULL; 822 if (!gpu) 823 return NULL; 824 825 /* 826 * If the target doesn't support private address spaces then return 827 * the global one 828 */ 829 if (gpu->funcs->create_private_address_space) { 830 aspace = gpu->funcs->create_private_address_space(gpu); 831 if (!IS_ERR(aspace)) 832 aspace->pid = get_pid(task_pid(task)); 833 } 834 835 if (IS_ERR_OR_NULL(aspace)) 836 aspace = msm_gem_address_space_get(gpu->aspace); 837 838 return aspace; 839 } 840 841 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 842 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 843 const char *name, struct msm_gpu_config *config) 844 { 845 int i, ret, nr_rings = config->nr_rings; 846 void *memptrs; 847 uint64_t memptrs_iova; 848 849 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 850 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 851 852 gpu->dev = drm; 853 gpu->funcs = funcs; 854 gpu->name = name; 855 856 gpu->worker = kthread_create_worker(0, "gpu-worker"); 857 if (IS_ERR(gpu->worker)) { 858 ret = PTR_ERR(gpu->worker); 859 gpu->worker = NULL; 860 goto fail; 861 } 862 863 sched_set_fifo_low(gpu->worker->task); 864 865 INIT_LIST_HEAD(&gpu->active_list); 866 mutex_init(&gpu->active_lock); 867 mutex_init(&gpu->lock); 868 init_waitqueue_head(&gpu->retire_event); 869 kthread_init_work(&gpu->retire_work, retire_worker); 870 kthread_init_work(&gpu->recover_work, recover_worker); 871 kthread_init_work(&gpu->fault_work, fault_worker); 872 873 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 874 875 spin_lock_init(&gpu->perf_lock); 876 877 878 /* Map registers: */ 879 gpu->mmio = msm_ioremap(pdev, config->ioname); 880 if (IS_ERR(gpu->mmio)) { 881 ret = PTR_ERR(gpu->mmio); 882 goto fail; 883 } 884 885 /* Get Interrupt: */ 886 gpu->irq = platform_get_irq(pdev, 0); 887 if (gpu->irq < 0) { 888 ret = gpu->irq; 889 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret); 890 goto fail; 891 } 892 893 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 894 IRQF_TRIGGER_HIGH, "gpu-irq", gpu); 895 if (ret) { 896 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 897 goto fail; 898 } 899 900 ret = get_clocks(pdev, gpu); 901 if (ret) 902 goto fail; 903 904 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 905 DBG("ebi1_clk: %p", gpu->ebi1_clk); 906 if (IS_ERR(gpu->ebi1_clk)) 907 gpu->ebi1_clk = NULL; 908 909 /* Acquire regulators: */ 910 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 911 DBG("gpu_reg: %p", gpu->gpu_reg); 912 if (IS_ERR(gpu->gpu_reg)) 913 gpu->gpu_reg = NULL; 914 915 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 916 DBG("gpu_cx: %p", gpu->gpu_cx); 917 if (IS_ERR(gpu->gpu_cx)) 918 gpu->gpu_cx = NULL; 919 920 gpu->pdev = pdev; 921 platform_set_drvdata(pdev, &gpu->adreno_smmu); 922 923 msm_devfreq_init(gpu); 924 925 926 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev); 927 928 if (gpu->aspace == NULL) 929 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); 930 else if (IS_ERR(gpu->aspace)) { 931 ret = PTR_ERR(gpu->aspace); 932 goto fail; 933 } 934 935 memptrs = msm_gem_kernel_new(drm, 936 sizeof(struct msm_rbmemptrs) * nr_rings, 937 check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo, 938 &memptrs_iova); 939 940 if (IS_ERR(memptrs)) { 941 ret = PTR_ERR(memptrs); 942 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); 943 goto fail; 944 } 945 946 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); 947 948 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 949 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 950 ARRAY_SIZE(gpu->rb)); 951 nr_rings = ARRAY_SIZE(gpu->rb); 952 } 953 954 /* Create ringbuffer(s): */ 955 for (i = 0; i < nr_rings; i++) { 956 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 957 958 if (IS_ERR(gpu->rb[i])) { 959 ret = PTR_ERR(gpu->rb[i]); 960 DRM_DEV_ERROR(drm->dev, 961 "could not create ringbuffer %d: %d\n", i, ret); 962 goto fail; 963 } 964 965 memptrs += sizeof(struct msm_rbmemptrs); 966 memptrs_iova += sizeof(struct msm_rbmemptrs); 967 } 968 969 gpu->nr_rings = nr_rings; 970 971 refcount_set(&gpu->sysprof_active, 1); 972 973 return 0; 974 975 fail: 976 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 977 msm_ringbuffer_destroy(gpu->rb[i]); 978 gpu->rb[i] = NULL; 979 } 980 981 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace); 982 983 platform_set_drvdata(pdev, NULL); 984 return ret; 985 } 986 987 void msm_gpu_cleanup(struct msm_gpu *gpu) 988 { 989 int i; 990 991 DBG("%s", gpu->name); 992 993 WARN_ON(!list_empty(&gpu->active_list)); 994 995 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 996 msm_ringbuffer_destroy(gpu->rb[i]); 997 gpu->rb[i] = NULL; 998 } 999 1000 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace); 1001 1002 if (!IS_ERR_OR_NULL(gpu->aspace)) { 1003 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu); 1004 msm_gem_address_space_put(gpu->aspace); 1005 } 1006 1007 if (gpu->worker) { 1008 kthread_destroy_worker(gpu->worker); 1009 } 1010 1011 msm_devfreq_cleanup(gpu); 1012 } 1013