1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "msm_gpu.h" 19 #include "msm_gem.h" 20 #include "msm_mmu.h" 21 #include "msm_fence.h" 22 23 #include <generated/utsrelease.h> 24 #include <linux/string_helpers.h> 25 #include <linux/pm_opp.h> 26 #include <linux/devfreq.h> 27 #include <linux/devcoredump.h> 28 29 /* 30 * Power Management: 31 */ 32 33 static int msm_devfreq_target(struct device *dev, unsigned long *freq, 34 u32 flags) 35 { 36 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); 37 struct dev_pm_opp *opp; 38 39 opp = devfreq_recommended_opp(dev, freq, flags); 40 41 if (IS_ERR(opp)) 42 return PTR_ERR(opp); 43 44 if (gpu->funcs->gpu_set_freq) 45 gpu->funcs->gpu_set_freq(gpu, (u64)*freq); 46 else 47 clk_set_rate(gpu->core_clk, *freq); 48 49 dev_pm_opp_put(opp); 50 51 return 0; 52 } 53 54 static int msm_devfreq_get_dev_status(struct device *dev, 55 struct devfreq_dev_status *status) 56 { 57 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); 58 ktime_t time; 59 60 if (gpu->funcs->gpu_get_freq) 61 status->current_frequency = gpu->funcs->gpu_get_freq(gpu); 62 else 63 status->current_frequency = clk_get_rate(gpu->core_clk); 64 65 status->busy_time = gpu->funcs->gpu_busy(gpu); 66 67 time = ktime_get(); 68 status->total_time = ktime_us_delta(time, gpu->devfreq.time); 69 gpu->devfreq.time = time; 70 71 return 0; 72 } 73 74 static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) 75 { 76 struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); 77 78 if (gpu->funcs->gpu_get_freq) 79 *freq = gpu->funcs->gpu_get_freq(gpu); 80 else 81 *freq = clk_get_rate(gpu->core_clk); 82 83 return 0; 84 } 85 86 static struct devfreq_dev_profile msm_devfreq_profile = { 87 .polling_ms = 10, 88 .target = msm_devfreq_target, 89 .get_dev_status = msm_devfreq_get_dev_status, 90 .get_cur_freq = msm_devfreq_get_cur_freq, 91 }; 92 93 static void msm_devfreq_init(struct msm_gpu *gpu) 94 { 95 /* We need target support to do devfreq */ 96 if (!gpu->funcs->gpu_busy) 97 return; 98 99 msm_devfreq_profile.initial_freq = gpu->fast_rate; 100 101 /* 102 * Don't set the freq_table or max_state and let devfreq build the table 103 * from OPP 104 */ 105 106 gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev, 107 &msm_devfreq_profile, "simple_ondemand", NULL); 108 109 if (IS_ERR(gpu->devfreq.devfreq)) { 110 dev_err(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n"); 111 gpu->devfreq.devfreq = NULL; 112 } 113 114 devfreq_suspend_device(gpu->devfreq.devfreq); 115 } 116 117 static int enable_pwrrail(struct msm_gpu *gpu) 118 { 119 struct drm_device *dev = gpu->dev; 120 int ret = 0; 121 122 if (gpu->gpu_reg) { 123 ret = regulator_enable(gpu->gpu_reg); 124 if (ret) { 125 dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 126 return ret; 127 } 128 } 129 130 if (gpu->gpu_cx) { 131 ret = regulator_enable(gpu->gpu_cx); 132 if (ret) { 133 dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 134 return ret; 135 } 136 } 137 138 return 0; 139 } 140 141 static int disable_pwrrail(struct msm_gpu *gpu) 142 { 143 if (gpu->gpu_cx) 144 regulator_disable(gpu->gpu_cx); 145 if (gpu->gpu_reg) 146 regulator_disable(gpu->gpu_reg); 147 return 0; 148 } 149 150 static int enable_clk(struct msm_gpu *gpu) 151 { 152 if (gpu->core_clk && gpu->fast_rate) 153 clk_set_rate(gpu->core_clk, gpu->fast_rate); 154 155 /* Set the RBBM timer rate to 19.2Mhz */ 156 if (gpu->rbbmtimer_clk) 157 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 158 159 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 160 } 161 162 static int disable_clk(struct msm_gpu *gpu) 163 { 164 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 165 166 /* 167 * Set the clock to a deliberately low rate. On older targets the clock 168 * speed had to be non zero to avoid problems. On newer targets this 169 * will be rounded down to zero anyway so it all works out. 170 */ 171 if (gpu->core_clk) 172 clk_set_rate(gpu->core_clk, 27000000); 173 174 if (gpu->rbbmtimer_clk) 175 clk_set_rate(gpu->rbbmtimer_clk, 0); 176 177 return 0; 178 } 179 180 static int enable_axi(struct msm_gpu *gpu) 181 { 182 if (gpu->ebi1_clk) 183 clk_prepare_enable(gpu->ebi1_clk); 184 return 0; 185 } 186 187 static int disable_axi(struct msm_gpu *gpu) 188 { 189 if (gpu->ebi1_clk) 190 clk_disable_unprepare(gpu->ebi1_clk); 191 return 0; 192 } 193 194 void msm_gpu_resume_devfreq(struct msm_gpu *gpu) 195 { 196 gpu->devfreq.busy_cycles = 0; 197 gpu->devfreq.time = ktime_get(); 198 199 devfreq_resume_device(gpu->devfreq.devfreq); 200 } 201 202 int msm_gpu_pm_resume(struct msm_gpu *gpu) 203 { 204 int ret; 205 206 DBG("%s", gpu->name); 207 208 ret = enable_pwrrail(gpu); 209 if (ret) 210 return ret; 211 212 ret = enable_clk(gpu); 213 if (ret) 214 return ret; 215 216 ret = enable_axi(gpu); 217 if (ret) 218 return ret; 219 220 msm_gpu_resume_devfreq(gpu); 221 222 gpu->needs_hw_init = true; 223 224 return 0; 225 } 226 227 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 228 { 229 int ret; 230 231 DBG("%s", gpu->name); 232 233 devfreq_suspend_device(gpu->devfreq.devfreq); 234 235 ret = disable_axi(gpu); 236 if (ret) 237 return ret; 238 239 ret = disable_clk(gpu); 240 if (ret) 241 return ret; 242 243 ret = disable_pwrrail(gpu); 244 if (ret) 245 return ret; 246 247 return 0; 248 } 249 250 int msm_gpu_hw_init(struct msm_gpu *gpu) 251 { 252 int ret; 253 254 WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex)); 255 256 if (!gpu->needs_hw_init) 257 return 0; 258 259 disable_irq(gpu->irq); 260 ret = gpu->funcs->hw_init(gpu); 261 if (!ret) 262 gpu->needs_hw_init = false; 263 enable_irq(gpu->irq); 264 265 return ret; 266 } 267 268 #ifdef CONFIG_DEV_COREDUMP 269 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 270 size_t count, void *data, size_t datalen) 271 { 272 struct msm_gpu *gpu = data; 273 struct drm_print_iterator iter; 274 struct drm_printer p; 275 struct msm_gpu_state *state; 276 277 state = msm_gpu_crashstate_get(gpu); 278 if (!state) 279 return 0; 280 281 iter.data = buffer; 282 iter.offset = 0; 283 iter.start = offset; 284 iter.remain = count; 285 286 p = drm_coredump_printer(&iter); 287 288 drm_printf(&p, "---\n"); 289 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 290 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 291 drm_printf(&p, "time: %lld.%09ld\n", 292 state->time.tv_sec, state->time.tv_nsec); 293 if (state->comm) 294 drm_printf(&p, "comm: %s\n", state->comm); 295 if (state->cmd) 296 drm_printf(&p, "cmdline: %s\n", state->cmd); 297 298 gpu->funcs->show(gpu, state, &p); 299 300 msm_gpu_crashstate_put(gpu); 301 302 return count - iter.remain; 303 } 304 305 static void msm_gpu_devcoredump_free(void *data) 306 { 307 struct msm_gpu *gpu = data; 308 309 msm_gpu_crashstate_put(gpu); 310 } 311 312 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 313 struct msm_gem_object *obj, u64 iova, u32 flags) 314 { 315 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 316 317 /* Don't record write only objects */ 318 319 state_bo->size = obj->base.size; 320 state_bo->iova = iova; 321 322 /* Only store the data for buffer objects marked for read */ 323 if ((flags & MSM_SUBMIT_BO_READ)) { 324 void *ptr; 325 326 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); 327 if (!state_bo->data) 328 return; 329 330 ptr = msm_gem_get_vaddr_active(&obj->base); 331 if (IS_ERR(ptr)) { 332 kvfree(state_bo->data); 333 return; 334 } 335 336 memcpy(state_bo->data, ptr, obj->base.size); 337 msm_gem_put_vaddr(&obj->base); 338 } 339 340 state->nr_bos++; 341 } 342 343 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 344 struct msm_gem_submit *submit, char *comm, char *cmd) 345 { 346 struct msm_gpu_state *state; 347 348 /* Check if the target supports capturing crash state */ 349 if (!gpu->funcs->gpu_state_get) 350 return; 351 352 /* Only save one crash state at a time */ 353 if (gpu->crashstate) 354 return; 355 356 state = gpu->funcs->gpu_state_get(gpu); 357 if (IS_ERR_OR_NULL(state)) 358 return; 359 360 /* Fill in the additional crash state information */ 361 state->comm = kstrdup(comm, GFP_KERNEL); 362 state->cmd = kstrdup(cmd, GFP_KERNEL); 363 364 if (submit) { 365 int i; 366 367 state->bos = kcalloc(submit->nr_bos, 368 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 369 370 for (i = 0; state->bos && i < submit->nr_bos; i++) 371 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj, 372 submit->bos[i].iova, submit->bos[i].flags); 373 } 374 375 /* Set the active crash state to be dumped on failure */ 376 gpu->crashstate = state; 377 378 /* FIXME: Release the crashstate if this errors out? */ 379 dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 380 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 381 } 382 #else 383 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 384 struct msm_gem_submit *submit, char *comm, char *cmd) 385 { 386 } 387 #endif 388 389 /* 390 * Hangcheck detection for locked gpu: 391 */ 392 393 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 394 uint32_t fence) 395 { 396 struct msm_gem_submit *submit; 397 398 list_for_each_entry(submit, &ring->submits, node) { 399 if (submit->seqno > fence) 400 break; 401 402 msm_update_fence(submit->ring->fctx, 403 submit->fence->seqno); 404 } 405 } 406 407 static struct msm_gem_submit * 408 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 409 { 410 struct msm_gem_submit *submit; 411 412 WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex)); 413 414 list_for_each_entry(submit, &ring->submits, node) 415 if (submit->seqno == fence) 416 return submit; 417 418 return NULL; 419 } 420 421 static void retire_submits(struct msm_gpu *gpu); 422 423 static void recover_worker(struct work_struct *work) 424 { 425 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 426 struct drm_device *dev = gpu->dev; 427 struct msm_drm_private *priv = dev->dev_private; 428 struct msm_gem_submit *submit; 429 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 430 char *comm = NULL, *cmd = NULL; 431 int i; 432 433 mutex_lock(&dev->struct_mutex); 434 435 dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name); 436 437 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 438 if (submit) { 439 struct task_struct *task; 440 441 task = get_pid_task(submit->pid, PIDTYPE_PID); 442 if (task) { 443 comm = kstrdup(task->comm, GFP_KERNEL); 444 445 /* 446 * So slightly annoying, in other paths like 447 * mmap'ing gem buffers, mmap_sem is acquired 448 * before struct_mutex, which means we can't 449 * hold struct_mutex across the call to 450 * get_cmdline(). But submits are retired 451 * from the same in-order workqueue, so we can 452 * safely drop the lock here without worrying 453 * about the submit going away. 454 */ 455 mutex_unlock(&dev->struct_mutex); 456 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 457 put_task_struct(task); 458 mutex_lock(&dev->struct_mutex); 459 } 460 461 if (comm && cmd) { 462 dev_err(dev->dev, "%s: offending task: %s (%s)\n", 463 gpu->name, comm, cmd); 464 465 msm_rd_dump_submit(priv->hangrd, submit, 466 "offending task: %s (%s)", comm, cmd); 467 } else 468 msm_rd_dump_submit(priv->hangrd, submit, NULL); 469 } 470 471 /* Record the crash state */ 472 pm_runtime_get_sync(&gpu->pdev->dev); 473 msm_gpu_crashstate_capture(gpu, submit, comm, cmd); 474 pm_runtime_put_sync(&gpu->pdev->dev); 475 476 kfree(cmd); 477 kfree(comm); 478 479 /* 480 * Update all the rings with the latest and greatest fence.. this 481 * needs to happen after msm_rd_dump_submit() to ensure that the 482 * bo's referenced by the offending submit are still around. 483 */ 484 for (i = 0; i < gpu->nr_rings; i++) { 485 struct msm_ringbuffer *ring = gpu->rb[i]; 486 487 uint32_t fence = ring->memptrs->fence; 488 489 /* 490 * For the current (faulting?) ring/submit advance the fence by 491 * one more to clear the faulting submit 492 */ 493 if (ring == cur_ring) 494 fence++; 495 496 update_fences(gpu, ring, fence); 497 } 498 499 if (msm_gpu_active(gpu)) { 500 /* retire completed submits, plus the one that hung: */ 501 retire_submits(gpu); 502 503 pm_runtime_get_sync(&gpu->pdev->dev); 504 gpu->funcs->recover(gpu); 505 pm_runtime_put_sync(&gpu->pdev->dev); 506 507 /* 508 * Replay all remaining submits starting with highest priority 509 * ring 510 */ 511 for (i = 0; i < gpu->nr_rings; i++) { 512 struct msm_ringbuffer *ring = gpu->rb[i]; 513 514 list_for_each_entry(submit, &ring->submits, node) 515 gpu->funcs->submit(gpu, submit, NULL); 516 } 517 } 518 519 mutex_unlock(&dev->struct_mutex); 520 521 msm_gpu_retire(gpu); 522 } 523 524 static void hangcheck_timer_reset(struct msm_gpu *gpu) 525 { 526 DBG("%s", gpu->name); 527 mod_timer(&gpu->hangcheck_timer, 528 round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES)); 529 } 530 531 static void hangcheck_handler(struct timer_list *t) 532 { 533 struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); 534 struct drm_device *dev = gpu->dev; 535 struct msm_drm_private *priv = dev->dev_private; 536 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 537 uint32_t fence = ring->memptrs->fence; 538 539 if (fence != ring->hangcheck_fence) { 540 /* some progress has been made.. ya! */ 541 ring->hangcheck_fence = fence; 542 } else if (fence < ring->seqno) { 543 /* no progress and not done.. hung! */ 544 ring->hangcheck_fence = fence; 545 dev_err(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 546 gpu->name, ring->id); 547 dev_err(dev->dev, "%s: completed fence: %u\n", 548 gpu->name, fence); 549 dev_err(dev->dev, "%s: submitted fence: %u\n", 550 gpu->name, ring->seqno); 551 552 queue_work(priv->wq, &gpu->recover_work); 553 } 554 555 /* if still more pending work, reset the hangcheck timer: */ 556 if (ring->seqno > ring->hangcheck_fence) 557 hangcheck_timer_reset(gpu); 558 559 /* workaround for missing irq: */ 560 queue_work(priv->wq, &gpu->retire_work); 561 } 562 563 /* 564 * Performance Counters: 565 */ 566 567 /* called under perf_lock */ 568 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 569 { 570 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 571 int i, n = min(ncntrs, gpu->num_perfcntrs); 572 573 /* read current values: */ 574 for (i = 0; i < gpu->num_perfcntrs; i++) 575 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 576 577 /* update cntrs: */ 578 for (i = 0; i < n; i++) 579 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 580 581 /* save current values: */ 582 for (i = 0; i < gpu->num_perfcntrs; i++) 583 gpu->last_cntrs[i] = current_cntrs[i]; 584 585 return n; 586 } 587 588 static void update_sw_cntrs(struct msm_gpu *gpu) 589 { 590 ktime_t time; 591 uint32_t elapsed; 592 unsigned long flags; 593 594 spin_lock_irqsave(&gpu->perf_lock, flags); 595 if (!gpu->perfcntr_active) 596 goto out; 597 598 time = ktime_get(); 599 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 600 601 gpu->totaltime += elapsed; 602 if (gpu->last_sample.active) 603 gpu->activetime += elapsed; 604 605 gpu->last_sample.active = msm_gpu_active(gpu); 606 gpu->last_sample.time = time; 607 608 out: 609 spin_unlock_irqrestore(&gpu->perf_lock, flags); 610 } 611 612 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 613 { 614 unsigned long flags; 615 616 pm_runtime_get_sync(&gpu->pdev->dev); 617 618 spin_lock_irqsave(&gpu->perf_lock, flags); 619 /* we could dynamically enable/disable perfcntr registers too.. */ 620 gpu->last_sample.active = msm_gpu_active(gpu); 621 gpu->last_sample.time = ktime_get(); 622 gpu->activetime = gpu->totaltime = 0; 623 gpu->perfcntr_active = true; 624 update_hw_cntrs(gpu, 0, NULL); 625 spin_unlock_irqrestore(&gpu->perf_lock, flags); 626 } 627 628 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 629 { 630 gpu->perfcntr_active = false; 631 pm_runtime_put_sync(&gpu->pdev->dev); 632 } 633 634 /* returns -errno or # of cntrs sampled */ 635 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 636 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 637 { 638 unsigned long flags; 639 int ret; 640 641 spin_lock_irqsave(&gpu->perf_lock, flags); 642 643 if (!gpu->perfcntr_active) { 644 ret = -EINVAL; 645 goto out; 646 } 647 648 *activetime = gpu->activetime; 649 *totaltime = gpu->totaltime; 650 651 gpu->activetime = gpu->totaltime = 0; 652 653 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 654 655 out: 656 spin_unlock_irqrestore(&gpu->perf_lock, flags); 657 658 return ret; 659 } 660 661 /* 662 * Cmdstream submission/retirement: 663 */ 664 665 static void retire_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 666 { 667 int i; 668 669 for (i = 0; i < submit->nr_bos; i++) { 670 struct msm_gem_object *msm_obj = submit->bos[i].obj; 671 /* move to inactive: */ 672 msm_gem_move_to_inactive(&msm_obj->base); 673 msm_gem_put_iova(&msm_obj->base, gpu->aspace); 674 drm_gem_object_put(&msm_obj->base); 675 } 676 677 pm_runtime_mark_last_busy(&gpu->pdev->dev); 678 pm_runtime_put_autosuspend(&gpu->pdev->dev); 679 msm_gem_submit_free(submit); 680 } 681 682 static void retire_submits(struct msm_gpu *gpu) 683 { 684 struct drm_device *dev = gpu->dev; 685 struct msm_gem_submit *submit, *tmp; 686 int i; 687 688 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 689 690 /* Retire the commits starting with highest priority */ 691 for (i = 0; i < gpu->nr_rings; i++) { 692 struct msm_ringbuffer *ring = gpu->rb[i]; 693 694 list_for_each_entry_safe(submit, tmp, &ring->submits, node) { 695 if (dma_fence_is_signaled(submit->fence)) 696 retire_submit(gpu, submit); 697 } 698 } 699 } 700 701 static void retire_worker(struct work_struct *work) 702 { 703 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 704 struct drm_device *dev = gpu->dev; 705 int i; 706 707 for (i = 0; i < gpu->nr_rings; i++) 708 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); 709 710 mutex_lock(&dev->struct_mutex); 711 retire_submits(gpu); 712 mutex_unlock(&dev->struct_mutex); 713 } 714 715 /* call from irq handler to schedule work to retire bo's */ 716 void msm_gpu_retire(struct msm_gpu *gpu) 717 { 718 struct msm_drm_private *priv = gpu->dev->dev_private; 719 queue_work(priv->wq, &gpu->retire_work); 720 update_sw_cntrs(gpu); 721 } 722 723 /* add bo's to gpu's ring, and kick gpu: */ 724 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 725 struct msm_file_private *ctx) 726 { 727 struct drm_device *dev = gpu->dev; 728 struct msm_drm_private *priv = dev->dev_private; 729 struct msm_ringbuffer *ring = submit->ring; 730 int i; 731 732 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 733 734 pm_runtime_get_sync(&gpu->pdev->dev); 735 736 msm_gpu_hw_init(gpu); 737 738 submit->seqno = ++ring->seqno; 739 740 list_add_tail(&submit->node, &ring->submits); 741 742 msm_rd_dump_submit(priv->rd, submit, NULL); 743 744 update_sw_cntrs(gpu); 745 746 for (i = 0; i < submit->nr_bos; i++) { 747 struct msm_gem_object *msm_obj = submit->bos[i].obj; 748 uint64_t iova; 749 750 /* can't happen yet.. but when we add 2d support we'll have 751 * to deal w/ cross-ring synchronization: 752 */ 753 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); 754 755 /* submit takes a reference to the bo and iova until retired: */ 756 drm_gem_object_get(&msm_obj->base); 757 msm_gem_get_iova(&msm_obj->base, 758 submit->gpu->aspace, &iova); 759 760 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) 761 msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); 762 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ) 763 msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); 764 } 765 766 gpu->funcs->submit(gpu, submit, ctx); 767 priv->lastctx = ctx; 768 769 hangcheck_timer_reset(gpu); 770 } 771 772 /* 773 * Init/Cleanup: 774 */ 775 776 static irqreturn_t irq_handler(int irq, void *data) 777 { 778 struct msm_gpu *gpu = data; 779 return gpu->funcs->irq(gpu); 780 } 781 782 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 783 { 784 int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks); 785 786 if (ret < 1) { 787 gpu->nr_clocks = 0; 788 return ret; 789 } 790 791 gpu->nr_clocks = ret; 792 793 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 794 gpu->nr_clocks, "core"); 795 796 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 797 gpu->nr_clocks, "rbbmtimer"); 798 799 return 0; 800 } 801 802 static struct msm_gem_address_space * 803 msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, 804 uint64_t va_start, uint64_t va_end) 805 { 806 struct iommu_domain *iommu; 807 struct msm_gem_address_space *aspace; 808 int ret; 809 810 /* 811 * Setup IOMMU.. eventually we will (I think) do this once per context 812 * and have separate page tables per context. For now, to keep things 813 * simple and to get something working, just use a single address space: 814 */ 815 iommu = iommu_domain_alloc(&platform_bus_type); 816 if (!iommu) 817 return NULL; 818 819 iommu->geometry.aperture_start = va_start; 820 iommu->geometry.aperture_end = va_end; 821 822 dev_info(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); 823 824 aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu"); 825 if (IS_ERR(aspace)) { 826 dev_err(gpu->dev->dev, "failed to init iommu: %ld\n", 827 PTR_ERR(aspace)); 828 iommu_domain_free(iommu); 829 return ERR_CAST(aspace); 830 } 831 832 ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); 833 if (ret) { 834 msm_gem_address_space_put(aspace); 835 return ERR_PTR(ret); 836 } 837 838 return aspace; 839 } 840 841 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 842 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 843 const char *name, struct msm_gpu_config *config) 844 { 845 int i, ret, nr_rings = config->nr_rings; 846 void *memptrs; 847 uint64_t memptrs_iova; 848 849 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 850 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 851 852 gpu->dev = drm; 853 gpu->funcs = funcs; 854 gpu->name = name; 855 856 INIT_LIST_HEAD(&gpu->active_list); 857 INIT_WORK(&gpu->retire_work, retire_worker); 858 INIT_WORK(&gpu->recover_work, recover_worker); 859 860 861 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 862 863 spin_lock_init(&gpu->perf_lock); 864 865 866 /* Map registers: */ 867 gpu->mmio = msm_ioremap(pdev, config->ioname, name); 868 if (IS_ERR(gpu->mmio)) { 869 ret = PTR_ERR(gpu->mmio); 870 goto fail; 871 } 872 873 /* Get Interrupt: */ 874 gpu->irq = platform_get_irq_byname(pdev, config->irqname); 875 if (gpu->irq < 0) { 876 ret = gpu->irq; 877 dev_err(drm->dev, "failed to get irq: %d\n", ret); 878 goto fail; 879 } 880 881 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 882 IRQF_TRIGGER_HIGH, gpu->name, gpu); 883 if (ret) { 884 dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 885 goto fail; 886 } 887 888 ret = get_clocks(pdev, gpu); 889 if (ret) 890 goto fail; 891 892 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 893 DBG("ebi1_clk: %p", gpu->ebi1_clk); 894 if (IS_ERR(gpu->ebi1_clk)) 895 gpu->ebi1_clk = NULL; 896 897 /* Acquire regulators: */ 898 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 899 DBG("gpu_reg: %p", gpu->gpu_reg); 900 if (IS_ERR(gpu->gpu_reg)) 901 gpu->gpu_reg = NULL; 902 903 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 904 DBG("gpu_cx: %p", gpu->gpu_cx); 905 if (IS_ERR(gpu->gpu_cx)) 906 gpu->gpu_cx = NULL; 907 908 gpu->pdev = pdev; 909 platform_set_drvdata(pdev, gpu); 910 911 msm_devfreq_init(gpu); 912 913 gpu->aspace = msm_gpu_create_address_space(gpu, pdev, 914 config->va_start, config->va_end); 915 916 if (gpu->aspace == NULL) 917 dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); 918 else if (IS_ERR(gpu->aspace)) { 919 ret = PTR_ERR(gpu->aspace); 920 goto fail; 921 } 922 923 memptrs = msm_gem_kernel_new(drm, sizeof(*gpu->memptrs_bo), 924 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, 925 &memptrs_iova); 926 927 if (IS_ERR(memptrs)) { 928 ret = PTR_ERR(memptrs); 929 dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); 930 goto fail; 931 } 932 933 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 934 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 935 ARRAY_SIZE(gpu->rb)); 936 nr_rings = ARRAY_SIZE(gpu->rb); 937 } 938 939 /* Create ringbuffer(s): */ 940 for (i = 0; i < nr_rings; i++) { 941 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 942 943 if (IS_ERR(gpu->rb[i])) { 944 ret = PTR_ERR(gpu->rb[i]); 945 dev_err(drm->dev, 946 "could not create ringbuffer %d: %d\n", i, ret); 947 goto fail; 948 } 949 950 memptrs += sizeof(struct msm_rbmemptrs); 951 memptrs_iova += sizeof(struct msm_rbmemptrs); 952 } 953 954 gpu->nr_rings = nr_rings; 955 956 return 0; 957 958 fail: 959 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 960 msm_ringbuffer_destroy(gpu->rb[i]); 961 gpu->rb[i] = NULL; 962 } 963 964 if (gpu->memptrs_bo) { 965 msm_gem_put_vaddr(gpu->memptrs_bo); 966 msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace); 967 drm_gem_object_put_unlocked(gpu->memptrs_bo); 968 } 969 970 platform_set_drvdata(pdev, NULL); 971 return ret; 972 } 973 974 void msm_gpu_cleanup(struct msm_gpu *gpu) 975 { 976 int i; 977 978 DBG("%s", gpu->name); 979 980 WARN_ON(!list_empty(&gpu->active_list)); 981 982 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 983 msm_ringbuffer_destroy(gpu->rb[i]); 984 gpu->rb[i] = NULL; 985 } 986 987 if (gpu->memptrs_bo) { 988 msm_gem_put_vaddr(gpu->memptrs_bo); 989 msm_gem_put_iova(gpu->memptrs_bo, gpu->aspace); 990 drm_gem_object_put_unlocked(gpu->memptrs_bo); 991 } 992 993 if (!IS_ERR_OR_NULL(gpu->aspace)) { 994 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, 995 NULL, 0); 996 msm_gem_address_space_put(gpu->aspace); 997 } 998 } 999