xref: /openbmc/linux/drivers/gpu/drm/msm/msm_gem.h (revision a7d3c950)
1c8afe684SRob Clark /*
2c8afe684SRob Clark  * Copyright (C) 2013 Red Hat
3c8afe684SRob Clark  * Author: Rob Clark <robdclark@gmail.com>
4c8afe684SRob Clark  *
5c8afe684SRob Clark  * This program is free software; you can redistribute it and/or modify it
6c8afe684SRob Clark  * under the terms of the GNU General Public License version 2 as published by
7c8afe684SRob Clark  * the Free Software Foundation.
8c8afe684SRob Clark  *
9c8afe684SRob Clark  * This program is distributed in the hope that it will be useful, but WITHOUT
10c8afe684SRob Clark  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11c8afe684SRob Clark  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12c8afe684SRob Clark  * more details.
13c8afe684SRob Clark  *
14c8afe684SRob Clark  * You should have received a copy of the GNU General Public License along with
15c8afe684SRob Clark  * this program.  If not, see <http://www.gnu.org/licenses/>.
16c8afe684SRob Clark  */
17c8afe684SRob Clark 
18c8afe684SRob Clark #ifndef __MSM_GEM_H__
19c8afe684SRob Clark #define __MSM_GEM_H__
20c8afe684SRob Clark 
217198e6b0SRob Clark #include <linux/reservation.h>
22c8afe684SRob Clark #include "msm_drv.h"
23c8afe684SRob Clark 
24c8afe684SRob Clark struct msm_gem_object {
25c8afe684SRob Clark 	struct drm_gem_object base;
26c8afe684SRob Clark 
27c8afe684SRob Clark 	uint32_t flags;
28c8afe684SRob Clark 
297198e6b0SRob Clark 	/* And object is either:
307198e6b0SRob Clark 	 *  inactive - on priv->inactive_list
317198e6b0SRob Clark 	 *  active   - on one one of the gpu's active_list..  well, at
327198e6b0SRob Clark 	 *     least for now we don't have (I don't think) hw sync between
337198e6b0SRob Clark 	 *     2d and 3d one devices which have both, meaning we need to
347198e6b0SRob Clark 	 *     block on submit if a bo is already on other ring
357198e6b0SRob Clark 	 *
367198e6b0SRob Clark 	 */
37c8afe684SRob Clark 	struct list_head mm_list;
387198e6b0SRob Clark 	struct msm_gpu *gpu;     /* non-null if active */
39bf6811f3SRob Clark 	uint32_t read_fence, write_fence;
407198e6b0SRob Clark 
417198e6b0SRob Clark 	/* Transiently in the process of submit ioctl, objects associated
427198e6b0SRob Clark 	 * with the submit are on submit->bo_list.. this only lasts for
437198e6b0SRob Clark 	 * the duration of the ioctl, so one bo can never be on multiple
447198e6b0SRob Clark 	 * submit lists.
457198e6b0SRob Clark 	 */
467198e6b0SRob Clark 	struct list_head submit_entry;
477198e6b0SRob Clark 
48c8afe684SRob Clark 	struct page **pages;
49c8afe684SRob Clark 	struct sg_table *sgt;
50c8afe684SRob Clark 	void *vaddr;
51c8afe684SRob Clark 
52c8afe684SRob Clark 	struct {
53c8afe684SRob Clark 		// XXX
54c8afe684SRob Clark 		uint32_t iova;
55c8afe684SRob Clark 	} domain[NUM_DOMAINS];
567198e6b0SRob Clark 
577198e6b0SRob Clark 	/* normally (resv == &_resv) except for imported bo's */
587198e6b0SRob Clark 	struct reservation_object *resv;
597198e6b0SRob Clark 	struct reservation_object _resv;
60871d812aSRob Clark 
61871d812aSRob Clark 	/* For physically contiguous buffers.  Used when we don't have
62871d812aSRob Clark 	 * an IOMMU.
63871d812aSRob Clark 	 */
64871d812aSRob Clark 	struct drm_mm_node *vram_node;
65c8afe684SRob Clark };
66c8afe684SRob Clark #define to_msm_bo(x) container_of(x, struct msm_gem_object, base)
67c8afe684SRob Clark 
687198e6b0SRob Clark static inline bool is_active(struct msm_gem_object *msm_obj)
697198e6b0SRob Clark {
707198e6b0SRob Clark 	return msm_obj->gpu != NULL;
717198e6b0SRob Clark }
727198e6b0SRob Clark 
737198e6b0SRob Clark #define MAX_CMDS 4
747198e6b0SRob Clark 
757198e6b0SRob Clark /* Created per submit-ioctl, to track bo's and cmdstream bufs, etc,
767198e6b0SRob Clark  * associated with the cmdstream submission for synchronization (and
777198e6b0SRob Clark  * make it easier to unwind when things go wrong, etc).  This only
787198e6b0SRob Clark  * lasts for the duration of the submit-ioctl.
797198e6b0SRob Clark  */
807198e6b0SRob Clark struct msm_gem_submit {
817198e6b0SRob Clark 	struct drm_device *dev;
827198e6b0SRob Clark 	struct msm_gpu *gpu;
837198e6b0SRob Clark 	struct list_head bo_list;
847198e6b0SRob Clark 	struct ww_acquire_ctx ticket;
857198e6b0SRob Clark 	uint32_t fence;
867198e6b0SRob Clark 	bool valid;
877198e6b0SRob Clark 	unsigned int nr_cmds;
887198e6b0SRob Clark 	unsigned int nr_bos;
897198e6b0SRob Clark 	struct {
907198e6b0SRob Clark 		uint32_t type;
917198e6b0SRob Clark 		uint32_t size;  /* in dwords */
927198e6b0SRob Clark 		uint32_t iova;
93a7d3c950SRob Clark 		uint32_t idx;   /* cmdstream buffer idx in bos[] */
947198e6b0SRob Clark 	} cmd[MAX_CMDS];
957198e6b0SRob Clark 	struct {
967198e6b0SRob Clark 		uint32_t flags;
977198e6b0SRob Clark 		struct msm_gem_object *obj;
987198e6b0SRob Clark 		uint32_t iova;
997198e6b0SRob Clark 	} bos[0];
1007198e6b0SRob Clark };
1017198e6b0SRob Clark 
102c8afe684SRob Clark #endif /* __MSM_GEM_H__ */
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