1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2fde5de6cSRob Clark /*
3fde5de6cSRob Clark * Copyright (C) 2013-2016 Red Hat
4fde5de6cSRob Clark * Author: Rob Clark <robdclark@gmail.com>
5fde5de6cSRob Clark */
6fde5de6cSRob Clark
7fde5de6cSRob Clark #ifndef __MSM_FENCE_H__
8fde5de6cSRob Clark #define __MSM_FENCE_H__
9fde5de6cSRob Clark
10fde5de6cSRob Clark #include "msm_drv.h"
11fde5de6cSRob Clark
12da3d378dSRob Clark /**
13da3d378dSRob Clark * struct msm_fence_context - fence context for gpu
14da3d378dSRob Clark *
15da3d378dSRob Clark * Each ringbuffer has a single fence context, with the GPU writing an
16da3d378dSRob Clark * incrementing fence seqno at the end of each submit
17da3d378dSRob Clark */
18ca762a8aSRob Clark struct msm_fence_context {
19ca762a8aSRob Clark struct drm_device *dev;
20da3d378dSRob Clark /** name: human readable name for fence timeline */
21f97decacSJordan Crouse char name[32];
22da3d378dSRob Clark /** context: see dma_fence_context_alloc() */
23b6295f9aSRob Clark unsigned context;
2495d1deb0SRob Clark /** index: similar to context, but local to msm_fence_context's */
2595d1deb0SRob Clark unsigned index;
26da3d378dSRob Clark
27da3d378dSRob Clark /**
28da3d378dSRob Clark * last_fence:
29da3d378dSRob Clark *
30da3d378dSRob Clark * Last assigned fence, incremented each time a fence is created
31da3d378dSRob Clark * on this fence context. If last_fence == completed_fence,
32da3d378dSRob Clark * there is no remaining pending work
33da3d378dSRob Clark */
34da3d378dSRob Clark uint32_t last_fence;
35da3d378dSRob Clark
36da3d378dSRob Clark /**
37da3d378dSRob Clark * completed_fence:
38da3d378dSRob Clark *
39da3d378dSRob Clark * The last completed fence, updated from the CPU after interrupt
40da3d378dSRob Clark * from GPU
41da3d378dSRob Clark */
42da3d378dSRob Clark uint32_t completed_fence;
43da3d378dSRob Clark
44da3d378dSRob Clark /**
45da3d378dSRob Clark * fenceptr:
46da3d378dSRob Clark *
47da3d378dSRob Clark * The address that the GPU directly writes with completed fence
48da3d378dSRob Clark * seqno. This can be ahead of completed_fence. We can peek at
49da3d378dSRob Clark * this to see if a fence has already signaled but the CPU hasn't
50da3d378dSRob Clark * gotten around to handling the irq and updating completed_fence
51da3d378dSRob Clark */
52da3d378dSRob Clark volatile uint32_t *fenceptr;
53da3d378dSRob Clark
54b6295f9aSRob Clark spinlock_t spinlock;
55*f8b8487cSRob Clark
56*f8b8487cSRob Clark /*
57*f8b8487cSRob Clark * TODO this doesn't really deal with multiple deadlines, like
58*f8b8487cSRob Clark * if userspace got multiple frames ahead.. OTOH atomic updates
59*f8b8487cSRob Clark * don't queue, so maybe that is ok
60*f8b8487cSRob Clark */
61*f8b8487cSRob Clark
62*f8b8487cSRob Clark /** next_deadline: Time of next deadline */
63*f8b8487cSRob Clark ktime_t next_deadline;
64*f8b8487cSRob Clark
65*f8b8487cSRob Clark /**
66*f8b8487cSRob Clark * next_deadline_fence:
67*f8b8487cSRob Clark *
68*f8b8487cSRob Clark * Fence value for next pending deadline. The deadline timer is
69*f8b8487cSRob Clark * canceled when this fence is signaled.
70*f8b8487cSRob Clark */
71*f8b8487cSRob Clark uint32_t next_deadline_fence;
72*f8b8487cSRob Clark
73*f8b8487cSRob Clark struct hrtimer deadline_timer;
74*f8b8487cSRob Clark struct kthread_work deadline_work;
75ca762a8aSRob Clark };
76ca762a8aSRob Clark
77ca762a8aSRob Clark struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev,
78da3d378dSRob Clark volatile uint32_t *fenceptr, const char *name);
79ca762a8aSRob Clark void msm_fence_context_free(struct msm_fence_context *fctx);
80ca762a8aSRob Clark
8195d1deb0SRob Clark bool msm_fence_completed(struct msm_fence_context *fctx, uint32_t fence);
82ca762a8aSRob Clark void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence);
83fde5de6cSRob Clark
84f94e6a51SRob Clark struct dma_fence * msm_fence_alloc(void);
85f94e6a51SRob Clark void msm_fence_init(struct dma_fence *fence, struct msm_fence_context *fctx);
86b6295f9aSRob Clark
875f3aee4cSRob Clark static inline bool
fence_before(uint32_t a,uint32_t b)885f3aee4cSRob Clark fence_before(uint32_t a, uint32_t b)
895f3aee4cSRob Clark {
905f3aee4cSRob Clark return (int32_t)(a - b) < 0;
915f3aee4cSRob Clark }
925f3aee4cSRob Clark
935f3aee4cSRob Clark static inline bool
fence_after(uint32_t a,uint32_t b)945f3aee4cSRob Clark fence_after(uint32_t a, uint32_t b)
955f3aee4cSRob Clark {
965f3aee4cSRob Clark return (int32_t)(a - b) > 0;
975f3aee4cSRob Clark }
985f3aee4cSRob Clark
99fde5de6cSRob Clark #endif
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