1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/module.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/list.h> 21 #include <linux/iommu.h> 22 #include <linux/types.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_device.h> 25 #include <linux/sizes.h> 26 #include <linux/kthread.h> 27 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 struct msm_kms; 37 struct msm_gpu; 38 struct msm_mmu; 39 struct msm_mdss; 40 struct msm_rd_state; 41 struct msm_perf_state; 42 struct msm_gem_submit; 43 struct msm_fence_context; 44 struct msm_gem_address_space; 45 struct msm_gem_vma; 46 struct msm_disp_state; 47 48 #define MAX_CRTCS 8 49 #define MAX_PLANES 20 50 #define MAX_ENCODERS 8 51 #define MAX_BRIDGES 8 52 #define MAX_CONNECTORS 8 53 54 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 55 56 enum msm_mdp_plane_property { 57 PLANE_PROP_ZPOS, 58 PLANE_PROP_ALPHA, 59 PLANE_PROP_PREMULTIPLIED, 60 PLANE_PROP_MAX_NUM 61 }; 62 63 enum msm_dp_controller { 64 MSM_DP_CONTROLLER_0, 65 MSM_DP_CONTROLLER_1, 66 MSM_DP_CONTROLLER_2, 67 MSM_DP_CONTROLLER_COUNT, 68 }; 69 70 #define MSM_GPU_MAX_RINGS 4 71 #define MAX_H_TILES_PER_DISPLAY 2 72 73 /** 74 * enum msm_display_caps - features/capabilities supported by displays 75 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 76 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 77 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 78 * @MSM_DISPLAY_CAP_EDID: EDID supported 79 */ 80 enum msm_display_caps { 81 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 82 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 83 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 84 MSM_DISPLAY_CAP_EDID = BIT(3), 85 }; 86 87 /** 88 * enum msm_event_wait - type of HW events to wait for 89 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 90 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 91 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 92 */ 93 enum msm_event_wait { 94 MSM_ENC_COMMIT_DONE = 0, 95 MSM_ENC_TX_COMPLETE, 96 MSM_ENC_VBLANK, 97 }; 98 99 /** 100 * struct msm_display_topology - defines a display topology pipeline 101 * @num_lm: number of layer mixers used 102 * @num_enc: number of compression encoder blocks used 103 * @num_intf: number of interfaces the panel is mounted on 104 */ 105 struct msm_display_topology { 106 u32 num_lm; 107 u32 num_enc; 108 u32 num_intf; 109 u32 num_dspp; 110 }; 111 112 /* Commit/Event thread specific structure */ 113 struct msm_drm_thread { 114 struct drm_device *dev; 115 unsigned int crtc_id; 116 struct kthread_worker *worker; 117 }; 118 119 struct msm_drm_private { 120 121 struct drm_device *dev; 122 123 struct msm_kms *kms; 124 125 /* subordinate devices, if present: */ 126 struct platform_device *gpu_pdev; 127 128 /* top level MDSS wrapper device (for MDP5/DPU only) */ 129 struct msm_mdss *mdss; 130 131 /* possibly this should be in the kms component, but it is 132 * shared by both mdp4 and mdp5.. 133 */ 134 struct hdmi *hdmi; 135 136 /* DSI is shared by mdp4 and mdp5 */ 137 struct msm_dsi *dsi[2]; 138 139 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 140 141 /* when we have more than one 'msm_gpu' these need to be an array: */ 142 struct msm_gpu *gpu; 143 144 /* gpu is only set on open(), but we need this info earlier */ 145 bool is_a2xx; 146 bool has_cached_coherent; 147 148 struct drm_fb_helper *fbdev; 149 150 struct msm_rd_state *rd; /* debugfs to dump all submits */ 151 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 152 struct msm_perf_state *perf; 153 154 /** 155 * List of all GEM objects (mainly for debugfs, protected by obj_lock 156 * (acquire before per GEM object lock) 157 */ 158 struct list_head objects; 159 struct mutex obj_lock; 160 161 /** 162 * LRUs of inactive GEM objects. Every bo is either in one of the 163 * inactive lists (depending on whether or not it is shrinkable) or 164 * gpu->active_list (for the gpu it is active on[1]), or transiently 165 * on a temporary list as the shrinker is running. 166 * 167 * Note that inactive_willneed also contains pinned and vmap'd bos, 168 * but the number of pinned-but-not-active objects is small (scanout 169 * buffers, ringbuffer, etc). 170 * 171 * These lists are protected by mm_lock (which should be acquired 172 * before per GEM object lock). One should *not* hold mm_lock in 173 * get_pages()/vmap()/etc paths, as they can trigger the shrinker. 174 * 175 * [1] if someone ever added support for the old 2d cores, there could be 176 * more than one gpu object 177 */ 178 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */ 179 struct list_head inactive_dontneed; /* inactive + shrinkable */ 180 struct list_head inactive_unpinned; /* inactive + purged or unpinned */ 181 long shrinkable_count; /* write access under mm_lock */ 182 long evictable_count; /* write access under mm_lock */ 183 struct mutex mm_lock; 184 185 struct workqueue_struct *wq; 186 187 unsigned int num_planes; 188 struct drm_plane *planes[MAX_PLANES]; 189 190 unsigned int num_crtcs; 191 struct drm_crtc *crtcs[MAX_CRTCS]; 192 193 struct msm_drm_thread event_thread[MAX_CRTCS]; 194 195 unsigned int num_encoders; 196 struct drm_encoder *encoders[MAX_ENCODERS]; 197 198 unsigned int num_bridges; 199 struct drm_bridge *bridges[MAX_BRIDGES]; 200 201 unsigned int num_connectors; 202 struct drm_connector *connectors[MAX_CONNECTORS]; 203 204 /* Properties */ 205 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 206 207 /* VRAM carveout, used when no IOMMU: */ 208 struct { 209 unsigned long size; 210 dma_addr_t paddr; 211 /* NOTE: mm managed at the page level, size is in # of pages 212 * and position mm_node->start is in # of pages: 213 */ 214 struct drm_mm mm; 215 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 216 } vram; 217 218 struct notifier_block vmap_notifier; 219 struct shrinker shrinker; 220 221 struct drm_atomic_state *pm_state; 222 223 /* For hang detection, in ms */ 224 unsigned int hangcheck_period; 225 226 /** 227 * disable_err_irq: 228 * 229 * Disable handling of GPU hw error interrupts, to force fallback to 230 * sw hangcheck timer. Written (via debugfs) by igt tests to test 231 * the sw hangcheck mechanism. 232 */ 233 bool disable_err_irq; 234 }; 235 236 struct msm_format { 237 uint32_t pixel_format; 238 }; 239 240 struct msm_pending_timer; 241 242 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 243 struct msm_kms *kms, int crtc_idx); 244 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 245 void msm_atomic_commit_tail(struct drm_atomic_state *state); 246 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 247 void msm_atomic_state_clear(struct drm_atomic_state *state); 248 void msm_atomic_state_free(struct drm_atomic_state *state); 249 250 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 251 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 252 253 int msm_gem_init_vma(struct msm_gem_address_space *aspace, 254 struct msm_gem_vma *vma, int npages, 255 u64 range_start, u64 range_end); 256 void msm_gem_purge_vma(struct msm_gem_address_space *aspace, 257 struct msm_gem_vma *vma); 258 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 259 struct msm_gem_vma *vma); 260 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 261 struct msm_gem_vma *vma, int prot, 262 struct sg_table *sgt, int npages); 263 void msm_gem_close_vma(struct msm_gem_address_space *aspace, 264 struct msm_gem_vma *vma); 265 266 267 struct msm_gem_address_space * 268 msm_gem_address_space_get(struct msm_gem_address_space *aspace); 269 270 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 271 272 struct msm_gem_address_space * 273 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name, 274 u64 va_start, u64 size); 275 276 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 277 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 278 279 bool msm_use_mmu(struct drm_device *dev); 280 281 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 282 struct drm_file *file); 283 284 #ifdef CONFIG_DEBUG_FS 285 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 286 #endif 287 288 void msm_gem_shrinker_init(struct drm_device *dev); 289 void msm_gem_shrinker_cleanup(struct drm_device *dev); 290 291 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 292 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 293 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 294 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 295 struct dma_buf_attachment *attach, struct sg_table *sg); 296 int msm_gem_prime_pin(struct drm_gem_object *obj); 297 void msm_gem_prime_unpin(struct drm_gem_object *obj); 298 299 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 300 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 301 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 302 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 303 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 304 struct msm_gem_address_space *aspace, int plane); 305 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 306 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 307 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 308 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 309 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 310 int w, int h, int p, uint32_t format); 311 312 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 313 void msm_fbdev_free(struct drm_device *dev); 314 315 struct hdmi; 316 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 317 struct drm_encoder *encoder); 318 void __init msm_hdmi_register(void); 319 void __exit msm_hdmi_unregister(void); 320 321 struct msm_dsi; 322 #ifdef CONFIG_DRM_MSM_DSI 323 int dsi_dev_attach(struct platform_device *pdev); 324 void dsi_dev_detach(struct platform_device *pdev); 325 void __init msm_dsi_register(void); 326 void __exit msm_dsi_unregister(void); 327 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 328 struct drm_encoder *encoder); 329 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 330 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 331 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 332 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 333 #else 334 static inline void __init msm_dsi_register(void) 335 { 336 } 337 static inline void __exit msm_dsi_unregister(void) 338 { 339 } 340 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 341 struct drm_device *dev, 342 struct drm_encoder *encoder) 343 { 344 return -EINVAL; 345 } 346 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 347 { 348 } 349 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 350 { 351 return false; 352 } 353 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 354 { 355 return false; 356 } 357 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 358 { 359 return false; 360 } 361 #endif 362 363 #ifdef CONFIG_DRM_MSM_DP 364 int __init msm_dp_register(void); 365 void __exit msm_dp_unregister(void); 366 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 367 struct drm_encoder *encoder); 368 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder); 369 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder); 370 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder); 371 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, 372 const struct drm_display_mode *mode, 373 const struct drm_display_mode *adjusted_mode); 374 375 struct drm_bridge *msm_dp_bridge_init(struct msm_dp *dp_display, 376 struct drm_device *dev, 377 struct drm_encoder *encoder); 378 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 379 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 380 381 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 382 383 #else 384 static inline int __init msm_dp_register(void) 385 { 386 return -EINVAL; 387 } 388 static inline void __exit msm_dp_unregister(void) 389 { 390 } 391 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 392 struct drm_device *dev, 393 struct drm_encoder *encoder) 394 { 395 return -EINVAL; 396 } 397 static inline int msm_dp_display_enable(struct msm_dp *dp, 398 struct drm_encoder *encoder) 399 { 400 return -EINVAL; 401 } 402 static inline int msm_dp_display_disable(struct msm_dp *dp, 403 struct drm_encoder *encoder) 404 { 405 return -EINVAL; 406 } 407 static inline int msm_dp_display_pre_disable(struct msm_dp *dp, 408 struct drm_encoder *encoder) 409 { 410 return -EINVAL; 411 } 412 static inline void msm_dp_display_mode_set(struct msm_dp *dp, 413 struct drm_encoder *encoder, 414 const struct drm_display_mode *mode, 415 const struct drm_display_mode *adjusted_mode) 416 { 417 } 418 419 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 420 { 421 } 422 423 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 424 { 425 } 426 427 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 428 struct drm_minor *minor) 429 { 430 } 431 432 #endif 433 434 void __init msm_mdp_register(void); 435 void __exit msm_mdp_unregister(void); 436 void __init msm_dpu_register(void); 437 void __exit msm_dpu_unregister(void); 438 439 #ifdef CONFIG_DEBUG_FS 440 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 441 int msm_debugfs_late_init(struct drm_device *dev); 442 int msm_rd_debugfs_init(struct drm_minor *minor); 443 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 444 __printf(3, 4) 445 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 446 const char *fmt, ...); 447 int msm_perf_debugfs_init(struct drm_minor *minor); 448 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 449 #else 450 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 451 __printf(3, 4) 452 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 453 struct msm_gem_submit *submit, 454 const char *fmt, ...) {} 455 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 456 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 457 #endif 458 459 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 460 461 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 462 const char *name); 463 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 464 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 465 phys_addr_t *size); 466 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 467 468 #define msm_writel(data, addr) writel((data), (addr)) 469 #define msm_readl(addr) readl((addr)) 470 471 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 472 { 473 u32 val = msm_readl(addr); 474 475 val &= ~mask; 476 msm_writel(val | or, addr); 477 } 478 479 /** 480 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 481 * 482 * @timer: hrtimer to control when the kthread work is triggered 483 * @work: the kthread work 484 * @worker: the kthread worker the work will be scheduled on 485 */ 486 struct msm_hrtimer_work { 487 struct hrtimer timer; 488 struct kthread_work work; 489 struct kthread_worker *worker; 490 }; 491 492 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 493 ktime_t wakeup_time, 494 enum hrtimer_mode mode); 495 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 496 struct kthread_worker *worker, 497 kthread_work_func_t fn, 498 clockid_t clock_id, 499 enum hrtimer_mode mode); 500 501 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 502 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 503 504 static inline int align_pitch(int width, int bpp) 505 { 506 int bytespp = (bpp + 7) / 8; 507 /* adreno needs pitch aligned to 32 pixels: */ 508 return bytespp * ALIGN(width, 32); 509 } 510 511 /* for the generated headers: */ 512 #define INVALID_IDX(idx) ({BUG(); 0;}) 513 #define fui(x) ({BUG(); 0;}) 514 #define _mesa_float_to_half(x) ({BUG(); 0;}) 515 516 517 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 518 519 /* for conditionally setting boolean flag(s): */ 520 #define COND(bool, val) ((bool) ? (val) : 0) 521 522 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 523 { 524 ktime_t now = ktime_get(); 525 s64 remaining_jiffies; 526 527 if (ktime_compare(*timeout, now) < 0) { 528 remaining_jiffies = 0; 529 } else { 530 ktime_t rem = ktime_sub(*timeout, now); 531 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 532 } 533 534 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX); 535 } 536 537 #endif /* __MSM_DRV_H__ */ 538