xref: /openbmc/linux/drivers/gpu/drm/msm/msm_drv.h (revision da2ef666)
1 /*
2  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published by
8  * the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #ifndef __MSM_DRV_H__
20 #define __MSM_DRV_H__
21 
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/cpufreq.h>
25 #include <linux/module.h>
26 #include <linux/component.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31 #include <linux/list.h>
32 #include <linux/iommu.h>
33 #include <linux/types.h>
34 #include <linux/of_graph.h>
35 #include <linux/of_device.h>
36 #include <asm/sizes.h>
37 #include <linux/kthread.h>
38 
39 #include <drm/drmP.h>
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_fb_helper.h>
45 #include <drm/msm_drm.h>
46 #include <drm/drm_gem.h>
47 
48 struct msm_kms;
49 struct msm_gpu;
50 struct msm_mmu;
51 struct msm_mdss;
52 struct msm_rd_state;
53 struct msm_perf_state;
54 struct msm_gem_submit;
55 struct msm_fence_context;
56 struct msm_gem_address_space;
57 struct msm_gem_vma;
58 
59 #define MAX_CRTCS      8
60 #define MAX_PLANES     20
61 #define MAX_ENCODERS   8
62 #define MAX_BRIDGES    8
63 #define MAX_CONNECTORS 8
64 
65 struct msm_file_private {
66 	rwlock_t queuelock;
67 	struct list_head submitqueues;
68 	int queueid;
69 };
70 
71 enum msm_mdp_plane_property {
72 	PLANE_PROP_ZPOS,
73 	PLANE_PROP_ALPHA,
74 	PLANE_PROP_PREMULTIPLIED,
75 	PLANE_PROP_MAX_NUM
76 };
77 
78 struct msm_vblank_ctrl {
79 	struct kthread_work work;
80 	struct list_head event_list;
81 	spinlock_t lock;
82 };
83 
84 #define MSM_GPU_MAX_RINGS 4
85 #define MAX_H_TILES_PER_DISPLAY 2
86 
87 /**
88  * enum msm_display_caps - features/capabilities supported by displays
89  * @MSM_DISPLAY_CAP_VID_MODE:           Video or "active" mode supported
90  * @MSM_DISPLAY_CAP_CMD_MODE:           Command mode supported
91  * @MSM_DISPLAY_CAP_HOT_PLUG:           Hot plug detection supported
92  * @MSM_DISPLAY_CAP_EDID:               EDID supported
93  */
94 enum msm_display_caps {
95 	MSM_DISPLAY_CAP_VID_MODE	= BIT(0),
96 	MSM_DISPLAY_CAP_CMD_MODE	= BIT(1),
97 	MSM_DISPLAY_CAP_HOT_PLUG	= BIT(2),
98 	MSM_DISPLAY_CAP_EDID		= BIT(3),
99 };
100 
101 /**
102  * enum msm_event_wait - type of HW events to wait for
103  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
104  * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
105  * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
106  */
107 enum msm_event_wait {
108 	MSM_ENC_COMMIT_DONE = 0,
109 	MSM_ENC_TX_COMPLETE,
110 	MSM_ENC_VBLANK,
111 };
112 
113 /**
114  * struct msm_display_topology - defines a display topology pipeline
115  * @num_lm:       number of layer mixers used
116  * @num_enc:      number of compression encoder blocks used
117  * @num_intf:     number of interfaces the panel is mounted on
118  */
119 struct msm_display_topology {
120 	u32 num_lm;
121 	u32 num_enc;
122 	u32 num_intf;
123 };
124 
125 /**
126  * struct msm_display_info - defines display properties
127  * @intf_type:          DRM_MODE_CONNECTOR_ display type
128  * @capabilities:       Bitmask of display flags
129  * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
130  * @h_tile_instance:    Controller instance used per tile. Number of elements is
131  *                      based on num_of_h_tiles
132  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
133  *				 used instead of panel TE in cmd mode panels
134  */
135 struct msm_display_info {
136 	int intf_type;
137 	uint32_t capabilities;
138 	uint32_t num_of_h_tiles;
139 	uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
140 	bool is_te_using_watchdog_timer;
141 };
142 
143 /* Commit/Event thread specific structure */
144 struct msm_drm_thread {
145 	struct drm_device *dev;
146 	struct task_struct *thread;
147 	unsigned int crtc_id;
148 	struct kthread_worker worker;
149 };
150 
151 struct msm_drm_private {
152 
153 	struct drm_device *dev;
154 
155 	struct msm_kms *kms;
156 
157 	/* subordinate devices, if present: */
158 	struct platform_device *gpu_pdev;
159 
160 	/* top level MDSS wrapper device (for MDP5/DPU only) */
161 	struct msm_mdss *mdss;
162 
163 	/* possibly this should be in the kms component, but it is
164 	 * shared by both mdp4 and mdp5..
165 	 */
166 	struct hdmi *hdmi;
167 
168 	/* eDP is for mdp5 only, but kms has not been created
169 	 * when edp_bind() and edp_init() are called. Here is the only
170 	 * place to keep the edp instance.
171 	 */
172 	struct msm_edp *edp;
173 
174 	/* DSI is shared by mdp4 and mdp5 */
175 	struct msm_dsi *dsi[2];
176 
177 	/* when we have more than one 'msm_gpu' these need to be an array: */
178 	struct msm_gpu *gpu;
179 	struct msm_file_private *lastctx;
180 
181 	struct drm_fb_helper *fbdev;
182 
183 	struct msm_rd_state *rd;       /* debugfs to dump all submits */
184 	struct msm_rd_state *hangrd;   /* debugfs to dump hanging submits */
185 	struct msm_perf_state *perf;
186 
187 	/* list of GEM objects: */
188 	struct list_head inactive_list;
189 
190 	struct workqueue_struct *wq;
191 
192 	unsigned int num_planes;
193 	struct drm_plane *planes[MAX_PLANES];
194 
195 	unsigned int num_crtcs;
196 	struct drm_crtc *crtcs[MAX_CRTCS];
197 
198 	struct msm_drm_thread disp_thread[MAX_CRTCS];
199 	struct msm_drm_thread event_thread[MAX_CRTCS];
200 
201 	unsigned int num_encoders;
202 	struct drm_encoder *encoders[MAX_ENCODERS];
203 
204 	unsigned int num_bridges;
205 	struct drm_bridge *bridges[MAX_BRIDGES];
206 
207 	unsigned int num_connectors;
208 	struct drm_connector *connectors[MAX_CONNECTORS];
209 
210 	/* Properties */
211 	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
212 
213 	/* VRAM carveout, used when no IOMMU: */
214 	struct {
215 		unsigned long size;
216 		dma_addr_t paddr;
217 		/* NOTE: mm managed at the page level, size is in # of pages
218 		 * and position mm_node->start is in # of pages:
219 		 */
220 		struct drm_mm mm;
221 		spinlock_t lock; /* Protects drm_mm node allocation/removal */
222 	} vram;
223 
224 	struct notifier_block vmap_notifier;
225 	struct shrinker shrinker;
226 
227 	struct msm_vblank_ctrl vblank_ctrl;
228 	struct drm_atomic_state *pm_state;
229 };
230 
231 struct msm_format {
232 	uint32_t pixel_format;
233 };
234 
235 int msm_atomic_prepare_fb(struct drm_plane *plane,
236 			  struct drm_plane_state *new_state);
237 void msm_atomic_commit_tail(struct drm_atomic_state *state);
238 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
239 void msm_atomic_state_clear(struct drm_atomic_state *state);
240 void msm_atomic_state_free(struct drm_atomic_state *state);
241 
242 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
243 		struct msm_gem_vma *vma, struct sg_table *sgt);
244 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
245 		struct msm_gem_vma *vma, struct sg_table *sgt, int npages);
246 
247 void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
248 
249 struct msm_gem_address_space *
250 msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
251 		const char *name);
252 
253 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
254 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
255 
256 void msm_gem_submit_free(struct msm_gem_submit *submit);
257 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
258 		struct drm_file *file);
259 
260 void msm_gem_shrinker_init(struct drm_device *dev);
261 void msm_gem_shrinker_cleanup(struct drm_device *dev);
262 
263 int msm_gem_mmap_obj(struct drm_gem_object *obj,
264 			struct vm_area_struct *vma);
265 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
266 vm_fault_t msm_gem_fault(struct vm_fault *vmf);
267 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
268 int msm_gem_get_iova(struct drm_gem_object *obj,
269 		struct msm_gem_address_space *aspace, uint64_t *iova);
270 uint64_t msm_gem_iova(struct drm_gem_object *obj,
271 		struct msm_gem_address_space *aspace);
272 struct page **msm_gem_get_pages(struct drm_gem_object *obj);
273 void msm_gem_put_pages(struct drm_gem_object *obj);
274 void msm_gem_put_iova(struct drm_gem_object *obj,
275 		struct msm_gem_address_space *aspace);
276 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
277 		struct drm_mode_create_dumb *args);
278 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
279 		uint32_t handle, uint64_t *offset);
280 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
281 void *msm_gem_prime_vmap(struct drm_gem_object *obj);
282 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
283 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
284 struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj);
285 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
286 		struct dma_buf_attachment *attach, struct sg_table *sg);
287 int msm_gem_prime_pin(struct drm_gem_object *obj);
288 void msm_gem_prime_unpin(struct drm_gem_object *obj);
289 void *msm_gem_get_vaddr(struct drm_gem_object *obj);
290 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
291 void msm_gem_put_vaddr(struct drm_gem_object *obj);
292 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
293 int msm_gem_sync_object(struct drm_gem_object *obj,
294 		struct msm_fence_context *fctx, bool exclusive);
295 void msm_gem_move_to_active(struct drm_gem_object *obj,
296 		struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
297 void msm_gem_move_to_inactive(struct drm_gem_object *obj);
298 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
299 int msm_gem_cpu_fini(struct drm_gem_object *obj);
300 void msm_gem_free_object(struct drm_gem_object *obj);
301 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
302 		uint32_t size, uint32_t flags, uint32_t *handle);
303 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
304 		uint32_t size, uint32_t flags);
305 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
306 		uint32_t size, uint32_t flags);
307 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
308 		uint32_t flags, struct msm_gem_address_space *aspace,
309 		struct drm_gem_object **bo, uint64_t *iova);
310 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
311 		uint32_t flags, struct msm_gem_address_space *aspace,
312 		struct drm_gem_object **bo, uint64_t *iova);
313 struct drm_gem_object *msm_gem_import(struct drm_device *dev,
314 		struct dma_buf *dmabuf, struct sg_table *sgt);
315 
316 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
317 		struct msm_gem_address_space *aspace);
318 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
319 		struct msm_gem_address_space *aspace);
320 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
321 		struct msm_gem_address_space *aspace, int plane);
322 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
323 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
324 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
325 		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
326 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
327 		int w, int h, int p, uint32_t format);
328 
329 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
330 void msm_fbdev_free(struct drm_device *dev);
331 
332 struct hdmi;
333 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
334 		struct drm_encoder *encoder);
335 void __init msm_hdmi_register(void);
336 void __exit msm_hdmi_unregister(void);
337 
338 struct msm_edp;
339 void __init msm_edp_register(void);
340 void __exit msm_edp_unregister(void);
341 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
342 		struct drm_encoder *encoder);
343 
344 struct msm_dsi;
345 #ifdef CONFIG_DRM_MSM_DSI
346 void __init msm_dsi_register(void);
347 void __exit msm_dsi_unregister(void);
348 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
349 			 struct drm_encoder *encoder);
350 #else
351 static inline void __init msm_dsi_register(void)
352 {
353 }
354 static inline void __exit msm_dsi_unregister(void)
355 {
356 }
357 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
358 				       struct drm_device *dev,
359 				       struct drm_encoder *encoder)
360 {
361 	return -EINVAL;
362 }
363 #endif
364 
365 void __init msm_mdp_register(void);
366 void __exit msm_mdp_unregister(void);
367 void __init msm_dpu_register(void);
368 void __exit msm_dpu_unregister(void);
369 
370 #ifdef CONFIG_DEBUG_FS
371 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
372 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
373 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
374 int msm_debugfs_late_init(struct drm_device *dev);
375 int msm_rd_debugfs_init(struct drm_minor *minor);
376 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
377 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
378 		const char *fmt, ...);
379 int msm_perf_debugfs_init(struct drm_minor *minor);
380 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
381 #else
382 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
383 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
384 		const char *fmt, ...) {}
385 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
386 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
387 #endif
388 
389 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
390 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);
391 
392 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
393 	const char *name);
394 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
395 		const char *dbgname);
396 void msm_writel(u32 data, void __iomem *addr);
397 u32 msm_readl(const void __iomem *addr);
398 
399 struct msm_gpu_submitqueue;
400 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
401 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
402 		u32 id);
403 int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
404 		u32 prio, u32 flags, u32 *id);
405 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
406 void msm_submitqueue_close(struct msm_file_private *ctx);
407 
408 void msm_submitqueue_destroy(struct kref *kref);
409 
410 
411 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
412 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
413 
414 static inline int align_pitch(int width, int bpp)
415 {
416 	int bytespp = (bpp + 7) / 8;
417 	/* adreno needs pitch aligned to 32 pixels: */
418 	return bytespp * ALIGN(width, 32);
419 }
420 
421 /* for the generated headers: */
422 #define INVALID_IDX(idx) ({BUG(); 0;})
423 #define fui(x)                ({BUG(); 0;})
424 #define util_float_to_half(x) ({BUG(); 0;})
425 
426 
427 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
428 
429 /* for conditionally setting boolean flag(s): */
430 #define COND(bool, val) ((bool) ? (val) : 0)
431 
432 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
433 {
434 	ktime_t now = ktime_get();
435 	unsigned long remaining_jiffies;
436 
437 	if (ktime_compare(*timeout, now) < 0) {
438 		remaining_jiffies = 0;
439 	} else {
440 		ktime_t rem = ktime_sub(*timeout, now);
441 		struct timespec ts = ktime_to_timespec(rem);
442 		remaining_jiffies = timespec_to_jiffies(&ts);
443 	}
444 
445 	return remaining_jiffies;
446 }
447 
448 #endif /* __MSM_DRV_H__ */
449