1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRV_H__ 19 #define __MSM_DRV_H__ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/module.h> 25 #include <linux/component.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/list.h> 31 #include <linux/iommu.h> 32 #include <linux/types.h> 33 #include <asm/sizes.h> 34 35 #ifndef CONFIG_OF 36 #include <mach/board.h> 37 #include <mach/socinfo.h> 38 #include <mach/iommu_domains.h> 39 #endif 40 41 #include <drm/drmP.h> 42 #include <drm/drm_atomic.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_crtc_helper.h> 45 #include <drm/drm_plane_helper.h> 46 #include <drm/drm_fb_helper.h> 47 #include <drm/msm_drm.h> 48 #include <drm/drm_gem.h> 49 50 struct msm_kms; 51 struct msm_gpu; 52 struct msm_mmu; 53 struct msm_rd_state; 54 struct msm_perf_state; 55 struct msm_gem_submit; 56 57 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 58 59 struct msm_file_private { 60 /* currently we don't do anything useful with this.. but when 61 * per-context address spaces are supported we'd keep track of 62 * the context's page-tables here. 63 */ 64 int dummy; 65 }; 66 67 struct msm_drm_private { 68 69 struct msm_kms *kms; 70 71 /* subordinate devices, if present: */ 72 struct platform_device *gpu_pdev; 73 74 /* possibly this should be in the kms component, but it is 75 * shared by both mdp4 and mdp5.. 76 */ 77 struct hdmi *hdmi; 78 79 /* when we have more than one 'msm_gpu' these need to be an array: */ 80 struct msm_gpu *gpu; 81 struct msm_file_private *lastctx; 82 83 struct drm_fb_helper *fbdev; 84 85 uint32_t next_fence, completed_fence; 86 wait_queue_head_t fence_event; 87 88 struct msm_rd_state *rd; 89 struct msm_perf_state *perf; 90 91 /* list of GEM objects: */ 92 struct list_head inactive_list; 93 94 struct workqueue_struct *wq; 95 96 /* callbacks deferred until bo is inactive: */ 97 struct list_head fence_cbs; 98 99 /* crtcs pending async atomic updates: */ 100 uint32_t pending_crtcs; 101 wait_queue_head_t pending_crtcs_event; 102 103 /* registered MMUs: */ 104 unsigned int num_mmus; 105 struct msm_mmu *mmus[NUM_DOMAINS]; 106 107 unsigned int num_planes; 108 struct drm_plane *planes[8]; 109 110 unsigned int num_crtcs; 111 struct drm_crtc *crtcs[8]; 112 113 unsigned int num_encoders; 114 struct drm_encoder *encoders[8]; 115 116 unsigned int num_bridges; 117 struct drm_bridge *bridges[8]; 118 119 unsigned int num_connectors; 120 struct drm_connector *connectors[8]; 121 122 /* VRAM carveout, used when no IOMMU: */ 123 struct { 124 unsigned long size; 125 dma_addr_t paddr; 126 /* NOTE: mm managed at the page level, size is in # of pages 127 * and position mm_node->start is in # of pages: 128 */ 129 struct drm_mm mm; 130 } vram; 131 }; 132 133 struct msm_format { 134 uint32_t pixel_format; 135 }; 136 137 /* callback from wq once fence has passed: */ 138 struct msm_fence_cb { 139 struct work_struct work; 140 uint32_t fence; 141 void (*func)(struct msm_fence_cb *cb); 142 }; 143 144 void __msm_fence_worker(struct work_struct *work); 145 146 #define INIT_FENCE_CB(_cb, _func) do { \ 147 INIT_WORK(&(_cb)->work, __msm_fence_worker); \ 148 (_cb)->func = _func; \ 149 } while (0) 150 151 int msm_atomic_commit(struct drm_device *dev, 152 struct drm_atomic_state *state, bool async); 153 154 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 155 156 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, 157 struct timespec *timeout); 158 int msm_queue_fence_cb(struct drm_device *dev, 159 struct msm_fence_cb *cb, uint32_t fence); 160 void msm_update_fence(struct drm_device *dev, uint32_t fence); 161 162 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 163 struct drm_file *file); 164 165 int msm_gem_mmap_obj(struct drm_gem_object *obj, 166 struct vm_area_struct *vma); 167 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 168 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 169 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 170 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 171 uint32_t *iova); 172 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 173 uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); 174 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 175 void msm_gem_put_pages(struct drm_gem_object *obj); 176 void msm_gem_put_iova(struct drm_gem_object *obj, int id); 177 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 178 struct drm_mode_create_dumb *args); 179 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 180 uint32_t handle, uint64_t *offset); 181 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 182 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 183 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 184 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 185 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 186 struct dma_buf_attachment *attach, struct sg_table *sg); 187 int msm_gem_prime_pin(struct drm_gem_object *obj); 188 void msm_gem_prime_unpin(struct drm_gem_object *obj); 189 void *msm_gem_vaddr_locked(struct drm_gem_object *obj); 190 void *msm_gem_vaddr(struct drm_gem_object *obj); 191 int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, 192 struct msm_fence_cb *cb); 193 void msm_gem_move_to_active(struct drm_gem_object *obj, 194 struct msm_gpu *gpu, bool write, uint32_t fence); 195 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 196 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, 197 struct timespec *timeout); 198 int msm_gem_cpu_fini(struct drm_gem_object *obj); 199 void msm_gem_free_object(struct drm_gem_object *obj); 200 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 201 uint32_t size, uint32_t flags, uint32_t *handle); 202 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 203 uint32_t size, uint32_t flags); 204 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 205 uint32_t size, struct sg_table *sgt); 206 207 int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); 208 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); 209 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); 210 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 211 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 212 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 213 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 214 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 215 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd); 216 217 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 218 219 struct hdmi; 220 int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 221 struct drm_encoder *encoder); 222 void __init hdmi_register(void); 223 void __exit hdmi_unregister(void); 224 225 #ifdef CONFIG_DEBUG_FS 226 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 227 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 228 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 229 int msm_debugfs_late_init(struct drm_device *dev); 230 int msm_rd_debugfs_init(struct drm_minor *minor); 231 void msm_rd_debugfs_cleanup(struct drm_minor *minor); 232 void msm_rd_dump_submit(struct msm_gem_submit *submit); 233 int msm_perf_debugfs_init(struct drm_minor *minor); 234 void msm_perf_debugfs_cleanup(struct drm_minor *minor); 235 #else 236 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 237 static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} 238 #endif 239 240 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 241 const char *dbgname); 242 void msm_writel(u32 data, void __iomem *addr); 243 u32 msm_readl(const void __iomem *addr); 244 245 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 246 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 247 248 static inline bool fence_completed(struct drm_device *dev, uint32_t fence) 249 { 250 struct msm_drm_private *priv = dev->dev_private; 251 return priv->completed_fence >= fence; 252 } 253 254 static inline int align_pitch(int width, int bpp) 255 { 256 int bytespp = (bpp + 7) / 8; 257 /* adreno needs pitch aligned to 32 pixels: */ 258 return bytespp * ALIGN(width, 32); 259 } 260 261 /* for the generated headers: */ 262 #define INVALID_IDX(idx) ({BUG(); 0;}) 263 #define fui(x) ({BUG(); 0;}) 264 #define util_float_to_half(x) ({BUG(); 0;}) 265 266 267 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 268 269 /* for conditionally setting boolean flag(s): */ 270 #define COND(bool, val) ((bool) ? (val) : 0) 271 272 273 #endif /* __MSM_DRV_H__ */ 274