1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRV_H__ 19 #define __MSM_DRV_H__ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/module.h> 25 #include <linux/component.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/list.h> 31 #include <linux/iommu.h> 32 #include <linux/types.h> 33 #include <linux/of_graph.h> 34 #include <linux/of_device.h> 35 #include <asm/sizes.h> 36 37 #include <drm/drmP.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_fb_helper.h> 43 #include <drm/msm_drm.h> 44 #include <drm/drm_gem.h> 45 46 struct msm_kms; 47 struct msm_gpu; 48 struct msm_mmu; 49 struct msm_mdss; 50 struct msm_rd_state; 51 struct msm_perf_state; 52 struct msm_gem_submit; 53 struct msm_fence_context; 54 struct msm_fence_cb; 55 56 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 57 58 struct msm_file_private { 59 /* currently we don't do anything useful with this.. but when 60 * per-context address spaces are supported we'd keep track of 61 * the context's page-tables here. 62 */ 63 int dummy; 64 }; 65 66 enum msm_mdp_plane_property { 67 PLANE_PROP_ZPOS, 68 PLANE_PROP_ALPHA, 69 PLANE_PROP_PREMULTIPLIED, 70 PLANE_PROP_MAX_NUM 71 }; 72 73 struct msm_vblank_ctrl { 74 struct work_struct work; 75 struct list_head event_list; 76 spinlock_t lock; 77 }; 78 79 struct msm_drm_private { 80 81 struct drm_device *dev; 82 83 struct msm_kms *kms; 84 85 /* subordinate devices, if present: */ 86 struct platform_device *gpu_pdev; 87 88 /* top level MDSS wrapper device (for MDP5 only) */ 89 struct msm_mdss *mdss; 90 91 /* possibly this should be in the kms component, but it is 92 * shared by both mdp4 and mdp5.. 93 */ 94 struct hdmi *hdmi; 95 96 /* eDP is for mdp5 only, but kms has not been created 97 * when edp_bind() and edp_init() are called. Here is the only 98 * place to keep the edp instance. 99 */ 100 struct msm_edp *edp; 101 102 /* DSI is shared by mdp4 and mdp5 */ 103 struct msm_dsi *dsi[2]; 104 105 /* when we have more than one 'msm_gpu' these need to be an array: */ 106 struct msm_gpu *gpu; 107 struct msm_file_private *lastctx; 108 109 struct drm_fb_helper *fbdev; 110 111 struct msm_rd_state *rd; 112 struct msm_perf_state *perf; 113 114 /* list of GEM objects: */ 115 struct list_head inactive_list; 116 117 struct workqueue_struct *wq; 118 struct workqueue_struct *atomic_wq; 119 120 /* crtcs pending async atomic updates: */ 121 uint32_t pending_crtcs; 122 wait_queue_head_t pending_crtcs_event; 123 124 /* registered MMUs: */ 125 unsigned int num_mmus; 126 struct msm_mmu *mmus[NUM_DOMAINS]; 127 128 unsigned int num_planes; 129 struct drm_plane *planes[8]; 130 131 unsigned int num_crtcs; 132 struct drm_crtc *crtcs[8]; 133 134 unsigned int num_encoders; 135 struct drm_encoder *encoders[8]; 136 137 unsigned int num_bridges; 138 struct drm_bridge *bridges[8]; 139 140 unsigned int num_connectors; 141 struct drm_connector *connectors[8]; 142 143 /* Properties */ 144 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 145 146 /* VRAM carveout, used when no IOMMU: */ 147 struct { 148 unsigned long size; 149 dma_addr_t paddr; 150 /* NOTE: mm managed at the page level, size is in # of pages 151 * and position mm_node->start is in # of pages: 152 */ 153 struct drm_mm mm; 154 } vram; 155 156 struct notifier_block vmap_notifier; 157 struct shrinker shrinker; 158 159 struct msm_vblank_ctrl vblank_ctrl; 160 161 /* task holding struct_mutex.. currently only used in submit path 162 * to detect and reject faults from copy_from_user() for submit 163 * ioctl. 164 */ 165 struct task_struct *struct_mutex_task; 166 }; 167 168 struct msm_format { 169 uint32_t pixel_format; 170 }; 171 172 int msm_atomic_check(struct drm_device *dev, 173 struct drm_atomic_state *state); 174 int msm_atomic_commit(struct drm_device *dev, 175 struct drm_atomic_state *state, bool nonblock); 176 177 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 178 179 void msm_gem_submit_free(struct msm_gem_submit *submit); 180 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 181 struct drm_file *file); 182 183 void msm_gem_shrinker_init(struct drm_device *dev); 184 void msm_gem_shrinker_cleanup(struct drm_device *dev); 185 186 int msm_gem_mmap_obj(struct drm_gem_object *obj, 187 struct vm_area_struct *vma); 188 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 189 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 190 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 191 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 192 uint32_t *iova); 193 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 194 uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); 195 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 196 void msm_gem_put_pages(struct drm_gem_object *obj); 197 void msm_gem_put_iova(struct drm_gem_object *obj, int id); 198 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 199 struct drm_mode_create_dumb *args); 200 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 201 uint32_t handle, uint64_t *offset); 202 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 203 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 204 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 205 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 206 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 207 struct dma_buf_attachment *attach, struct sg_table *sg); 208 int msm_gem_prime_pin(struct drm_gem_object *obj); 209 void msm_gem_prime_unpin(struct drm_gem_object *obj); 210 void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj); 211 void *msm_gem_get_vaddr(struct drm_gem_object *obj); 212 void msm_gem_put_vaddr_locked(struct drm_gem_object *obj); 213 void msm_gem_put_vaddr(struct drm_gem_object *obj); 214 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 215 void msm_gem_purge(struct drm_gem_object *obj); 216 void msm_gem_vunmap(struct drm_gem_object *obj); 217 int msm_gem_sync_object(struct drm_gem_object *obj, 218 struct msm_fence_context *fctx, bool exclusive); 219 void msm_gem_move_to_active(struct drm_gem_object *obj, 220 struct msm_gpu *gpu, bool exclusive, struct fence *fence); 221 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 222 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 223 int msm_gem_cpu_fini(struct drm_gem_object *obj); 224 void msm_gem_free_object(struct drm_gem_object *obj); 225 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 226 uint32_t size, uint32_t flags, uint32_t *handle); 227 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 228 uint32_t size, uint32_t flags); 229 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 230 struct dma_buf *dmabuf, struct sg_table *sgt); 231 232 int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); 233 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); 234 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); 235 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 236 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 237 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 238 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 239 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 240 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 241 242 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 243 void msm_fbdev_free(struct drm_device *dev); 244 245 struct hdmi; 246 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 247 struct drm_encoder *encoder); 248 void __init msm_hdmi_register(void); 249 void __exit msm_hdmi_unregister(void); 250 251 struct msm_edp; 252 void __init msm_edp_register(void); 253 void __exit msm_edp_unregister(void); 254 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 255 struct drm_encoder *encoder); 256 257 struct msm_dsi; 258 enum msm_dsi_encoder_id { 259 MSM_DSI_VIDEO_ENCODER_ID = 0, 260 MSM_DSI_CMD_ENCODER_ID = 1, 261 MSM_DSI_ENCODER_NUM = 2 262 }; 263 #ifdef CONFIG_DRM_MSM_DSI 264 void __init msm_dsi_register(void); 265 void __exit msm_dsi_unregister(void); 266 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 267 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); 268 #else 269 static inline void __init msm_dsi_register(void) 270 { 271 } 272 static inline void __exit msm_dsi_unregister(void) 273 { 274 } 275 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 276 struct drm_device *dev, 277 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) 278 { 279 return -EINVAL; 280 } 281 #endif 282 283 void __init msm_mdp_register(void); 284 void __exit msm_mdp_unregister(void); 285 286 #ifdef CONFIG_DEBUG_FS 287 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 288 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 289 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 290 int msm_debugfs_late_init(struct drm_device *dev); 291 int msm_rd_debugfs_init(struct drm_minor *minor); 292 void msm_rd_debugfs_cleanup(struct drm_minor *minor); 293 void msm_rd_dump_submit(struct msm_gem_submit *submit); 294 int msm_perf_debugfs_init(struct drm_minor *minor); 295 void msm_perf_debugfs_cleanup(struct drm_minor *minor); 296 #else 297 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 298 static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} 299 #endif 300 301 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 302 const char *dbgname); 303 void msm_writel(u32 data, void __iomem *addr); 304 u32 msm_readl(const void __iomem *addr); 305 306 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 307 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 308 309 static inline int align_pitch(int width, int bpp) 310 { 311 int bytespp = (bpp + 7) / 8; 312 /* adreno needs pitch aligned to 32 pixels: */ 313 return bytespp * ALIGN(width, 32); 314 } 315 316 /* for the generated headers: */ 317 #define INVALID_IDX(idx) ({BUG(); 0;}) 318 #define fui(x) ({BUG(); 0;}) 319 #define util_float_to_half(x) ({BUG(); 0;}) 320 321 322 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 323 324 /* for conditionally setting boolean flag(s): */ 325 #define COND(bool, val) ((bool) ? (val) : 0) 326 327 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 328 { 329 ktime_t now = ktime_get(); 330 unsigned long remaining_jiffies; 331 332 if (ktime_compare(*timeout, now) < 0) { 333 remaining_jiffies = 0; 334 } else { 335 ktime_t rem = ktime_sub(*timeout, now); 336 struct timespec ts = ktime_to_timespec(rem); 337 remaining_jiffies = timespec_to_jiffies(&ts); 338 } 339 340 return remaining_jiffies; 341 } 342 343 #endif /* __MSM_DRV_H__ */ 344