1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/module.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/list.h> 21 #include <linux/iommu.h> 22 #include <linux/types.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_device.h> 25 #include <linux/sizes.h> 26 #include <linux/kthread.h> 27 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/display/drm_dsc.h> 34 #include <drm/msm_drm.h> 35 #include <drm/drm_gem.h> 36 37 struct msm_kms; 38 struct msm_gpu; 39 struct msm_mmu; 40 struct msm_mdss; 41 struct msm_rd_state; 42 struct msm_perf_state; 43 struct msm_gem_submit; 44 struct msm_fence_context; 45 struct msm_gem_address_space; 46 struct msm_gem_vma; 47 struct msm_disp_state; 48 49 #define MAX_CRTCS 8 50 #define MAX_BRIDGES 8 51 52 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 53 54 enum msm_dp_controller { 55 MSM_DP_CONTROLLER_0, 56 MSM_DP_CONTROLLER_1, 57 MSM_DP_CONTROLLER_2, 58 MSM_DP_CONTROLLER_COUNT, 59 }; 60 61 #define MSM_GPU_MAX_RINGS 4 62 #define MAX_H_TILES_PER_DISPLAY 2 63 64 /** 65 * enum msm_display_caps - features/capabilities supported by displays 66 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 67 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 68 */ 69 enum msm_display_caps { 70 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 71 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 72 }; 73 74 /** 75 * enum msm_event_wait - type of HW events to wait for 76 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 77 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 78 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 79 */ 80 enum msm_event_wait { 81 MSM_ENC_COMMIT_DONE = 0, 82 MSM_ENC_TX_COMPLETE, 83 MSM_ENC_VBLANK, 84 }; 85 86 /** 87 * struct msm_display_topology - defines a display topology pipeline 88 * @num_lm: number of layer mixers used 89 * @num_enc: number of compression encoder blocks used 90 * @num_intf: number of interfaces the panel is mounted on 91 * @num_dspp: number of dspp blocks used 92 * @num_dsc: number of Display Stream Compression (DSC) blocks used 93 */ 94 struct msm_display_topology { 95 u32 num_lm; 96 u32 num_enc; 97 u32 num_intf; 98 u32 num_dspp; 99 u32 num_dsc; 100 }; 101 102 /* Commit/Event thread specific structure */ 103 struct msm_drm_thread { 104 struct drm_device *dev; 105 unsigned int crtc_id; 106 struct kthread_worker *worker; 107 }; 108 109 /* DSC config */ 110 struct msm_display_dsc_config { 111 struct drm_dsc_config *drm; 112 }; 113 114 struct msm_drm_private { 115 116 struct drm_device *dev; 117 118 struct msm_kms *kms; 119 int (*kms_init)(struct drm_device *dev); 120 121 /* subordinate devices, if present: */ 122 struct platform_device *gpu_pdev; 123 124 /* possibly this should be in the kms component, but it is 125 * shared by both mdp4 and mdp5.. 126 */ 127 struct hdmi *hdmi; 128 129 /* DSI is shared by mdp4 and mdp5 */ 130 struct msm_dsi *dsi[2]; 131 132 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 133 134 /* when we have more than one 'msm_gpu' these need to be an array: */ 135 struct msm_gpu *gpu; 136 137 /* gpu is only set on open(), but we need this info earlier */ 138 bool is_a2xx; 139 bool has_cached_coherent; 140 141 struct drm_fb_helper *fbdev; 142 143 struct msm_rd_state *rd; /* debugfs to dump all submits */ 144 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 145 struct msm_perf_state *perf; 146 147 /** 148 * List of all GEM objects (mainly for debugfs, protected by obj_lock 149 * (acquire before per GEM object lock) 150 */ 151 struct list_head objects; 152 struct mutex obj_lock; 153 154 /** 155 * LRUs of inactive GEM objects. Every bo is either in one of the 156 * inactive lists (depending on whether or not it is shrinkable) or 157 * gpu->active_list (for the gpu it is active on[1]), or transiently 158 * on a temporary list as the shrinker is running. 159 * 160 * Note that inactive_willneed also contains pinned and vmap'd bos, 161 * but the number of pinned-but-not-active objects is small (scanout 162 * buffers, ringbuffer, etc). 163 * 164 * These lists are protected by mm_lock (which should be acquired 165 * before per GEM object lock). One should *not* hold mm_lock in 166 * get_pages()/vmap()/etc paths, as they can trigger the shrinker. 167 * 168 * [1] if someone ever added support for the old 2d cores, there could be 169 * more than one gpu object 170 */ 171 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */ 172 struct list_head inactive_dontneed; /* inactive + shrinkable */ 173 struct list_head inactive_unpinned; /* inactive + purged or unpinned */ 174 long shrinkable_count; /* write access under mm_lock */ 175 long evictable_count; /* write access under mm_lock */ 176 struct mutex mm_lock; 177 178 struct workqueue_struct *wq; 179 180 unsigned int num_crtcs; 181 struct drm_crtc *crtcs[MAX_CRTCS]; 182 183 struct msm_drm_thread event_thread[MAX_CRTCS]; 184 185 unsigned int num_bridges; 186 struct drm_bridge *bridges[MAX_BRIDGES]; 187 188 /* VRAM carveout, used when no IOMMU: */ 189 struct { 190 unsigned long size; 191 dma_addr_t paddr; 192 /* NOTE: mm managed at the page level, size is in # of pages 193 * and position mm_node->start is in # of pages: 194 */ 195 struct drm_mm mm; 196 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 197 } vram; 198 199 struct notifier_block vmap_notifier; 200 struct shrinker shrinker; 201 202 struct drm_atomic_state *pm_state; 203 204 /* For hang detection, in ms */ 205 unsigned int hangcheck_period; 206 207 /** 208 * disable_err_irq: 209 * 210 * Disable handling of GPU hw error interrupts, to force fallback to 211 * sw hangcheck timer. Written (via debugfs) by igt tests to test 212 * the sw hangcheck mechanism. 213 */ 214 bool disable_err_irq; 215 }; 216 217 struct msm_format { 218 uint32_t pixel_format; 219 }; 220 221 struct msm_pending_timer; 222 223 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 224 struct msm_kms *kms, int crtc_idx); 225 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 226 void msm_atomic_commit_tail(struct drm_atomic_state *state); 227 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 228 void msm_atomic_state_clear(struct drm_atomic_state *state); 229 void msm_atomic_state_free(struct drm_atomic_state *state); 230 231 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 232 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 233 234 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 235 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 236 237 bool msm_use_mmu(struct drm_device *dev); 238 239 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 240 struct drm_file *file); 241 242 #ifdef CONFIG_DEBUG_FS 243 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 244 #endif 245 246 void msm_gem_shrinker_init(struct drm_device *dev); 247 void msm_gem_shrinker_cleanup(struct drm_device *dev); 248 249 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 250 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 251 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 252 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 253 struct dma_buf_attachment *attach, struct sg_table *sg); 254 int msm_gem_prime_pin(struct drm_gem_object *obj); 255 void msm_gem_prime_unpin(struct drm_gem_object *obj); 256 257 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 258 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 259 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 260 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 261 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 262 struct msm_gem_address_space *aspace, int plane); 263 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 264 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 265 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 266 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 267 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 268 int w, int h, int p, uint32_t format); 269 270 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 271 void msm_fbdev_free(struct drm_device *dev); 272 273 struct hdmi; 274 #ifdef CONFIG_DRM_MSM_HDMI 275 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 276 struct drm_encoder *encoder); 277 void __init msm_hdmi_register(void); 278 void __exit msm_hdmi_unregister(void); 279 #else 280 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 281 struct drm_encoder *encoder) 282 { 283 return -EINVAL; 284 } 285 static inline void __init msm_hdmi_register(void) {} 286 static inline void __exit msm_hdmi_unregister(void) {} 287 #endif 288 289 struct msm_dsi; 290 #ifdef CONFIG_DRM_MSM_DSI 291 int dsi_dev_attach(struct platform_device *pdev); 292 void dsi_dev_detach(struct platform_device *pdev); 293 void __init msm_dsi_register(void); 294 void __exit msm_dsi_unregister(void); 295 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 296 struct drm_encoder *encoder); 297 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 298 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 299 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 300 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 301 struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 302 #else 303 static inline void __init msm_dsi_register(void) 304 { 305 } 306 static inline void __exit msm_dsi_unregister(void) 307 { 308 } 309 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 310 struct drm_device *dev, 311 struct drm_encoder *encoder) 312 { 313 return -EINVAL; 314 } 315 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 316 { 317 } 318 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 319 { 320 return false; 321 } 322 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 323 { 324 return false; 325 } 326 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 327 { 328 return false; 329 } 330 331 static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 332 { 333 return NULL; 334 } 335 #endif 336 337 #ifdef CONFIG_DRM_MSM_DP 338 int __init msm_dp_register(void); 339 void __exit msm_dp_unregister(void); 340 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 341 struct drm_encoder *encoder); 342 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 343 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 344 345 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 346 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 347 348 #else 349 static inline int __init msm_dp_register(void) 350 { 351 return -EINVAL; 352 } 353 static inline void __exit msm_dp_unregister(void) 354 { 355 } 356 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 357 struct drm_device *dev, 358 struct drm_encoder *encoder) 359 { 360 return -EINVAL; 361 } 362 363 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 364 { 365 } 366 367 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 368 { 369 } 370 371 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 372 struct drm_minor *minor) 373 { 374 } 375 376 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 377 { 378 return false; 379 } 380 381 #endif 382 383 #ifdef CONFIG_DRM_MSM_MDP4 384 void msm_mdp4_register(void); 385 void msm_mdp4_unregister(void); 386 #else 387 static inline void msm_mdp4_register(void) {} 388 static inline void msm_mdp4_unregister(void) {} 389 #endif 390 391 #ifdef CONFIG_DRM_MSM_MDP5 392 void msm_mdp_register(void); 393 void msm_mdp_unregister(void); 394 #else 395 static inline void msm_mdp_register(void) {} 396 static inline void msm_mdp_unregister(void) {} 397 #endif 398 399 #ifdef CONFIG_DRM_MSM_DPU 400 void msm_dpu_register(void); 401 void msm_dpu_unregister(void); 402 #else 403 static inline void msm_dpu_register(void) {} 404 static inline void msm_dpu_unregister(void) {} 405 #endif 406 407 #ifdef CONFIG_DRM_MSM_MDSS 408 void msm_mdss_register(void); 409 void msm_mdss_unregister(void); 410 #else 411 static inline void msm_mdss_register(void) {} 412 static inline void msm_mdss_unregister(void) {} 413 #endif 414 415 #ifdef CONFIG_DEBUG_FS 416 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 417 int msm_debugfs_late_init(struct drm_device *dev); 418 int msm_rd_debugfs_init(struct drm_minor *minor); 419 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 420 __printf(3, 4) 421 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 422 const char *fmt, ...); 423 int msm_perf_debugfs_init(struct drm_minor *minor); 424 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 425 #else 426 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 427 __printf(3, 4) 428 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 429 struct msm_gem_submit *submit, 430 const char *fmt, ...) {} 431 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 432 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 433 #endif 434 435 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 436 437 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 438 const char *name); 439 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 440 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 441 phys_addr_t *size); 442 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 443 444 #define msm_writel(data, addr) writel((data), (addr)) 445 #define msm_readl(addr) readl((addr)) 446 447 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 448 { 449 u32 val = msm_readl(addr); 450 451 val &= ~mask; 452 msm_writel(val | or, addr); 453 } 454 455 /** 456 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 457 * 458 * @timer: hrtimer to control when the kthread work is triggered 459 * @work: the kthread work 460 * @worker: the kthread worker the work will be scheduled on 461 */ 462 struct msm_hrtimer_work { 463 struct hrtimer timer; 464 struct kthread_work work; 465 struct kthread_worker *worker; 466 }; 467 468 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 469 ktime_t wakeup_time, 470 enum hrtimer_mode mode); 471 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 472 struct kthread_worker *worker, 473 kthread_work_func_t fn, 474 clockid_t clock_id, 475 enum hrtimer_mode mode); 476 477 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 478 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 479 480 static inline int align_pitch(int width, int bpp) 481 { 482 int bytespp = (bpp + 7) / 8; 483 /* adreno needs pitch aligned to 32 pixels: */ 484 return bytespp * ALIGN(width, 32); 485 } 486 487 /* for the generated headers: */ 488 #define INVALID_IDX(idx) ({BUG(); 0;}) 489 #define fui(x) ({BUG(); 0;}) 490 #define _mesa_float_to_half(x) ({BUG(); 0;}) 491 492 493 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 494 495 /* for conditionally setting boolean flag(s): */ 496 #define COND(bool, val) ((bool) ? (val) : 0) 497 498 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 499 { 500 ktime_t now = ktime_get(); 501 s64 remaining_jiffies; 502 503 if (ktime_compare(*timeout, now) < 0) { 504 remaining_jiffies = 0; 505 } else { 506 ktime_t rem = ktime_sub(*timeout, now); 507 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 508 } 509 510 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX); 511 } 512 513 /* Driver helpers */ 514 515 extern const struct component_master_ops msm_drm_ops; 516 517 int msm_pm_prepare(struct device *dev); 518 void msm_pm_complete(struct device *dev); 519 520 int msm_drv_probe(struct device *dev, 521 int (*kms_init)(struct drm_device *dev)); 522 void msm_drv_shutdown(struct platform_device *pdev); 523 524 525 #endif /* __MSM_DRV_H__ */ 526