1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/module.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/list.h> 21 #include <linux/iommu.h> 22 #include <linux/types.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_device.h> 25 #include <linux/sizes.h> 26 #include <linux/kthread.h> 27 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/display/drm_dsc.h> 34 #include <drm/msm_drm.h> 35 #include <drm/drm_gem.h> 36 37 struct msm_kms; 38 struct msm_gpu; 39 struct msm_mmu; 40 struct msm_mdss; 41 struct msm_rd_state; 42 struct msm_perf_state; 43 struct msm_gem_submit; 44 struct msm_fence_context; 45 struct msm_gem_address_space; 46 struct msm_gem_vma; 47 struct msm_disp_state; 48 49 #define MAX_CRTCS 8 50 #define MAX_BRIDGES 8 51 52 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 53 54 enum msm_dp_controller { 55 MSM_DP_CONTROLLER_0, 56 MSM_DP_CONTROLLER_1, 57 MSM_DP_CONTROLLER_2, 58 MSM_DP_CONTROLLER_COUNT, 59 }; 60 61 #define MSM_GPU_MAX_RINGS 4 62 #define MAX_H_TILES_PER_DISPLAY 2 63 64 /** 65 * enum msm_event_wait - type of HW events to wait for 66 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 67 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 68 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 69 */ 70 enum msm_event_wait { 71 MSM_ENC_COMMIT_DONE = 0, 72 MSM_ENC_TX_COMPLETE, 73 MSM_ENC_VBLANK, 74 }; 75 76 /** 77 * struct msm_display_topology - defines a display topology pipeline 78 * @num_lm: number of layer mixers used 79 * @num_enc: number of compression encoder blocks used 80 * @num_intf: number of interfaces the panel is mounted on 81 * @num_dspp: number of dspp blocks used 82 * @num_dsc: number of Display Stream Compression (DSC) blocks used 83 */ 84 struct msm_display_topology { 85 u32 num_lm; 86 u32 num_enc; 87 u32 num_intf; 88 u32 num_dspp; 89 u32 num_dsc; 90 }; 91 92 /* Commit/Event thread specific structure */ 93 struct msm_drm_thread { 94 struct drm_device *dev; 95 unsigned int crtc_id; 96 struct kthread_worker *worker; 97 }; 98 99 /* DSC config */ 100 struct msm_display_dsc_config { 101 struct drm_dsc_config *drm; 102 }; 103 104 struct msm_drm_private { 105 106 struct drm_device *dev; 107 108 struct msm_kms *kms; 109 int (*kms_init)(struct drm_device *dev); 110 111 /* subordinate devices, if present: */ 112 struct platform_device *gpu_pdev; 113 114 /* possibly this should be in the kms component, but it is 115 * shared by both mdp4 and mdp5.. 116 */ 117 struct hdmi *hdmi; 118 119 /* DSI is shared by mdp4 and mdp5 */ 120 struct msm_dsi *dsi[2]; 121 122 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 123 124 /* when we have more than one 'msm_gpu' these need to be an array: */ 125 struct msm_gpu *gpu; 126 127 /* gpu is only set on open(), but we need this info earlier */ 128 bool is_a2xx; 129 bool has_cached_coherent; 130 131 struct drm_fb_helper *fbdev; 132 133 struct msm_rd_state *rd; /* debugfs to dump all submits */ 134 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 135 struct msm_perf_state *perf; 136 137 /** 138 * List of all GEM objects (mainly for debugfs, protected by obj_lock 139 * (acquire before per GEM object lock) 140 */ 141 struct list_head objects; 142 struct mutex obj_lock; 143 144 /** 145 * LRUs of inactive GEM objects. Every bo is either in one of the 146 * inactive lists (depending on whether or not it is shrinkable) or 147 * gpu->active_list (for the gpu it is active on[1]), or transiently 148 * on a temporary list as the shrinker is running. 149 * 150 * Note that inactive_willneed also contains pinned and vmap'd bos, 151 * but the number of pinned-but-not-active objects is small (scanout 152 * buffers, ringbuffer, etc). 153 * 154 * These lists are protected by mm_lock (which should be acquired 155 * before per GEM object lock). One should *not* hold mm_lock in 156 * get_pages()/vmap()/etc paths, as they can trigger the shrinker. 157 * 158 * [1] if someone ever added support for the old 2d cores, there could be 159 * more than one gpu object 160 */ 161 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */ 162 struct list_head inactive_dontneed; /* inactive + shrinkable */ 163 struct list_head inactive_unpinned; /* inactive + purged or unpinned */ 164 long shrinkable_count; /* write access under mm_lock */ 165 long evictable_count; /* write access under mm_lock */ 166 struct mutex mm_lock; 167 168 struct workqueue_struct *wq; 169 170 unsigned int num_crtcs; 171 struct drm_crtc *crtcs[MAX_CRTCS]; 172 173 struct msm_drm_thread event_thread[MAX_CRTCS]; 174 175 unsigned int num_bridges; 176 struct drm_bridge *bridges[MAX_BRIDGES]; 177 178 /* VRAM carveout, used when no IOMMU: */ 179 struct { 180 unsigned long size; 181 dma_addr_t paddr; 182 /* NOTE: mm managed at the page level, size is in # of pages 183 * and position mm_node->start is in # of pages: 184 */ 185 struct drm_mm mm; 186 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 187 } vram; 188 189 struct notifier_block vmap_notifier; 190 struct shrinker shrinker; 191 192 struct drm_atomic_state *pm_state; 193 194 /* For hang detection, in ms */ 195 unsigned int hangcheck_period; 196 197 /** 198 * disable_err_irq: 199 * 200 * Disable handling of GPU hw error interrupts, to force fallback to 201 * sw hangcheck timer. Written (via debugfs) by igt tests to test 202 * the sw hangcheck mechanism. 203 */ 204 bool disable_err_irq; 205 }; 206 207 struct msm_format { 208 uint32_t pixel_format; 209 }; 210 211 struct msm_pending_timer; 212 213 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 214 struct msm_kms *kms, int crtc_idx); 215 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 216 void msm_atomic_commit_tail(struct drm_atomic_state *state); 217 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 218 void msm_atomic_state_clear(struct drm_atomic_state *state); 219 void msm_atomic_state_free(struct drm_atomic_state *state); 220 221 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 222 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 223 224 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 225 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 226 227 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 228 bool msm_use_mmu(struct drm_device *dev); 229 230 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 231 struct drm_file *file); 232 233 #ifdef CONFIG_DEBUG_FS 234 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 235 #endif 236 237 void msm_gem_shrinker_init(struct drm_device *dev); 238 void msm_gem_shrinker_cleanup(struct drm_device *dev); 239 240 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 241 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 242 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 243 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 244 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 245 struct dma_buf_attachment *attach, struct sg_table *sg); 246 int msm_gem_prime_pin(struct drm_gem_object *obj); 247 void msm_gem_prime_unpin(struct drm_gem_object *obj); 248 249 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 250 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 251 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 252 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 253 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 254 struct msm_gem_address_space *aspace, int plane); 255 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 256 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 257 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 258 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 259 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 260 int w, int h, int p, uint32_t format); 261 262 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 263 void msm_fbdev_free(struct drm_device *dev); 264 265 struct hdmi; 266 #ifdef CONFIG_DRM_MSM_HDMI 267 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 268 struct drm_encoder *encoder); 269 void __init msm_hdmi_register(void); 270 void __exit msm_hdmi_unregister(void); 271 #else 272 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 273 struct drm_encoder *encoder) 274 { 275 return -EINVAL; 276 } 277 static inline void __init msm_hdmi_register(void) {} 278 static inline void __exit msm_hdmi_unregister(void) {} 279 #endif 280 281 struct msm_dsi; 282 #ifdef CONFIG_DRM_MSM_DSI 283 int dsi_dev_attach(struct platform_device *pdev); 284 void dsi_dev_detach(struct platform_device *pdev); 285 void __init msm_dsi_register(void); 286 void __exit msm_dsi_unregister(void); 287 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 288 struct drm_encoder *encoder); 289 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 290 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 291 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 292 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 293 struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 294 #else 295 static inline void __init msm_dsi_register(void) 296 { 297 } 298 static inline void __exit msm_dsi_unregister(void) 299 { 300 } 301 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 302 struct drm_device *dev, 303 struct drm_encoder *encoder) 304 { 305 return -EINVAL; 306 } 307 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 308 { 309 } 310 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 311 { 312 return false; 313 } 314 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 315 { 316 return false; 317 } 318 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 319 { 320 return false; 321 } 322 323 static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 324 { 325 return NULL; 326 } 327 #endif 328 329 #ifdef CONFIG_DRM_MSM_DP 330 int __init msm_dp_register(void); 331 void __exit msm_dp_unregister(void); 332 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 333 struct drm_encoder *encoder); 334 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 335 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 336 337 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 338 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 339 340 #else 341 static inline int __init msm_dp_register(void) 342 { 343 return -EINVAL; 344 } 345 static inline void __exit msm_dp_unregister(void) 346 { 347 } 348 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 349 struct drm_device *dev, 350 struct drm_encoder *encoder) 351 { 352 return -EINVAL; 353 } 354 355 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 356 { 357 } 358 359 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 360 { 361 } 362 363 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 364 struct drm_minor *minor) 365 { 366 } 367 368 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 369 { 370 return false; 371 } 372 373 #endif 374 375 #ifdef CONFIG_DRM_MSM_MDP4 376 void msm_mdp4_register(void); 377 void msm_mdp4_unregister(void); 378 #else 379 static inline void msm_mdp4_register(void) {} 380 static inline void msm_mdp4_unregister(void) {} 381 #endif 382 383 #ifdef CONFIG_DRM_MSM_MDP5 384 void msm_mdp_register(void); 385 void msm_mdp_unregister(void); 386 #else 387 static inline void msm_mdp_register(void) {} 388 static inline void msm_mdp_unregister(void) {} 389 #endif 390 391 #ifdef CONFIG_DRM_MSM_DPU 392 void msm_dpu_register(void); 393 void msm_dpu_unregister(void); 394 #else 395 static inline void msm_dpu_register(void) {} 396 static inline void msm_dpu_unregister(void) {} 397 #endif 398 399 #ifdef CONFIG_DRM_MSM_MDSS 400 void msm_mdss_register(void); 401 void msm_mdss_unregister(void); 402 #else 403 static inline void msm_mdss_register(void) {} 404 static inline void msm_mdss_unregister(void) {} 405 #endif 406 407 #ifdef CONFIG_DEBUG_FS 408 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 409 int msm_debugfs_late_init(struct drm_device *dev); 410 int msm_rd_debugfs_init(struct drm_minor *minor); 411 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 412 __printf(3, 4) 413 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 414 const char *fmt, ...); 415 int msm_perf_debugfs_init(struct drm_minor *minor); 416 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 417 #else 418 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 419 __printf(3, 4) 420 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 421 struct msm_gem_submit *submit, 422 const char *fmt, ...) {} 423 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 424 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 425 #endif 426 427 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 428 429 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 430 const char *name); 431 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 432 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 433 phys_addr_t *size); 434 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 435 436 #define msm_writel(data, addr) writel((data), (addr)) 437 #define msm_readl(addr) readl((addr)) 438 439 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 440 { 441 u32 val = msm_readl(addr); 442 443 val &= ~mask; 444 msm_writel(val | or, addr); 445 } 446 447 /** 448 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 449 * 450 * @timer: hrtimer to control when the kthread work is triggered 451 * @work: the kthread work 452 * @worker: the kthread worker the work will be scheduled on 453 */ 454 struct msm_hrtimer_work { 455 struct hrtimer timer; 456 struct kthread_work work; 457 struct kthread_worker *worker; 458 }; 459 460 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 461 ktime_t wakeup_time, 462 enum hrtimer_mode mode); 463 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 464 struct kthread_worker *worker, 465 kthread_work_func_t fn, 466 clockid_t clock_id, 467 enum hrtimer_mode mode); 468 469 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 470 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 471 472 static inline int align_pitch(int width, int bpp) 473 { 474 int bytespp = (bpp + 7) / 8; 475 /* adreno needs pitch aligned to 32 pixels: */ 476 return bytespp * ALIGN(width, 32); 477 } 478 479 /* for the generated headers: */ 480 #define INVALID_IDX(idx) ({BUG(); 0;}) 481 #define fui(x) ({BUG(); 0;}) 482 #define _mesa_float_to_half(x) ({BUG(); 0;}) 483 484 485 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 486 487 /* for conditionally setting boolean flag(s): */ 488 #define COND(bool, val) ((bool) ? (val) : 0) 489 490 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 491 { 492 ktime_t now = ktime_get(); 493 s64 remaining_jiffies; 494 495 if (ktime_compare(*timeout, now) < 0) { 496 remaining_jiffies = 0; 497 } else { 498 ktime_t rem = ktime_sub(*timeout, now); 499 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 500 } 501 502 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX); 503 } 504 505 /* Driver helpers */ 506 507 extern const struct component_master_ops msm_drm_ops; 508 509 int msm_pm_prepare(struct device *dev); 510 void msm_pm_complete(struct device *dev); 511 512 int msm_drv_probe(struct device *dev, 513 int (*kms_init)(struct drm_device *dev)); 514 void msm_drv_shutdown(struct platform_device *pdev); 515 516 517 #endif /* __MSM_DRV_H__ */ 518