1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/module.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/list.h> 21 #include <linux/iommu.h> 22 #include <linux/types.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_device.h> 25 #include <linux/sizes.h> 26 #include <linux/kthread.h> 27 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 struct msm_kms; 37 struct msm_gpu; 38 struct msm_mmu; 39 struct msm_mdss; 40 struct msm_rd_state; 41 struct msm_perf_state; 42 struct msm_gem_submit; 43 struct msm_fence_context; 44 struct msm_gem_address_space; 45 struct msm_gem_vma; 46 47 #define MAX_CRTCS 8 48 #define MAX_PLANES 20 49 #define MAX_ENCODERS 8 50 #define MAX_BRIDGES 8 51 #define MAX_CONNECTORS 8 52 53 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 54 55 struct msm_file_private { 56 rwlock_t queuelock; 57 struct list_head submitqueues; 58 int queueid; 59 struct msm_gem_address_space *aspace; 60 }; 61 62 enum msm_mdp_plane_property { 63 PLANE_PROP_ZPOS, 64 PLANE_PROP_ALPHA, 65 PLANE_PROP_PREMULTIPLIED, 66 PLANE_PROP_MAX_NUM 67 }; 68 69 #define MSM_GPU_MAX_RINGS 4 70 #define MAX_H_TILES_PER_DISPLAY 2 71 72 /** 73 * enum msm_display_caps - features/capabilities supported by displays 74 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported 75 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported 76 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported 77 * @MSM_DISPLAY_CAP_EDID: EDID supported 78 */ 79 enum msm_display_caps { 80 MSM_DISPLAY_CAP_VID_MODE = BIT(0), 81 MSM_DISPLAY_CAP_CMD_MODE = BIT(1), 82 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2), 83 MSM_DISPLAY_CAP_EDID = BIT(3), 84 }; 85 86 /** 87 * enum msm_event_wait - type of HW events to wait for 88 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 89 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 90 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 91 */ 92 enum msm_event_wait { 93 MSM_ENC_COMMIT_DONE = 0, 94 MSM_ENC_TX_COMPLETE, 95 MSM_ENC_VBLANK, 96 }; 97 98 /** 99 * struct msm_display_topology - defines a display topology pipeline 100 * @num_lm: number of layer mixers used 101 * @num_enc: number of compression encoder blocks used 102 * @num_intf: number of interfaces the panel is mounted on 103 */ 104 struct msm_display_topology { 105 u32 num_lm; 106 u32 num_enc; 107 u32 num_intf; 108 u32 num_dspp; 109 }; 110 111 /** 112 * struct msm_display_info - defines display properties 113 * @intf_type: DRM_MODE_ENCODER_ type 114 * @capabilities: Bitmask of display flags 115 * @num_of_h_tiles: Number of horizontal tiles in case of split interface 116 * @h_tile_instance: Controller instance used per tile. Number of elements is 117 * based on num_of_h_tiles 118 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is 119 * used instead of panel TE in cmd mode panels 120 */ 121 struct msm_display_info { 122 int intf_type; 123 uint32_t capabilities; 124 uint32_t num_of_h_tiles; 125 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; 126 bool is_te_using_watchdog_timer; 127 }; 128 129 /* Commit/Event thread specific structure */ 130 struct msm_drm_thread { 131 struct drm_device *dev; 132 struct task_struct *thread; 133 unsigned int crtc_id; 134 struct kthread_worker worker; 135 }; 136 137 struct msm_drm_private { 138 139 struct drm_device *dev; 140 141 struct msm_kms *kms; 142 143 /* subordinate devices, if present: */ 144 struct platform_device *gpu_pdev; 145 146 /* top level MDSS wrapper device (for MDP5/DPU only) */ 147 struct msm_mdss *mdss; 148 149 /* possibly this should be in the kms component, but it is 150 * shared by both mdp4 and mdp5.. 151 */ 152 struct hdmi *hdmi; 153 154 /* eDP is for mdp5 only, but kms has not been created 155 * when edp_bind() and edp_init() are called. Here is the only 156 * place to keep the edp instance. 157 */ 158 struct msm_edp *edp; 159 160 /* DSI is shared by mdp4 and mdp5 */ 161 struct msm_dsi *dsi[2]; 162 163 /* when we have more than one 'msm_gpu' these need to be an array: */ 164 struct msm_gpu *gpu; 165 struct msm_file_private *lastctx; 166 /* gpu is only set on open(), but we need this info earlier */ 167 bool is_a2xx; 168 169 struct drm_fb_helper *fbdev; 170 171 struct msm_rd_state *rd; /* debugfs to dump all submits */ 172 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 173 struct msm_perf_state *perf; 174 175 /* list of GEM objects: */ 176 struct list_head inactive_list; 177 178 /* worker for delayed free of objects: */ 179 struct work_struct free_work; 180 struct llist_head free_list; 181 182 struct workqueue_struct *wq; 183 184 unsigned int num_planes; 185 struct drm_plane *planes[MAX_PLANES]; 186 187 unsigned int num_crtcs; 188 struct drm_crtc *crtcs[MAX_CRTCS]; 189 190 struct msm_drm_thread event_thread[MAX_CRTCS]; 191 192 unsigned int num_encoders; 193 struct drm_encoder *encoders[MAX_ENCODERS]; 194 195 unsigned int num_bridges; 196 struct drm_bridge *bridges[MAX_BRIDGES]; 197 198 unsigned int num_connectors; 199 struct drm_connector *connectors[MAX_CONNECTORS]; 200 201 /* Properties */ 202 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 203 204 /* VRAM carveout, used when no IOMMU: */ 205 struct { 206 unsigned long size; 207 dma_addr_t paddr; 208 /* NOTE: mm managed at the page level, size is in # of pages 209 * and position mm_node->start is in # of pages: 210 */ 211 struct drm_mm mm; 212 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 213 } vram; 214 215 struct notifier_block vmap_notifier; 216 struct shrinker shrinker; 217 218 struct drm_atomic_state *pm_state; 219 }; 220 221 struct msm_format { 222 uint32_t pixel_format; 223 }; 224 225 struct msm_pending_timer; 226 227 int msm_atomic_prepare_fb(struct drm_plane *plane, 228 struct drm_plane_state *new_state); 229 void msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 230 struct msm_kms *kms, int crtc_idx); 231 void msm_atomic_commit_tail(struct drm_atomic_state *state); 232 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 233 void msm_atomic_state_clear(struct drm_atomic_state *state); 234 void msm_atomic_state_free(struct drm_atomic_state *state); 235 236 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 237 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 238 239 int msm_gem_init_vma(struct msm_gem_address_space *aspace, 240 struct msm_gem_vma *vma, int npages, 241 u64 range_start, u64 range_end); 242 void msm_gem_purge_vma(struct msm_gem_address_space *aspace, 243 struct msm_gem_vma *vma); 244 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, 245 struct msm_gem_vma *vma); 246 int msm_gem_map_vma(struct msm_gem_address_space *aspace, 247 struct msm_gem_vma *vma, int prot, 248 struct sg_table *sgt, int npages); 249 void msm_gem_close_vma(struct msm_gem_address_space *aspace, 250 struct msm_gem_vma *vma); 251 252 void msm_gem_address_space_put(struct msm_gem_address_space *aspace); 253 254 struct msm_gem_address_space * 255 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name, 256 u64 va_start, u64 size); 257 258 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 259 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 260 261 bool msm_use_mmu(struct drm_device *dev); 262 263 void msm_gem_submit_free(struct msm_gem_submit *submit); 264 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 265 struct drm_file *file); 266 267 void msm_gem_shrinker_init(struct drm_device *dev); 268 void msm_gem_shrinker_cleanup(struct drm_device *dev); 269 270 int msm_gem_mmap_obj(struct drm_gem_object *obj, 271 struct vm_area_struct *vma); 272 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 273 vm_fault_t msm_gem_fault(struct vm_fault *vmf); 274 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 275 int msm_gem_get_iova(struct drm_gem_object *obj, 276 struct msm_gem_address_space *aspace, uint64_t *iova); 277 int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj, 278 struct msm_gem_address_space *aspace, uint64_t *iova, 279 u64 range_start, u64 range_end); 280 int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, 281 struct msm_gem_address_space *aspace, uint64_t *iova); 282 uint64_t msm_gem_iova(struct drm_gem_object *obj, 283 struct msm_gem_address_space *aspace); 284 void msm_gem_unpin_iova(struct drm_gem_object *obj, 285 struct msm_gem_address_space *aspace); 286 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 287 void msm_gem_put_pages(struct drm_gem_object *obj); 288 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 289 struct drm_mode_create_dumb *args); 290 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 291 uint32_t handle, uint64_t *offset); 292 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 293 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 294 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 295 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 296 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 297 struct dma_buf_attachment *attach, struct sg_table *sg); 298 int msm_gem_prime_pin(struct drm_gem_object *obj); 299 void msm_gem_prime_unpin(struct drm_gem_object *obj); 300 void *msm_gem_get_vaddr(struct drm_gem_object *obj); 301 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj); 302 void msm_gem_put_vaddr(struct drm_gem_object *obj); 303 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv); 304 int msm_gem_sync_object(struct drm_gem_object *obj, 305 struct msm_fence_context *fctx, bool exclusive); 306 void msm_gem_move_to_active(struct drm_gem_object *obj, 307 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence); 308 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 309 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 310 int msm_gem_cpu_fini(struct drm_gem_object *obj); 311 void msm_gem_free_object(struct drm_gem_object *obj); 312 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 313 uint32_t size, uint32_t flags, uint32_t *handle, char *name); 314 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 315 uint32_t size, uint32_t flags); 316 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, 317 uint32_t size, uint32_t flags); 318 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, 319 uint32_t flags, struct msm_gem_address_space *aspace, 320 struct drm_gem_object **bo, uint64_t *iova); 321 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, 322 uint32_t flags, struct msm_gem_address_space *aspace, 323 struct drm_gem_object **bo, uint64_t *iova); 324 void msm_gem_kernel_put(struct drm_gem_object *bo, 325 struct msm_gem_address_space *aspace, bool locked); 326 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 327 struct dma_buf *dmabuf, struct sg_table *sgt); 328 void msm_gem_free_work(struct work_struct *work); 329 330 __printf(2, 3) 331 void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...); 332 333 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 334 struct msm_gem_address_space *aspace); 335 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 336 struct msm_gem_address_space *aspace); 337 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 338 struct msm_gem_address_space *aspace, int plane); 339 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 340 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 341 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 342 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 343 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 344 int w, int h, int p, uint32_t format); 345 346 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 347 void msm_fbdev_free(struct drm_device *dev); 348 349 struct hdmi; 350 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 351 struct drm_encoder *encoder); 352 void __init msm_hdmi_register(void); 353 void __exit msm_hdmi_unregister(void); 354 355 struct msm_edp; 356 void __init msm_edp_register(void); 357 void __exit msm_edp_unregister(void); 358 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 359 struct drm_encoder *encoder); 360 361 struct msm_dsi; 362 #ifdef CONFIG_DRM_MSM_DSI 363 void __init msm_dsi_register(void); 364 void __exit msm_dsi_unregister(void); 365 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 366 struct drm_encoder *encoder); 367 #else 368 static inline void __init msm_dsi_register(void) 369 { 370 } 371 static inline void __exit msm_dsi_unregister(void) 372 { 373 } 374 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 375 struct drm_device *dev, 376 struct drm_encoder *encoder) 377 { 378 return -EINVAL; 379 } 380 #endif 381 382 void __init msm_mdp_register(void); 383 void __exit msm_mdp_unregister(void); 384 void __init msm_dpu_register(void); 385 void __exit msm_dpu_unregister(void); 386 387 #ifdef CONFIG_DEBUG_FS 388 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 389 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 390 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 391 int msm_debugfs_late_init(struct drm_device *dev); 392 int msm_rd_debugfs_init(struct drm_minor *minor); 393 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 394 __printf(3, 4) 395 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 396 const char *fmt, ...); 397 int msm_perf_debugfs_init(struct drm_minor *minor); 398 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 399 #else 400 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 401 __printf(3, 4) 402 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 403 const char *fmt, ...) {} 404 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 405 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 406 #endif 407 408 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 409 410 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 411 const char *name); 412 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 413 const char *dbgname); 414 void msm_writel(u32 data, void __iomem *addr); 415 u32 msm_readl(const void __iomem *addr); 416 417 struct msm_gpu_submitqueue; 418 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); 419 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, 420 u32 id); 421 int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx, 422 u32 prio, u32 flags, u32 *id); 423 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, 424 struct drm_msm_submitqueue_query *args); 425 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); 426 void msm_submitqueue_close(struct msm_file_private *ctx); 427 428 void msm_submitqueue_destroy(struct kref *kref); 429 430 431 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 432 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 433 434 static inline int align_pitch(int width, int bpp) 435 { 436 int bytespp = (bpp + 7) / 8; 437 /* adreno needs pitch aligned to 32 pixels: */ 438 return bytespp * ALIGN(width, 32); 439 } 440 441 /* for the generated headers: */ 442 #define INVALID_IDX(idx) ({BUG(); 0;}) 443 #define fui(x) ({BUG(); 0;}) 444 #define util_float_to_half(x) ({BUG(); 0;}) 445 446 447 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 448 449 /* for conditionally setting boolean flag(s): */ 450 #define COND(bool, val) ((bool) ? (val) : 0) 451 452 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 453 { 454 ktime_t now = ktime_get(); 455 unsigned long remaining_jiffies; 456 457 if (ktime_compare(*timeout, now) < 0) { 458 remaining_jiffies = 0; 459 } else { 460 ktime_t rem = ktime_sub(*timeout, now); 461 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 462 } 463 464 return remaining_jiffies; 465 } 466 467 #endif /* __MSM_DRV_H__ */ 468