1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRV_H__ 19 #define __MSM_DRV_H__ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/module.h> 25 #include <linux/component.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/list.h> 31 #include <linux/iommu.h> 32 #include <linux/types.h> 33 #include <asm/sizes.h> 34 35 36 #if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_QCOM) 37 /* stubs we need for compile-test: */ 38 static inline struct device *msm_iommu_get_ctx(const char *ctx_name) 39 { 40 return NULL; 41 } 42 #endif 43 44 #ifndef CONFIG_OF 45 #include <mach/board.h> 46 #include <mach/socinfo.h> 47 #include <mach/iommu_domains.h> 48 #endif 49 50 #include <drm/drmP.h> 51 #include <drm/drm_crtc_helper.h> 52 #include <drm/drm_fb_helper.h> 53 #include <drm/msm_drm.h> 54 55 struct msm_kms; 56 struct msm_gpu; 57 struct msm_mmu; 58 struct msm_rd_state; 59 struct msm_perf_state; 60 struct msm_gem_submit; 61 62 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 63 64 struct msm_file_private { 65 /* currently we don't do anything useful with this.. but when 66 * per-context address spaces are supported we'd keep track of 67 * the context's page-tables here. 68 */ 69 int dummy; 70 }; 71 72 struct msm_drm_private { 73 74 struct msm_kms *kms; 75 76 /* subordinate devices, if present: */ 77 struct platform_device *hdmi_pdev, *gpu_pdev; 78 79 /* when we have more than one 'msm_gpu' these need to be an array: */ 80 struct msm_gpu *gpu; 81 struct msm_file_private *lastctx; 82 83 struct drm_fb_helper *fbdev; 84 85 uint32_t next_fence, completed_fence; 86 wait_queue_head_t fence_event; 87 88 struct msm_rd_state *rd; 89 struct msm_perf_state *perf; 90 91 /* list of GEM objects: */ 92 struct list_head inactive_list; 93 94 struct workqueue_struct *wq; 95 96 /* callbacks deferred until bo is inactive: */ 97 struct list_head fence_cbs; 98 99 /* registered MMUs: */ 100 unsigned int num_mmus; 101 struct msm_mmu *mmus[NUM_DOMAINS]; 102 103 unsigned int num_planes; 104 struct drm_plane *planes[8]; 105 106 unsigned int num_crtcs; 107 struct drm_crtc *crtcs[8]; 108 109 unsigned int num_encoders; 110 struct drm_encoder *encoders[8]; 111 112 unsigned int num_bridges; 113 struct drm_bridge *bridges[8]; 114 115 unsigned int num_connectors; 116 struct drm_connector *connectors[8]; 117 118 /* VRAM carveout, used when no IOMMU: */ 119 struct { 120 unsigned long size; 121 dma_addr_t paddr; 122 /* NOTE: mm managed at the page level, size is in # of pages 123 * and position mm_node->start is in # of pages: 124 */ 125 struct drm_mm mm; 126 } vram; 127 }; 128 129 struct msm_format { 130 uint32_t pixel_format; 131 }; 132 133 /* callback from wq once fence has passed: */ 134 struct msm_fence_cb { 135 struct work_struct work; 136 uint32_t fence; 137 void (*func)(struct msm_fence_cb *cb); 138 }; 139 140 void __msm_fence_worker(struct work_struct *work); 141 142 #define INIT_FENCE_CB(_cb, _func) do { \ 143 INIT_WORK(&(_cb)->work, __msm_fence_worker); \ 144 (_cb)->func = _func; \ 145 } while (0) 146 147 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 148 149 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, 150 struct timespec *timeout); 151 void msm_update_fence(struct drm_device *dev, uint32_t fence); 152 153 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 154 struct drm_file *file); 155 156 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 157 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 158 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 159 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 160 uint32_t *iova); 161 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 162 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 163 void msm_gem_put_pages(struct drm_gem_object *obj); 164 void msm_gem_put_iova(struct drm_gem_object *obj, int id); 165 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 166 struct drm_mode_create_dumb *args); 167 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 168 uint32_t handle, uint64_t *offset); 169 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 170 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 171 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 172 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 173 size_t size, struct sg_table *sg); 174 int msm_gem_prime_pin(struct drm_gem_object *obj); 175 void msm_gem_prime_unpin(struct drm_gem_object *obj); 176 void *msm_gem_vaddr_locked(struct drm_gem_object *obj); 177 void *msm_gem_vaddr(struct drm_gem_object *obj); 178 int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, 179 struct msm_fence_cb *cb); 180 void msm_gem_move_to_active(struct drm_gem_object *obj, 181 struct msm_gpu *gpu, bool write, uint32_t fence); 182 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 183 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, 184 struct timespec *timeout); 185 int msm_gem_cpu_fini(struct drm_gem_object *obj); 186 void msm_gem_free_object(struct drm_gem_object *obj); 187 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 188 uint32_t size, uint32_t flags, uint32_t *handle); 189 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 190 uint32_t size, uint32_t flags); 191 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 192 uint32_t size, struct sg_table *sgt); 193 194 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 195 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 196 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 197 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 198 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 199 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd); 200 201 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 202 203 struct hdmi; 204 struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder); 205 irqreturn_t hdmi_irq(int irq, void *dev_id); 206 void __init hdmi_register(void); 207 void __exit hdmi_unregister(void); 208 209 #ifdef CONFIG_DEBUG_FS 210 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 211 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 212 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 213 int msm_debugfs_late_init(struct drm_device *dev); 214 int msm_rd_debugfs_init(struct drm_minor *minor); 215 void msm_rd_debugfs_cleanup(struct drm_minor *minor); 216 void msm_rd_dump_submit(struct msm_gem_submit *submit); 217 int msm_perf_debugfs_init(struct drm_minor *minor); 218 void msm_perf_debugfs_cleanup(struct drm_minor *minor); 219 #else 220 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 221 static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} 222 #endif 223 224 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 225 const char *dbgname); 226 void msm_writel(u32 data, void __iomem *addr); 227 u32 msm_readl(const void __iomem *addr); 228 229 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 230 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 231 232 static inline bool fence_completed(struct drm_device *dev, uint32_t fence) 233 { 234 struct msm_drm_private *priv = dev->dev_private; 235 return priv->completed_fence >= fence; 236 } 237 238 static inline int align_pitch(int width, int bpp) 239 { 240 int bytespp = (bpp + 7) / 8; 241 /* adreno needs pitch aligned to 32 pixels: */ 242 return bytespp * ALIGN(width, 32); 243 } 244 245 /* for the generated headers: */ 246 #define INVALID_IDX(idx) ({BUG(); 0;}) 247 #define fui(x) ({BUG(); 0;}) 248 #define util_float_to_half(x) ({BUG(); 0;}) 249 250 251 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 252 253 /* for conditionally setting boolean flag(s): */ 254 #define COND(bool, val) ((bool) ? (val) : 0) 255 256 257 #endif /* __MSM_DRV_H__ */ 258